CN108063097A - A kind of three layers of integrated chip method - Google Patents
A kind of three layers of integrated chip method Download PDFInfo
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- CN108063097A CN108063097A CN201711378869.XA CN201711378869A CN108063097A CN 108063097 A CN108063097 A CN 108063097A CN 201711378869 A CN201711378869 A CN 201711378869A CN 108063097 A CN108063097 A CN 108063097A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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Abstract
The present invention provides a kind of three layers of integrated chip method, wherein, first substrate with the first metal interconnecting layer, one the second substrate and the 3rd substrate with the 3rd metal interconnecting layer with the second metal interconnecting layer are provided, comprised the following steps：First bonding face of the first substrate and the second bonding face of the second substrate carry out hybrid bonded after being oppositely arranged；To second the first predetermined thickness of substrate thinning；The position of corresponding second metal interconnecting layer carries out the extraction of the first metal wire in the second substrate, draws the face of the first metal wire as fourth bond face；The third bond face in fourth bond face and the 3rd substrate to the second substrate carries out hybrid bonded；To the 3rd the second predetermined thickness of substrate thinning；The position of corresponding 3rd metal interconnecting layer carries out the extraction of the second metal wire in the 3rd substrate, and forms a SiN layer in the 3rd substrate surface；Advantageous effect：Three layers of integrated chip can be realized, so as to improve device performance and integrated level.
Description
Technical field
The present invention relates to integrated chip manufacturing field more particularly to a kind of three layers of integrated chip methods.
Background technology
Current three dimensional integrated circuits (3D-IC) technology is by silicon perforation or hybrid bonded by two different chips
It is integrated, although having reached the raising of integrated device performance.But with the development of science and technology, people are to device performance and integrated level
Requirement it is higher and higher, layers of chips, which integrates, cannot meet the needs of increasingly expanding.
The content of the invention
In view of the above-mentioned problems, the present invention provides a kind of three layers of integrated chip method, wherein, providing one has the first metal
The 3rd lining of first substrate of interconnection layer, one the second substrate and one with the second metal interconnecting layer with the 3rd metal interconnecting layer
Bottom comprises the following steps：
Second bonding face of step S1, the first bonding face of first substrate and second substrate is oppositely arranged laggard
Row is hybrid bonded；
Step S2, to first predetermined thickness of the second substrate thinning；
Step S3, the position that second metal interconnecting layer is corresponded in second substrate carry out drawing for the first metal wire
Go out, draw the face of first metal wire as fourth bond face；
Step S4, the third bond face in the fourth bond face and the 3rd substrate to second substrate are mixed
Close bonding；
Step S5, to the second predetermined thickness of the 3rd substrate thinning；
Step S6, the position that the 3rd metal interconnecting layer is corresponded in the 3rd substrate carry out drawing for the second metal wire
Go out, and a SiN layer is formed in the 3rd substrate surface.
Wherein, during hybrid bonded in the step S1, first substrate is located at below second substrate, and described
First metal interconnecting layer is directed at second metal interconnecting layer.
Wherein, the extraction of metal wire comprises the following steps described in the step S3：
Step S31, the position that second metal interconnecting layer is corresponded in second substrate form contact hole；
Step S32, in filling a metal layer in the contact hole；
Step S33 is ground the metal layer, until exposing second substrate.
Wherein, in the step S4 it is hybrid bonded be by the 3rd substrate the 3rd metal interconnecting layer be aligned
First metal wire, is then bonded.
Wherein, first metal interconnecting layer is using one or more in copper, nickel, tin, sn-ag alloy, Tin Silver Copper Alloy
Combination.
Wherein, in the step S6, the extraction of second metal wire uses silicon perforation technique.
Advantageous effect：Using this method, three layers of integrated chip can be realized, so as to improve device performance and integrated level.
Description of the drawings
The structure diagram that each step of the invention of Fig. 1~6 is formed；
Fig. 7 flow charts of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained on the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
It should be noted that in the case where there is no conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
In a preferred embodiment, as shown in Figure 7, it is proposed that a kind of three layers of integrated chip method, wherein, provide one
Second substrate 2 and one of the first substrate 1, one with the first metal interconnecting layer 11 with the second metal interconnecting layer 21 is with the 3rd
3rd substrate 3 of metal interconnecting layer 31, comprises the following steps：
After second bonding face of step S1, the first bonding face of first substrate 1 and second substrate 2 is oppositely arranged
It carries out hybrid bonded；
The first predetermined thickness is thinned to second substrate 2 in step S2；
Step S3, the position that second metal interconnecting layer 21 is corresponded in second substrate 2 carry out the first metal wire
Extraction, draw the face of first metal wire as fourth bond face；
Step S4, the third bond face in the fourth bond face and the 3rd substrate 3 to second substrate 2 carry out
It is hybrid bonded；
The second predetermined thickness is thinned to the 3rd substrate 3 in step S5；
Step S6, the position that the 3rd metal interconnecting layer 31 is corresponded in the 3rd substrate 3 carry out the second metal wire
32 extraction, and form a SiN layer 4 in the 3rd substrate surface.
In above-mentioned technical proposal, while chip volume is kept, the extensive function of improving chip, from one single chip
The limitation of manufacturing process；The metal interconnection between functional chip is greatly shortened, reduces fever, power consumption and delay etc..Significantly
The bandwidth between function module is improved,
In a preferred embodiment, the first metal interconnecting layer 11 of the first substrate 1 is directed at the second of the second substrate 2
Metal interconnecting layer 21, carry out two substrates between it is hybrid bonded, obtain structure as shown in Figure 1.
In a preferred embodiment, it is a degree of to the bottom surface progress of the second substrate 2 to be thinned, it obtains such as Fig. 2 institutes
The structure shown.
In a preferred embodiment, laser drill or deep reaction are used in 2 bottom surface of the second substrate after being thinned
Ion etching forms contact hole.
Next, depositing an insulating layer, a barrier layer, a Seed Layer in contact hole, then, plating metal is filled out, it is ground
After form the first metal wire 22, structure diagram is as shown in Figure 3.
In a preferred embodiment, the 3rd metal interconnecting layer 31 in the 3rd substrate 3 is aligned in previous step and is formed
The first metal wire 22, carry out the hybrid bonded of the 3rd substrate 3 and the second substrate 2, form structure as shown in Figure 4.
In a preferred embodiment, it is a degree of to the progress of 3 bottom of the 3rd substrate to be thinned, it obtains as shown in Figure 5
Structure.
In a preferred embodiment, by silicon perforation technique, corresponding 3rd metal interconnecting layer 31 in the 3rd substrate 3
Position formed contact hole.
It is identical when then, with forming the first metal wire 22, an insulating layer, a barrier layer, a seed are deposited in contact hole
Layer then, fills out plating metal, the second metal wire 32 of polished formation.
Finally, a SiN layer 4 is formed on surface, forms structure as shown in Figure 6.
In above-mentioned technical proposal, the conventional skill in the technical field may be employed for the bonding between layers of chips substrate
Art.For such conventional technical means, no longer it is described in detail in this specification.
The foregoing is merely preferred embodiments of the present invention, not thereby limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent substitution and obviously change obtained scheme, should all include within the scope of the present invention.
Claims (6)
- A kind of 1. three layers of integrated chip method, which is characterized in that providing one has the first substrate of the first metal interconnecting layer, a tool There is the second substrate of the second metal interconnecting layer and one that there is the 3rd substrate of the 3rd metal interconnecting layer, comprise the following steps：Second bonding face of step S1, the first bonding face of first substrate and second substrate is mixed after being oppositely arranged Close bonding；Step S2, to first predetermined thickness of the second substrate thinning；Step S3, the position that second metal interconnecting layer is corresponded in second substrate carry out the extraction of the first metal wire, The face of first metal wire is drawn as fourth bond face；Step S4, the third bond face in the fourth bond face and the 3rd substrate to second substrate carry out mixing key It closes；Step S5, to the second predetermined thickness of the 3rd substrate thinning；Step S6, the position that the 3rd metal interconnecting layer is corresponded in the 3rd substrate carry out the extraction of the second metal wire, And form a SiN layer in the 3rd substrate surface.
- 2. according to the method described in claim 1, it is characterized in that, during hybrid bonded in the step S1, first lining Bottom is located at below second substrate, and first metal interconnecting layer is directed at second metal interconnecting layer.
- 3. according to the method described in claim 1, it is characterized in that, the extraction of metal wire described in the step S3 is including following Step：Step S31, the position that second metal interconnecting layer is corresponded in second substrate form contact hole；Step S32, in filling a metal layer in the contact hole；Step S33 is ground the metal layer, until exposing second substrate.
- 4. according to the method described in claim 1, it is characterized in that, in the step S4 it is hybrid bonded be will the described 3rd serve as a contrast The 3rd metal interconnecting layer in bottom is directed at first metal wire, is then bonded.
- 5. according to the method described in claim 1, it is characterized in that, first metal interconnecting layer is using copper, nickel, tin, Xi Yin One or more combination in alloy, Tin Silver Copper Alloy.
- 6. according to the method described in claim 1, it is characterized in that, in the step S6, the extraction of second metal wire makes With silicon perforation technique.
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| CN201711378869.XA CN108063097A (en) | 2017-12-19 | 2017-12-19 | A kind of three layers of integrated chip method |
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| CN201711378869.XA CN108063097A (en) | 2017-12-19 | 2017-12-19 | A kind of three layers of integrated chip method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110192269A (en) * | 2019-04-15 | 2019-08-30 | 长江存储科技有限责任公司 | Three dimensional NAND memory part is integrated with multiple functional chips |
| CN110838481A (en) * | 2018-08-15 | 2020-02-25 | 台湾积体电路制造股份有限公司 | Hybrid bonding techniques for stacked integrated circuits |
| CN113488505A (en) * | 2019-04-30 | 2021-10-08 | 长江存储科技有限责任公司 | Three-dimensional memory device with three-dimensional phase change memory |
| US11158604B2 (en) | 2019-04-15 | 2021-10-26 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
| US11367729B2 (en) | 2019-04-30 | 2022-06-21 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and NAND flash memory and methods for forming the same |
| US11430766B2 (en) | 2019-04-15 | 2022-08-30 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
| US11694993B2 (en) | 2019-04-15 | 2023-07-04 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11322481B2 (en) | 2018-08-15 | 2022-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding technology for stacking integrated circuits |
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| US11694993B2 (en) | 2019-04-15 | 2023-07-04 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
| US11749641B2 (en) | 2019-04-15 | 2023-09-05 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
| US11158604B2 (en) | 2019-04-15 | 2021-10-26 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
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| US12002788B2 (en) | 2019-04-15 | 2024-06-04 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
| WO2020211271A1 (en) * | 2019-04-15 | 2020-10-22 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
| US11430766B2 (en) | 2019-04-15 | 2022-08-30 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
| US11923339B2 (en) | 2019-04-15 | 2024-03-05 | Yangtze Memory Technologies Co., Ltd. | Integration of three-dimensional NAND memory devices with multiple functional chips |
| US11562985B2 (en) | 2019-04-15 | 2023-01-24 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
| CN110192269A (en) * | 2019-04-15 | 2019-08-30 | 长江存储科技有限责任公司 | Three dimensional NAND memory part is integrated with multiple functional chips |
| US11367729B2 (en) | 2019-04-30 | 2022-06-21 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and NAND flash memory and methods for forming the same |
| US11864367B2 (en) | 2019-04-30 | 2024-01-02 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and NAND flash memory and methods for forming the same |
| CN113488505B (en) * | 2019-04-30 | 2022-09-30 | 长江存储科技有限责任公司 | Three-dimensional memory device with three-dimensional phase change memory |
| CN113488505A (en) * | 2019-04-30 | 2021-10-08 | 长江存储科技有限责任公司 | Three-dimensional memory device with three-dimensional phase change memory |
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Application publication date: 20180522 |