A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（） 5-1發明領域： 本發明係有關於一種半導體製程，特別是有關於一 種自行對準接觸窗之形成方法’該方法係利用反自行對準 接觸窗蝕刻製程（Reverse SAC Etch Process)。 5-2發明背景： 由於半導體製程不斷之進展’製程之線寬已可以達 致非常窄之範圍’積體電路製程中將會涉及到金屬内連線 與元件主動區之間電性連繫之接觸窗之製作方法，在製造 積體電路時’接觸窗一般而言為使用姓刻製程將一介電層 利用一光阻做為钱刻罩幕形成一窗口以曝露元件之主動 區’因此提供元件主動區與後續内連線膜層之電性傳導之 路徑。 一般傳統定義自行對準接觸窗（self alig n contact ; SAC)之結構如第一圖所示，於半導體基材1上具有場氧 化區域3、墊氧化層5及複晶矽層7之結構，該複晶珍層 7之頂部表面則沈積一層二氧化矽之遮蓋層9，此複晶石夕 層7之側壁間隙壁（side wall spacer) 1 3以二氧化石夕戶斤級 成，第一圖中標號11為主動區，形成於各元件之間，# 號3為場氧化層作為主動區間之阻隔，沈積於各元件矣 之上的為内層介電層（inter -layer dielectric ;丨LD)15作五 -2- 私紙張尺度適用中國國家標率（QNS)八4規格（21OX297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝- ο 訂f · 線 '劈難^A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (5-1) Field of the Invention: The present invention relates to a semiconductor process, and particularly to a method for forming a self-aligned contact window. Reverse SAC Etch Process. 5-2 Background of the Invention: Due to the continuous progress of the semiconductor process, the line width of the process can reach a very narrow range. The integrated circuit process will involve the electrical connection between the metal interconnects and the active area of the component. The manufacturing method of the contact window, when manufacturing integrated circuits, the 'contact window is generally a lasting process using a dielectric layer using a photoresist as a money engraved screen to form a window to expose the active area of the component', thus providing The path of electrical conduction between the active area of the device and the subsequent interconnect film. Generally, the structure of a self-aligned contact window (SAC) is generally defined as shown in the first figure, and has a structure of a field oxide region 3, a pad oxide layer 5 and a polycrystalline silicon layer 7 on a semiconductor substrate 1. A silicon dioxide covering layer 9 is deposited on the top surface of the polycrystalline layer 7. The side wall spacers 1 of the polycrystalline stone layer 7 are made of dioxide dioxide. First, In the figure, reference numeral 11 is an active region, which is formed between the elements, # 3 is a field oxide layer as a barrier of the active region, and an inter-layer dielectric (LD) is deposited on each element. 15 work five -2- private paper standards apply China National Standards (QNS) 8 4 specifications (21OX297 mm) (Please read the precautions on the back before filling this page) Installation-ο Order f · Line 'Chang difficult ^
五、發明説明（ 編 經濟部中央標隼局員工消费合作社印製 ::後續沈積之膜層與基材之功用，上 與遮蓋層9是為防止後績沈積與主動區 門隙= 和複晶石夕7間造成短路之功用。 電〖生接觸之膜層 朴習用之方法首先於半導體基材」上形成場氧化區3, 接者沈積墊氧化層5及複晶矽層7於場氧化區3與 上方，在此複晶矽7上方接著沈積二氧化矽層9。、二 阻並蝕刻上述之塾氧化層5與複晶石夕7與二氧化石夕：9开: 成遮蓋層（cap layer),如第一圖所示之結果。下一步驟為 沈積-層二氧切層後以㈣該二氧切層製作側壁間隙 壁1 3。完成側壁間隙壁]3之製作後進行源極、汲極之摻 雜以形成主動區域W。在上述結果之結構表面沈積—層 内層介電層（inter-|ayer die丨ectric; ILD)15並在該内声八 電層（丨LD)15之上定義一光阻圖案17，以非等向性姓;二 .術蝕刻上述之内層介電層15後形成接觸窗19，最後去除 沈積之光阻完成接觸窗之製作，如第二圖所示。 傳統之方法在蝕刻時易造成複晶矽層7和後續沈積 與主動區做電性接觸之膜層間造成短路，主要原因為钮刻 形成接觸窗時，内層介電層1 5與側壁間隙壁彳3之蝕内 選擇比太小’造成側壁間隙壁13被蝕刻或是因過::度餘刻 造成遮蓋層9被蝕刻而暴露出複晶矽層7，為防止可能發 生之短路現象則增加二氧化矽遮蓋層之厚度，但是太厚之 二氧化矽層則使外觀之地形地勢（top0graphy)變差；或是 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝 線V. Description of the invention (edited by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs, printed by: the function of the subsequent deposition of the film and substrate, the upper and cover layers 9 are to prevent later deposition and the active area door gap = and complex crystal The function of causing a short circuit between Shi Xi 7. The conventional method of electrical contact film layer is to first form a field oxide region 3 on a semiconductor substrate, and then deposit a pad oxide layer 5 and a polycrystalline silicon layer 7 in the field oxide region. 3 and above, a silicon dioxide layer 9 is then deposited on top of the polycrystalline silicon 7. The second oxide layer 5 and the polycrystalline silicon oxide 7 and the silicon dioxide silicon oxide are resisted and etched: 9K: forming a cap layer (cap layer), the result shown in the first figure. The next step is to deposit a layer of dioxygen cutting layer and then use the dioxygen cutting layer to make a sidewall spacer 1 3. After completing the sidewall spacer] 3, perform the source electrode. The dopant is doped to form the active region W. On the structured surface of the result described above, an inter-layer dielectric layer (inter- | ayer die 丨 ectric; ILD) 15 is deposited and the internal acoustic eight-layer (丨 LD) 15 A photoresist pattern 17 is defined above, with an anisotropic surname; 2. The above-mentioned inner dielectric layer 15 is etched to form a connection Window 19, and finally remove the deposited photoresist to complete the production of the contact window, as shown in the second figure. The traditional method is easy to cause a short circuit between the polycrystalline silicon layer 7 and the film layer that is in electrical contact with the active area during subsequent deposition. The main reason is that when the contact window is formed by the button engraving, the internal selection ratio of the inner dielectric layer 15 and the side wall gap wall 彳 3 is too small. 9 is etched to expose the polycrystalline silicon layer 7, in order to prevent possible short-circuit phenomenon, the thickness of the silicon dioxide cover layer is increased, but a too thick silicon dioxide layer makes the topography of the appearance worse; or This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)-Loading line
經濟部中央標準局員工消费合作社印製 五、發明説明（） 採用雙層或甚至三層之側壁間隙壁，此做法又造成製程之 複雜性增加。 在自行對準接觸窗製程（SAC)之蝕刻過程中，傳統蝕 刻反應氣體之含C4F8、c〇與二氧化矽反應，製程中將會 產生高分子（polymer)形成於内層介電層1 5之上以增加其 蚀刻選擇性。然而過量之高分子將會造成内層介電層15之 钮刻停止，太少之高分子沈積則會因選擇性太低，造成側 壁間隙壁被蝕刻去除。 因此有必要提出一種方法可避免產生過多高分子產 物而造成蝕刻停止’以及避免側壁間隙壁被過度蝕刻掉而 造成短路現象。 / 5-3發明目的及概述： 本發明之主要目的為提供一種可避免蝕刻停止（etch stop)之自行對準接觸窗（self align contact)之形成方法， 該方法係利用反自行對準接觸窗蝕刻製程（Reverse SAC Etch Process)。 ·: :; 本發明之次一目的為避免側壁間隙壁（side wall spacer)因接觸窗#刻製程過度姓刻（〇veretch)而遭蚀刻， 進而防止複晶矽層間之短路。 (請先閱讀背面之注意事項存填寫本莧) .裝. 『丨訂 線 ο -4- 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -7#? t ΑΊ 五、發明説明（ 本發明利用反自行對準接觸窗蝕刻製程（Reverse SAC Etch Process)以防止複晶矽層與其他祺層間之短路 之自行對準接觸窗（self aijgn c〇ntact)形成方法。其結構 為半導體元，形成於半導體基材上，冑後形成側壁間^壁 於其上，接著先形成作為接觸窗之導電層，然後定義該接 觸窗之後再執行内層介電層之沉積。此即為本發明之特 徵，利用反自行對準接觸窗蝕刻製程，在主動區域上形成 於半導體基材上形成場氧化區後，沈積墊氧化層、 複晶矽層與氮化矽層經蝕刻後形成複晶矽層之主體，接著 =積第ft*化層於上述結果之表面’完成氮化⑦層沈積後 定義光阻蝕刻上述之第一氧化層以形成側壁間隙壁之製 作。沈積一層導電層於基材表面覆蓋場氧化層與氮化矽層 之上，最後定義光阻以蝕刻完成自行對準接觸窗（se|f a|jgn contact)之製作，隨後沉積一内層介電層（丨ld)之後即可接 續進行半導體後續製程。 (請先閲讀背面之注意事項再填寫本頁) Θ --ί — 2---裝.Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () The use of double-layered or even triple-layered side wall partitions has increased the complexity of the manufacturing process. During the self-aligned contact window process (SAC) etching process, the conventional etching reaction gas containing C4F8, co and silicon dioxide react, and a polymer will be formed in the inner dielectric layer 15 during the process. To increase its etch selectivity. However, excessive polymer will cause the button of the inner dielectric layer 15 to stop, and too little polymer deposition will cause the selectivity to be too low, which will cause the side wall gap to be removed by etching. Therefore, it is necessary to propose a method to avoid the etch stop caused by excessive polymer products' and to avoid the short-circuit phenomenon caused by the over-etching of the sidewall spacers. / 5-3 Objects and Summary of the Invention: The main object of the present invention is to provide a method for forming a self-align contact window which can avoid etch stop. The method uses an anti-self-align contact window. Etch Process (Reverse SAC Etch Process). · ::; The second purpose of the present invention is to prevent side wall spacers from being etched due to the over-etching process of the contact window #etching process, thereby preventing short circuits between the polycrystalline silicon layers. (Please read the precautions on the back and fill in this card first). Packing. "丨 Ordering Line ο -4- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -7 #? T ΑΊ 5 2. Description of the invention (The present invention uses a self-aligned contact window (self aijgn coontact) formation method using a reverse SAC Etch process to prevent a short circuit between a polycrystalline silicon layer and other layers. The structure is a semiconductor element, which is formed on a semiconductor substrate, and then a sidewall spacer is formed thereon, and then a conductive layer is formed as a contact window, and then the inner dielectric layer is deposited after defining the contact window. According to a feature of the present invention, an anti-self-aligned contact window etching process is used to form a field oxide region on a semiconductor substrate on an active region, and then a pad oxide layer, a polycrystalline silicon layer, and a silicon nitride layer are formed by etching. The main body of the polycrystalline silicon layer is followed by the formation of the ft * layer on the surface of the above result. After the hafnium nitride layer is deposited, the photoresist is etched to define the first oxide layer to form a sidewall spacer. Layer on the surface of the substrate covering the field oxide layer and the silicon nitride layer, and finally define a photoresist to etch to complete the self-aligned contact window (se | fa | jgn contact), and then deposit an inner dielectric layer (丨 ld ) And then proceed to the subsequent semiconductor manufacturing process. (Please read the precautions on the back before filling out this page) Θ --ί — 2 --- installation.
Γ訂L 之 Θ 丨線丨 經濟部中央橾準局員工消费合作社印裝 打多會。 自過不象 成時現 生窗路 發子觸短 本分接成 高成形 因形層 準 法 方 成 形 窗 觸 止壁 停隙 刻間 蝕壁 成側 造成 而造 次刻 其蝕 程為矽 製點'晶 統優複 傳之出 免明露 避發暴 可本而 |釐 公 7 9 2 經濟部中央標準局員工消贤合作社印製 A7 ·. _____B7五、發明説明（）5-4圈示簡單說明： 第一圖 為傳統定義自行對準接觸窗結構之截面圖。 第二圖 為傳統自行對準接觸窗結構之截面圖。 第三圖 為本發明自行對準接觸窗形成方法中形成閘極 結構之截面圖。 第四圖 為本發明自行對準接觸窗形成方法中形成側壁 間隙壁之截面圖。 第五圖 為本發明自行對準接觸窗形成方法中定義接觸 窗之截面圖。 第六圖 為本發明自行對準接觸窗形成方法中形成自行 對準接觸窗結構之截面圖。 第七圖 為本發明自行對準接觸窗形成方法中形成内層 介電層之截面圖。5-5發明詳細說明： 傳統之自行對準接觸窗製程在形成内建線路介電層 (interlayer dielectric; ILD)覆蓋於主動區之上後’定義 光阻蝕刻該介電層（丨L D)有時會在主動區之側壁間隙壁 (s i d e w a丨丨s p a c e r)上形成開孔或暴露出複晶石夕層；:’並且姓 刻過程中會因較長之過度飯刻造成石夕基材損失’或是因為 /光阻對準不良而將側壁間隙壁蝕刻而暴露出複晶石夕層造成 V 與後續沈積之膜層間之短路現象。為防止可能發生之短路 (請先閲讀背面之注意事項再填莴本頁) 裝---- ^—fn IK·—— 訂L-. 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚) A7 B7 經濟部中央標準局負工消费合作社印製 五、發明説明（） 現象則增加一帽蓋層（cap丨ayer)，或是形成雙層甚至三層 侧壁間隙壁’造成製程之複雜性升高及成本之增加。 如第三圖所示’以一晶面為<1〇〇>之單晶半導體為 基材’如P型單晶之基材2，以傳統之L 0 C 0 S製程製作 一厚的場氧化區4作為主動區域之絕緣物，此場氧化區域 4之形成是在有氧蒸氣之環境下熱氧化，溫度在85〇_1〇5〇 C間產生二氧化矽，厚度為4〇〇〇_6〇〇〇埃。 接著在上述半導體基材上沈積墊氧化層6及一複晶 矽層8覆蓋基材2與場氧化區域4上，該複晶矽層亦可替 換為矽化金屬（silicide)，厚度約為1 800至220〇埃之間， 以化學氣相法沈積。於上述之複晶矽層8表面以化學氣相 法沈積一介電層10覆蓋於該複晶矽層8之上，該介電層 可為TE〇S、氮化矽或氮氧化矽，厚度範圍約為225〇至 2 750埃之間》接著定義第一光阻圖案於該介電層之上， 以姓刻技術蝕刻上述之介電層、上述之複晶矽層及上述之 墊氧化層’此蝕刻可採用乾^刻去除去未被第—光阻覆蓋 之處，形成如第三圖所示之貧氧化層6、複晶矽層8與介 電層1 0，該介電層1 0主要作用為防止複晶矽層8與後續 沈積膜層之間形成短路現象之遮蓋層，最後除去該第一光 阻圖案。 請參考第四圖’以化學氣相沈積形成一氮化梦層於 -7- 本紙張尺度適用中國國家標準（CpS ) A4規格（210x297公赘） (請先閱讀背面之注意事項再填寫本頁)Γ Order L of Θ 丨 Line 丨 Printed by the Consumer Cooperatives of the Central Associated Bureau of the Ministry of Economic Affairs. Since the current generation of the current window is short, the tap is tapped into a high forming factor due to the formation of the quasi-normal square shaped window, the contact wall is stopped, the etching is caused by the side of the etching wall, and the etching process is silicon. The point of “Jing Tong You ’s Reunion” can be avoided to avoid exposure and violence. Centaur 7 9 2 Printed by Axian Cooperative of Employees of the Central Standards Bureau of the Ministry of Economic Affairs A7 ·. _____B7 V. Description of the invention () 5-4 circle Brief description: The first figure is a traditional sectional view of a self-aligned contact window structure. The second figure is a cross-sectional view of a conventional self-aligned contact window structure. The third figure is a sectional view of a gate structure formed in the self-aligned contact window forming method of the present invention. The fourth figure is a cross-sectional view of a side wall and a gap wall formed in the self-aligning contact window forming method of the present invention. The fifth figure is a cross-sectional view of a contact window defined in the self-aligning contact window forming method of the present invention. The sixth figure is a cross-sectional view of a self-aligning contact window forming method in the method for forming a self-aligning contact window of the present invention. The seventh figure is a cross-sectional view of an inner dielectric layer formed in the self-aligned contact window forming method of the present invention. 5-5 Detailed description of the invention: In the traditional self-aligned contact window process, after the built-in interlayer dielectric (ILD) is formed to cover the active area, the photoresist is etched to define the dielectric layer (LD). At the time, an opening will be formed in the side wall of the active area or the polycrystalline stone layer is exposed; 'and the material of the stone material will be lost due to a long excessive meal inscription process' Or, due to poor alignment of the / photoresist, the sidewall spacers are etched to expose the polycrystalline stone layer, causing a short circuit between V and the subsequent deposited film layer. In order to prevent possible short circuit (please read the precautions on the back before filling in the lettuce page) Loading ---- ^ —fn IK · —— Order L-. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification ( 210X297 Gongchu) A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. V. Description of the invention () The phenomenon is to add a cap layer, or to form a double-layer or even a three-layer sidewall gap. The complexity of the process increases and the cost increases. As shown in the third figure, 'using a single crystal semiconductor with a crystal plane of < 100% > as a substrate', such as the substrate 2 of a P-type single crystal, a thick L 0 C 0 S process is used to make a The field oxidized region 4 serves as an insulator of the active region. The formation of the field oxidized region 4 is thermally oxidized in an aerobic vapor environment, and the silicon dioxide is generated at a temperature of 850-1050C with a thickness of 400. 〇_60000 Angstroms. Next, a pad oxide layer 6 and a polycrystalline silicon layer 8 are deposited on the semiconductor substrate to cover the substrate 2 and the field oxidation region 4. The polycrystalline silicon layer can also be replaced with a silicide with a thickness of about 1 800. Between 2200 angstroms, deposited by chemical vapor deposition. A dielectric layer 10 is deposited on the surface of the above-mentioned polycrystalline silicon layer 8 by chemical vapor deposition to cover the polycrystalline silicon layer 8. The dielectric layer may be TEOS, silicon nitride, or silicon oxynitride, with a thickness of The range is about 2250 to 2 750 Angstroms. "Then define the first photoresist pattern on the dielectric layer, and etch the aforementioned dielectric layer, the aforementioned polycrystalline silicon layer, and the aforementioned pad oxide layer using the engraving technique. 'This etching can be removed by dry etching to remove the areas not covered by the first photoresist, forming a poor oxide layer 6, a polycrystalline silicon layer 8 and a dielectric layer 10 as shown in the third figure, and the dielectric layer 1 The main function of 0 is to prevent the formation of a short-circuit covering layer between the polycrystalline silicon layer 8 and the subsequent deposited film layer, and finally remove the first photoresist pattern. Please refer to the fourth picture 'Forming a nitride nitride layer by chemical vapor deposition at -7- This paper size applies to the Chinese National Standard (CpS) A4 specification (210x297). (Please read the precautions on the back before filling this page )
NV |裝| 訂 I xlfz/ .i線 A7 B7 經濟部中央標準局貝工消费合作社印製 五、發明説明（） 該墊氧化層6、該複晶矽層8與該介電層10之上且覆蓋 整個基材。下一步驟為形成侧壁間隙壁（side wall spacer) 1 4之製作，此步驟以蝕刻技術蝕刻該氮化矽層以 形成該氮•化矽層之側壁間隙壁（side wall spacer)14。此 側壁間隙壁1 4之功用如同遮蓋層1 〇之作用是做為防止 複晶石夕層8與後續沈積膜層及形成源極與汲極之主動區域 1 2之間形成短路現象，如第四圖所示。 如第五圖所示，形成一導電層16於上述之基材2、 場氧化區域4、遮蓋層1 0及側壁間隙壁14之上，該導電 層16之厚度約為4000埃至5000埃之間，該導電層16 係用於製作接觸窗之接觸層，可為複晶矽或矽化金屬 (s山cide)等導電材料。隨後，定義一第二光阻圖案18於 該導電層16上，該第二光阻圖案18係用於定義出接觸 窗區域。 請參考第六圊，為本發明自行對準接觸窗形成方法 中形成自行對準接觸窗結構之截面圖。本發明利用非等向 性敍刻法對該導電層彳6進行蝕刻以形成如第六圖所示之 自行對準接觸窗結構。若該導電層1 6為複晶矽，以C|2、 HBr氣體予以蝕刻除去非接觸窗區域之複晶矽層；^該導 電層1 6為矽化金屬，則以c丨2、Η B r氣體予以蝕刻除去非 接觸窗區域之矽化金屬層。此步驟即為反自行對準接觸窗 银刻製程（Reverse SAC Etch Process)，由於導電層 μ {請先閲讀背面之注意事項再填寫本f ) -裝. --訂 線 本紙張尺度適用中國國家標準（g^s ) A4規格（210X297公釐） -';-. W. A7 B7 經濟部中央標準局負工消费合作社印製 五、發明説明（） 與介電層1 0、侧壁間隙壁1 4之間具有相當大之蝕刻選擇 性，即使過度融刻（〇 v e r e t c h)亦不會造成介電層 1 〇、側壁 間隙壁14或基材2之損失。其次，本發明所提出之反自 行對準接觸窗蝕刻製程亦不會因高分子（polymer)堆積而 造成蝕刻停止（etch stop)之困擾》值得注意的是，本發明 所形成之接觸窗面積變大，較傳統結構為大。 請參考第七圖所示’為本發明自行對準接觸窗形成 方法中形成内層介電層之截面圖。利用化學氣相沉積形成 一内層介電層（inter-layer dielectric; ILD)20於上述基材 2、場氧化層4、遮蓋層10以及側壁間隙（side wall spacer)14之上’該内層介電層20可為侧麟石夕玻璃，.利 如BPTE0S，該内層電質層（ILD)20為防止後續沈積膜層 與主動區1 2接觸之複晶矽層彳6間接觸而造成之短路。 本發明之優點之一為當形，成接觸窗時不會造成側壁 間隙壁1 4或遮蓋層1〇被蝕刻而暴露出複晶矽層8 ,因本 實施例之反自行對準接觸窗蝕刻製程（Reverse SAc Etch Process)無法蝕刻側壁間隙之氮化矽層14。本發明不須 為防止短路現象而增加遮蓋層10之厚度，故不會因太厚 之遮蓋層而使外觀之地形地勢（t〇p〇graphy)變陡& ;其 次，本發明亦不需製作多重側帛間隙壁以 =短路：本發明之另一優點為不會因產生過多U而造 成蝕刻钕止，且製程單純不會受硬體設備所限制。 -9- 本紙張尺細中楚') ---- (請先閱讀背面之注意事項再填寫本頁) •裝. 訂 © 0丨線 A7 B7 五、發明説明（） 本發明以一較佳實施例說明如上，而熟悉此領域技 藝者，在不脫離本發明之精神範圍内，當可作些許更動潤 飾，其專利保護範圍更當視後附之申請專利範圍及其等同 領域而定。本發明有易於實施與提昇電性特點，故本發明 具備新穎性、實用性與進步性，故符合申請專利要件，爰 依法提出申請，請貴審查委員明鑑。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消f合作社印製 -10- 本紙張尺度適用中國國家標準（cm ) A4規格（210X 297公釐）NV | Equipment | Order I xlfz / .i line A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Bayer Consumer Cooperatives 5. Description of the invention () The pad oxide layer 6, the polycrystalline silicon layer 8 and the dielectric layer 10 And covers the entire substrate. The next step is to fabricate a side wall spacer 14. This step etches the silicon nitride layer by an etching technique to form a side wall spacer 14 of the silicon nitride layer. The function of this side wall spacer 14 is similar to that of the cover layer 10, which is to prevent the formation of a short circuit between the polycrystalline stone layer 8 and the subsequent deposited film layer and the active region 12 forming the source and drain electrodes. As shown in the four figures. As shown in the fifth figure, a conductive layer 16 is formed on the substrate 2, the field oxidation region 4, the cover layer 10, and the sidewall spacer 14 described above. The thickness of the conductive layer 16 is about 4000 angstroms to 5000 angstroms. In the meantime, the conductive layer 16 is used for making a contact layer of a contact window, and may be a conductive material such as polycrystalline silicon or silicon silicide (scide). Subsequently, a second photoresist pattern 18 is defined on the conductive layer 16, and the second photoresist pattern 18 is used to define a contact window area. Please refer to Section 6 for a cross-sectional view of a self-aligning contact window forming method in the method for forming a self-aligning contact window of the present invention. In the present invention, the conductive layer 彳 6 is etched using an anisotropic engraving method to form a self-aligned contact window structure as shown in FIG. If the conductive layer 16 is polycrystalline silicon, it is etched with C | 2 and HBr gas to remove the polycrystalline silicon layer in the non-contact window area. ^ If the conductive layer 16 is silicided metal, c 丨 2, Η B r The gas is etched to remove the silicided metal layer in the non-contact window area. This step is the Reverse SAC Etch Process for self-alignment of the contact window. Due to the conductive layer μ {Please read the precautions on the back before filling in this f) -Packing. --The size of the paper is applicable to China Standard (g ^ s) A4 size (210X297 mm)-';-. W. A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () and dielectric layer 10, side wall gap There is a considerable etch selectivity between 14 and even if the over-etching does not cause the loss of the dielectric layer 10, the sidewall spacer 14 or the substrate 2. Secondly, the anti-self-alignment contact window etching process proposed by the present invention will not be plagued by etch stop caused by polymer accumulation. It is worth noting that the area of the contact window formed by the present invention changes. Larger than traditional structures. Please refer to the seventh figure 'for a cross-sectional view of forming an inner dielectric layer in the self-aligned contact window forming method of the present invention. An inter-layer dielectric (ILD) 20 is formed by chemical vapor deposition on the above-mentioned substrate 2, field oxide layer 4, cover layer 10, and side wall spacer 14 'the inter-layer dielectric The layer 20 may be side glass, such as BPTE0S. The inner electric layer (ILD) 20 is to prevent the short circuit caused by the contact between the subsequent deposited film layer and the polycrystalline silicon layer 接触 6 in contact with the active area 12. One of the advantages of the present invention is that when the contact window is formed, it does not cause the side wall spacer 14 or the cover layer 10 to be etched to expose the polycrystalline silicon layer 8. Because of the self-aligned contact window etching in this embodiment, The Reverse SAc Etch Process cannot etch the silicon nitride layer 14 in the sidewall gap. The present invention does not need to increase the thickness of the cover layer 10 in order to prevent the short circuit phenomenon, so the topography and topography (t〇p〇graphy) of the appearance does not become steep due to the too thick cover layer; Secondly, the present invention also does not require Making multiple side wall spacers to = short circuit: Another advantage of the present invention is that it will not cause etching of neodymium due to excessive U generation, and the manufacturing process will not be limited by hardware equipment. -9- The paper ruler is very thin.) ---- (Please read the precautions on the back before filling this page) • Binding. Order © 0 丨 线 A7 B7 V. Description of the invention () The embodiments are explained above, and those skilled in the art can make some modifications to the present invention without departing from the spirit of the present invention. The scope of patent protection depends on the scope of the attached patent application and its equivalent fields. The invention has the characteristics of being easy to implement and improve electrical properties. Therefore, the invention has novelty, practicability and progress, and therefore meets the requirements for patent application. 提出 Submit an application in accordance with the law. (Please read the precautions on the back before filling this page) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, printed by the cooperative -10- This paper size applies to the Chinese national standard (cm) A4 size (210X 297 mm)