TW404017B - The plasma surface treatment method having the oxide of the patterned tetra-ethyl-ortho-silicate (TEOS) with reliable etch via and the interconnection - Google Patents

Abstract

A method of forming the etch via on the dielectric in the micro-electronic process. First , provide a substrate in the fabrication of the micro-electronic; next, form a layer of silicon oxide dielectric on the substrate; silicon oxide dielectrics uses tetra-ethyl-ortho-silicate (TEOS) as the silicon source material and is formed by utilizing plasma enhanced chemical vapor deposition (PECVD) method. Next, proceed plasma treatment towards silicon oxide dielectric and a layer of plasma treated silicon oxide dielectric is formed. A layer of patterned photoresist layer is formed on plasma treated silicon oxide dielectric which is used to define the position of the etch via. The patterned photoresist layer formed by this method peeled-off easily from the plasma treated silicon oxide dielectric after utilizing subsequently the isotropical etch method to proceed etching towards plasma treated silicon oxide dielectric.

Description

V. 4040: 7 at B7 printed by the Consumer Cooperative of the Central Bureau of Probability of the Ministry of Economics (1 Background of the Invention 1. Field of the Invention The present invention relates to a method for forming an etching groove on a dielectric layer in a microelectronic process In particular, the present invention relates to a method for forming an etched groove on a dielectric layer in a microelectronic process, and the cross-sectional profile can be repeatedly manufactured. 2. Related prior technologies: Generally used in microelectronic manufacturing technology to form For the fabrication of the dielectric layer of the microelectronics structure, a silicon oxide dielectric layer is used, which uses tetraethyl orthosilicate (TEOS) as the source material and is formed by chemical vapor deposition (CVD), such as thermochemistry Vapor phase deposition method and plasma enhanced chemical vapor deposition method (PECVD). The dielectric layer includes (but is not limited to) a front metal dielectric layer (PMD), a metal dielectric layer (IMD), and a back metal dielectric. Layer. A silicon oxide dielectric layer made of tetraethyl orthosilicate (TEOS) as a microelectronic structure using thermochemical vapor deposition and plasma enhanced chemical vapor deposition (PECVD). , More intended in microelectronics manufacturing Because the silicon oxide dielectric layer has more superior characteristics than those made using other methods and materials. In particular, the silicon oxide dielectric layer in advanced microelectronics processes is at least partially based on Tetraethyl orthosilicate (TEOS) is used as the source material. It is made by plasma enhanced chemical vapor deposition (PECVD). The dielectric layer made from it can form a relatively high density and narrow etching groove. Line width line layout structures, such as (but not limited to) etched conductor layer line layout structures, are used in advanced microelectronics manufacturing techniques, as shown in the first figure, and are often applied at least on this paper scale to the national standard ( CNS > A4 specification (210X297 mm) —.— — I —.—, 1 ί 1 pack-(Please read the note on the back before filling this page) Order — line 83. 3.10,000 Central Ministry of Economic Affairs Printed by Staff of the Bureau of Standards, printed by 4080 7 A7 _ ^ _ B7_ Five 'Description of the Invention (2) A wine glass-shaped etching groove is formed on the silicon oxide dielectric layer. As shown in the first figure, a base layer 10 has at least a series of patterned sand oxide dielectric layers 12a, 12b and 12c on its surface, It is formed by using tetraethyl orthosilicate (TEOS) as a growth source material and plasma enhanced chemical vapor deposition (PECVD). The series of patterned oxide sand dielectric layers 12a, 12b and 12c A pair of wineglass-shaped etch grooves 16a and 16b are formed on a series of patterned oxide sand dielectric layers 12a, 12b, and 12c to form a series of photoresist layers 14a, 14b, and 14c to help define the pair of wineglass-type etchings. The positions of the grooves 16a and 16b. Those skilled in the art understand that the shape of the wine glass of each wine glass type etching groove 16a and 16b should preferably be contracted, so as to better perform the subsequent etching of the wine glass type with a blanket conductive layer The grooves 16a and 16b are used to complete the microelectronic process of the cross-sectional view of the structure shown in the first figure. In order to form a wine glass-shaped profile in each of the wine glass type etching grooves 16a and 16b, a typical method is to cover the microelectronic manufacturing structure shown in the first figure by covering the photoresist layers 14a, 14b, and 14c formed in the etching pattern. The oxide-based dielectric layer is subjected to: (1) forming a patterned silicon oxide dielectric on the overlying oxide-based dielectric layer in a manner of continuous local anisotropic etching / local isotropic etching / complete anisotropic etching. Electrical layers 12a, 12b, and 12c; or (2) forming patterned silicon oxide dielectric layers 12a, 12b, and 12c. The anisotropic etching method used in this continuous etching is typically (but not excluded) a reactive ion etching (RIE) anisotropic etching (please read the precautions on the back first and then 4 (Write this page) .11 I

The paper size of the 1T line is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 83, 3.10,000 404017 at B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The isotropic etching method used for this continuous etching is typically (but not excluded) a wet chemical etching method. In the microelectronic process, it is expected to be able to use a series of patterned oxide-cut dielectric layers in the microelectronic structure, such as a series of patterned oxide-cut dielectric layers 12a, 12b, and 12c shown in the first figure. A pair of wine glass type etching grooves is defined as one pair of wine glass type etching grooves 16a and 16b shown in the first figure. However, in microelectronic manufacturing technology, this microelectronic manufacturing process cannot completely overcome manufacturing problems. In particular, in general microelectronic manufacturing technology, the entire series of etched photoresist layers, such as the series of etched photoresist layers 14a, 14b, and 14c shown in the first figure, will be at least partially oxidized from the pattern. The silicon dielectric layer is a series of patterned sand oxide dielectric layers 12a, i2b, and 1; 2c as shown in the first figure. The surface is peeled off to form a cross-sectional view similar to the microelectronic manufacturing structure shown in the second figure. Structure >> The second figure shows a cross-sectional view of a microelectronic structure, which is roughly the same as the cross-sectional view of the microelectronic structure in the first figure, but in which: 0) corresponds to the entire array of engraved light in the first figure Resist layers 14a, 14b, and 14c. The entire pattern of photoresist layers 14a, Mb, and 14c are partially peeled off to form a whole array of partially stripped etching resists 14a ', 141), and 14c ,; (2) The rows of patterned sand oxide dielectric layers 12a, 12b, and 12c, and their counterparts are over-etched to form a whole row of overetched patterned sand oxide dielectric layers 12a ', l2b', and Ik '; and (3) the pair Wine glass-shaped etching grooves i6a and their counterparts are over-etched to form a pair of over-shaft type Cup-shaped contact groove 16a, and 16b '. In the advanced microelectronic manufacturing, the microelectronic structure shown in the second figure

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--II line paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 83. 3.10,000 404017 A7 B7 V. Description of the invention () (Please read the note $ on the back of mackerel before filling this page > A microelectronic structure with a matching profile is less acceptable because it is difficult to successfully form a complete or reliable conductor connection or interconnection in an over-etched wineglass-shaped etching groove, as shown in the second figure. Over-etched wine glass-shaped etching grooves 16a 'and 16b'. In the microelectronic manufacturing technology, the industry hopes to provide new methods and materials to form wine glass-shaped contact grooves on the silicon oxide dielectric layer. Ethyl orthosilicate (TEOS) is a growth source material and is grown by chemical vapor deposition (CVD), like plasma enhanced chemical vapor with tetraethyl orthosilicate (TEOS) as a growth source material Phase deposition method (PECVD), without the partial peeling of the silicon dielectric layer, and over-etching causes the etching pattern defining the wine glass type etching groove in the wine glass shaped etching groove to oxidize the resistance layer, which is the focus of the present invention. For the formation of wine glass etch in microelectronics manufacturing Different methods have been disclosed for trough and wine glass structures, especially in integrated circuit manufacturing technology. For example, Liu et al., Disclosed in US Patent No. 5,180,689 for use in integrated circuit manufacturing technology A method for forming a wine glass-shaped etching groove on a multilayer dielectric layer in a integrated circuit manufacturing structure. The method uses a continuous anisotropic localized photoresist layer along a single etching pattern photoresist layer formed on the multilayer dielectric layer. In the manner of isotropic etching / local isotropic etching / completely anisotropic etching, a wine glass-shaped etching groove is formed on the multilayer dielectric layer. The thus formed wine glass-shaped etching groove can prevent the patterned multilayer dielectric layer from generating high temperature. There is also a similar method disclosed by Megn et al. In U.S. Patent No. 5,452,403, which is used in integrated circuit manufacturing technology to form a wine glass shaped groove in the integrated circuit manufacturing structure on the dielectric layer. This method uses the Chinese standard (CNS) A4 size (21〇 × 297 mm) of this paper standard. 83. 3.! 〇, 〇〇 The Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed A7 404 0 ^ 7 _ B7 V. Explanation of the invention () A single etching pattern photoresist layer is used to form an etching mask layer of a bowl-shaped etching groove, and a continuous process of local anisotropic etching / local isotropic etching is used. To form a bowl-shaped partial etching groove on the dielectric layer. Then remove the photoresist layer of the etched pattern, and use argon sputtering plasma anisotropic etching to completely etch the bowl-shaped etching groove to the dielectric. Layer, forming a wine glass-shaped etching groove, and at the same time flattening and smoothing the sharp edge changes of the dielectric layer. Furthermore, as disclosed by Hsu in US Patent No. 5,552,343, a method is used in integrated circuit manufacturing technology, A wine glass-shaped etching groove is formed in the integrated circuit manufacturing structure, which is doped with boron and phosphorus, and uses tetraethyl orthosilicate (TEOS) as a silicon source material to generate a silicon oxide dielectric layer. This method uses a buffered oxide etchant (BOE) to remove a boron and phosphorus-doped silicon oxide dielectric layer before forming an etched photoresist layer defining the location of a wine glass-shaped etch groove. By this method, the wine glass-shaped etching groove can be formed with a small entry angle on the surface of the boron and phosphorus doped oxide compared with the surface of the dielectric layer. Finally, as disclosed by Kim in US Patent No. 5,622,833, a method for manufacturing integrated circuits is used to form a wine glass-shaped etching groove on a dielectric layer and to form a wine glass-shaped communication groove on the wine glass-shaped etching groove. A pad-shaped conductive contact embellishment layer. This method uses a continuous local isotropic etching / complete anisotropic etching method to form a wine glass-shaped etching groove on the dielectric layer. In microelectronic manufacturing technology, the industry needs more methods and materials for forming wine glass-shaped etching grooves on the dielectric layer. It uses tetraethyl orthosilicate (TEOS) as a growth source material and uses chemical vapor deposition. (CVD) cost paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 83. 3.10,000 ----------; 1 pack --.--- ^-order- --- 'line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs_404017_Βτ__ V. Description of the invention (6) Long way, such as tetraethyl orthosilicic acid Salt (TEOS) is a plasma-enhanced chemical vapor deposition method (PECVD) as a growth source material, and it can not make the wine glass-shaped etching groove in the microelectronics manufacturing because of the etching pattern defining the wine glass-shaped etching groove. The silicon dielectric layer is partially peeled off and over-etched. In integrated circuit manufacturing technology, a method and material for forming a wine glass-shaped etching groove on a silicon oxide dielectric layer, which uses tetraethyl orthosilicate (TEOS) as a growth source material and uses chemical vapor deposition (CVD) ) Growth methods, such as plasma enhanced chemical vapor deposition (PECVD) with tetraethyl orthosilicate (TEOS) as the source material, which can not define the wine glass-shaped etching groove in microelectronics manufacturing The etching pattern of the wine glass type etching groove is partially peeled from the silicon oxide dielectric layer and over-etching occurs. The foregoing needs are directly addressed by the object of the present invention. Summary of the invention: 'The main purpose of the present invention is to provide a method for forming a wine glass-shaped etching groove from a silicon oxide dielectric layer in microelectronics manufacturing, which uses a plasma enhanced chemical vapor phase in a chemical vapor deposition method. Deposition method, and tetraethyl orthosilicate is used as its source material. A second object of the present invention is to provide a wine glass type etching tank according to the method described in the first object, and the wine glass type etching tank will not be formed by a silicon oxide dielectric layer due to a photoresist layer having an etching pattern. The third object of the present invention is mainly a microelectronic process for integrated circuit manufacturing technology according to the aforementioned first object and second object. The fourth object of the present invention is to provide a method, which is mainly based on the previous (please read the precautions on the back before filling this page). Binding bv ^ This paper is again applicable to the Chinese National Standard (CNS) A4 specification (210X297 (Mm) 83. 3.10,000 A7 _ _; ------- ___ B7 Fifth, the 1st purpose, the 2nd purpose and the 3rd purpose stated in (1), and the method can be used for manufacturing. In accordance with the purpose of the present invention, the present invention provides a method for forming an etching groove on a silicon oxide dielectric layer in microelectronics manufacturing, and using tetraethyl orthosilicate (TEOS) as a growth source material, using chemistry Vapor phase deposition (CVD). To implement the method of the present invention, a substrate for microelectronics manufacturing is first provided, and then a silicon oxide dielectric layer is formed on the substrate. The silicon oxide dielectric layer is made of tetraethyl orthosilicate (TE 0s) is a growth source material and is formed by a chemical vapor deposition (CVD) method. The silicon oxide dielectric layer is then subjected to a plasma treatment to form a plasma-treated silicon oxide dielectric layer. Then, an etching pattern photoresist layer is formed on the plasma-treated silicon oxide dielectric layer by defining an etching groove on the silicon oxide dielectric layer. Compared with the same ^ etched photoresist layer formed on the same silicon oxide dielectric layer without plasma treatment, the etched photoresist layer is subjected to subsequent plasma etching using an isotropic etching method. When the silicon oxide dielectric layer is processed and etched, it is difficult to peel off the silicon oxide dielectric layer treated by the plasma. Finally, the plasma-treated silicon oxide dielectric layer is etched out by an isotropic etching method. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics The present invention provides a method for forming a wine glass-shaped etching groove in microelectronics manufacturing, using tetraethyl orthosilicate (TEOS) as a growth source material, using chemical vapor deposition (CVD) grows on the silicon oxide dielectric layer, and the formation of the wine glass type etching groove does not occur. Therefore, in the wine glass type etching groove, the etching pattern defining the wine glass type etching groove is a photoresist layer on top of the silicon oxide dielectric layer. Dividing new j away, resulting in over-etching. In the present invention, you can understand the key to achieving the purpose of the present day and month, which is to form a full engraving to define a wine glass type etching groove. 1 light 83.3.10,000 (Please read the precautions on the back before filling this page) This paper The standard is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) A7 B7 404017 V. Description of the invention (8) Before the step of resisting the layer, the silicon oxide dielectric layer is treated with plasma to form a plasma-treated silicon oxide. Dielectric layer. Although the silicon oxide dielectric layer is treated with a plasma, the mechanism that helps to improve the adhesion of the etched photoresist layer to the silicon oxide dielectric layer is not completely clear, but it is believed that it can be used to avoid defining the wine glass type. The photoresist layer of the etching groove is partially peeled from the silicon oxide dielectric layer and over-etching occurs. The method of the present invention can be used for the fabrication of integrated circuits in a microelectronic process. The present invention is not distinguished from silicon oxide dielectrics which are only used in general microelectronics manufacturing, using ethyl orthosilicate (ETOS) as a growth source material, and plasma enhanced chemical vapor deposition (PECVD) growth. A method for forming a wine glass type etching groove on a layer. The field of microelectronics manufacturing that can be used in the present invention includes (but is not limited to) integrated circuit manufacturing, solar cell microelectronics manufacturing, ceramic-based microelectronics manufacturing, and flat display microelectronics manufacturing. Similarly, the method for forming a silicon oxide dielectric layer of a wine glass-type etching tank in the present invention can be used to form a microelectronic manufacturing element including (but not limited to) a front metal dielectric layer (PMD) and an inner metal dielectric. Layer (IMd) and back metal dielectric layer. The method of the invention is ready for manufacturing. The method of the present invention utilizes ethyl orthosilicate (ETOS) as a growth source material, and performs a plasma treatment on a silicon oxide dielectric layer grown by chemical vapor deposition (CVD) to enhance the photoresistance of the cut-off pattern. The adhesion on the silicon oxide dielectric layer and a wine glass type etching groove without over-etching are formed on the silicon oxide dielectric layer. As the plasma method is a well-known technology in microelectronics manufacturing technology, the method of the present invention is straightforward — ^ 1 1! I I I (Please read the precautions on the back before filling this page)

, 1T Line Printed by the Central Consumers 'Union of the Ministry of Economic Affairs (CNS), printed by the Consumer Cooperative Cooperative (CNS), 4 gauges (210x297 mm) 83.3.10,000 404017 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau, Ministry of Economy In manufacturing. Detailed description of the drawings The objects, features and advantages of the present invention will be disclosed in detail in the preferred embodiments described later. And the preferred embodiment will be more fully understood from the attached diagram, which is the main part of this disclosure. The first picture shows the microelectronics manufacturing. A cross-sectional view of a pair of wine glass-type etch grooves on the dielectric layer. The second figure shows a cross-sectional view of a pair of wine glass type etching grooves over-etched on a silicon oxide dielectric layer in a conventional microelectronic manufacturing method. Caused by partial peeling from the silicon oxide dielectric layer. The third to sixth figures show a series of cross-sectional views of one of the preferred embodiments of the present invention, used to explain the results of various manufacturing steps performed on the silicon oxide dielectric layer, which are mainly disclosed in the first aspect of the present invention. A wineglass-shaped etching groove without over-etching is formed in a preferred embodiment. A series of cross-sectional views shown in FIGS. 7 to 11 are used to explain the results of various manufacturing steps performed on the inner metal dielectric layer (IMD) in the manufacture of integrated circuits. A wine glass type etching groove without over-etching, as shown in the two preferred embodiments. Detailed description of the invention A preferred embodiment of the present invention is a method for manufacturing microelectronics, which uses chemical vapor deposition (CVD) and uses tetraethyl orthosaltate (TEOS) as the source material of silicon. A wine glass type etching groove is formed on the silicon oxide dielectric layer, and the wine glass type etching groove will not be used to define the wine glass type contact (please read the precautions on the back before filling this page). Applicable to China National Ladder Standard (CNS) A4 specification (2 丨 〇 < 297 public directors) 83. 3.10,000 A7 B7 5. Description of the invention () Etching pattern of grooves Photoresist layer on silicon oxide dielectric layer Partial peeling leads to excessive etching. In the present invention, the silicon oxide dielectric layer is first treated with a plasma, and then an etching pattern photoresist layer defining a wine glass type etching groove is formed thereon, thereby achieving the purpose of the invention. "Although the present invention is in a integrated circuit, In the manufacturing process, there is a substantial utilization price, which uses plasma enhanced chemical vapor deposition and uses tetraethyl orthosilicate (TEOS) as the source material to expose the metal dielectric layer (IMD) in silicon oxide. The wine glass type etching groove formed on the surface, and the method of the present invention can prevent the wine glass type etching groove from being over-etched. However, it is not only used for integrated circuit manufacturing, but also includes (but is not limited to) the micro cells of solar cells. In electronics manufacturing, ceramic-based microelectronics manufacturing and flat display microelectronics manufacturing, the silicon oxide dielectric layer can be formed including (but not limited to) a front metal dielectric layer (PMD), an inner metal dielectric The position of the IMD and the rear metal dielectric layer u For the first preferred embodiment, please refer to the third to sixth figures, which disclose a series of cross-sectional views for explaining the general specific embodiment of the present invention. system The microelectronic fabrication carry out the steps of the result, comprising a first specific preferred embodiment of the present invention, without excessive etching of one type of glass etching bath which silicon oxide dielectric layer is formed. The first figure shows a cross-section manufacturing diagram of early manufacturing steps in microelectronics manufacturing. The third figure shows a substrate 20 on which a silicon oxide dielectric cover layer 22 has been formed. In this first preferred embodiment of the present invention, I. 11—--II--Hr.---II-I I ..... II .-— I— I— .. USJ (Please read the notes on the reverse side before filling out this page).-Printed by the Beige Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ This paper is in Chinese National Standard (CNS) A4 size (210X297 mm) 83.3.10,000 A7 4 〇4〇 ± ^ _ £-V li, V. Description of the invention () The substrate 20 is used for microelectronic manufacturing including (but not limited to) integrated circuits, solar cells, ceramic-based microelectronic manufacturing, and In the microelectronic manufacturing of a flat display, the substrate 20 may be a simple substrate used for microelectronic manufacturing, or a substrate on which some microelectronic thin film layers have been formed. The microelectronic thin film layer may include (but is not limited to) a microelectronic conductor layer, a microelectronic semiconductor layer, and a microelectronic dielectric layer. For the silicon oxide dielectric layer 22, at least its exposed portion is a chemical vapor deposition method (CVD) and uses tetraethyl orthosilicate (TEOS) as the source material of silicon. This chemical vapor deposition method ( CVD) may be a thermal chemical vapor deposition method or a plasma enhanced chemical vapor deposition method (peCVD). ~ The silicon oxide dielectric layer 22 may be an undoped silicon oxide dielectric layer or a doped silicon oxide dielectric layer, and the doping material may include (but not limited to) boron and (I phosphorus, doping concentration) From a small amount to about 12 atomic percent 'as is well known in microelectronic manufacturing technology. The preferred chemical vapor deposition method (CVD) uses the following conditions: (1) a reaction chamber for which chemical vapor deposition (CVD) is applicable Pressure (that is, the Ministry of Economic Affairs, the Central Bureau of Standards, Work and Consumption Cooperation, Du printed on about 6 Torr to about 10 Torr for plasma enhanced chemical vapor deposition (PECVD), used for About 30 Torr to 50 Torr of Low Pressure Chemical Vapor Deposition (LPCVD), about 350 Torr of Sub-Atmospheric Chemical Vapor Deposition (SACVD) (

Torr) to 450 Torr, about 760 Torr for atmospheric pressure chemical vapor deposition (APCVD); (2) RF power (only required for plasma reaction), this uses 13.56 hundred Radio frequency in megahertz (MHz) with power of 600 watts to 900 watts; (3) appropriate substrate 20 temperature 'in heat 83. 3.10,000 1 ^^ 1. ^^^ 1 n ^ i I ^ J ^ i --II na I (Please read the precautions on the back before filling this page) The size of the paper is applicable to China National Standard (CNS) A4 specification (210 × 297 mm) A7 404017 _____ B7___ V. Description of the invention (12) About 350 to 550 degrees Celsius in phase deposition and about 350 to 450 degrees Celsius in plasma enhanced chemical vapor deposition (PECVD); (4) 180 to 280 mils (thousandths of an inch) (5) TEOS concentration and flow control for chemical vapor deposition (CVD) (ie, used in plasma enhanced chemical vapor deposition (PECVD)) Flow rate of 700 to about 1200 mg for low pressure chemical vapor deposition (LPCVD) flow rate of about 350 to about 600 mg per minute and for sub-atmospheric pressure chemical vapor deposition Method (SACVD) or for atmospheric pressure chemical vapor deposition (APCVD) flow rate of about 200 to about 400 mg per minute); (6) oxidant oxygen or ozone flow control, such as chemical vapor deposition method (CVD ) Dedicated flow (seem) of about 400 to 8000 cubic centimeters per minute (under standard conditions). And (7) the control of the flow rate of helium in the background gas (carrier gas) in the chemical vapor deposition method (ie, used in the plasma enhanced chemical vapor deposition method (PECVD), about 1000 cubic centimeters per minute) (Under standard conditions) (seem) flow rate, used in low pressure chemical vapor deposition (LPCVD) flow rate of about 1000 to about 1,400 cubic centimeters per minute (under standard conditions) (seem) and for sub-atmospheric pressure chemistry Flow rate of about 3,500 to about 4,500 cubic centimeters per minute (under standard conditions) in vapor deposition (SACVD). Preferably, the silicon oxide dielectric cover layer 22 is formed to a thickness of about 4,000 to 5,000 Angstroms (Angstroms). Please refer to the fourth figure. This cross-sectional view shows the manufacturing results of the substrate of the third figure in the subsequent microelectronic process. 'Compared to the third figure'. The silicon oxide dielectric cover layer 22 has been processed by the plasma 24 and becomes Plasma-treated silicon oxide 14 Γ ^ SpacilicalM ^ IIII Joc This paper is sized for China National Standard (CNS) A4 (210 X297 mm) (please read the precautions on the back before filling out this page) Printed by the Bureau of Standards, Consumer Cooperatives of the Ministry of Economic Affairs. Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 4040: 17 $ 5. Description of Invention (13) Dielectric layer 22 '. According to a first preferred embodiment of the present invention, it is preferable that the plasma 24 contains oxygen or nitrogen. More preferably, plasma 24 is composed of oxygen and nitrogen. "Best, plasma 24 is composed of oxygen." Although the silicon oxide dielectric coating 22 is treated by the first plasma 24, it is converted to plasma-treated silicon oxide. The mechanism of the dielectric layer 22 is not very clear, and it is believed that when the wine glass type etching groove is formed in the subsequent process, the photoresist layer is not formed on the silicon oxide dielectric layer due to the etching pattern defining the wine glass type etching groove. Partial peeling leads to excessive etching. Because the first plasma 24 can remove impurities from the surface covering the silicon oxide dielectric layer 22, or change its surface to form a oxidized sand dielectric layer 22 'at the plasma, the photoresist layer can be more easily patterned with its surface. Join. Although not specifically illustrated in the third and fourth figures, the first plasma 24 treatment of the silicon oxide < dielectric coating 22 is preferably the same as the process of forming the silicon oxide dielectric layer 20 on the substrate It is carried out in a reactor, or in an adjacent reactor (meaning not exposed to the atmosphere). This will provide better manufacturing efficiency and make the formation of the silicon oxide dielectric layer 20 on the substrate and the plasma-treated silicon oxide dielectric layer 22 'on the substrate 20 more reliable. Preferably, the first plasma 24 treatment uses the following conditions: (1) a reactor pressure of about 7 to about 11 Torr; (2) a use frequency of 13.56 million hertz (MHz) and a power of about 600 Watts to about 800 watts of RF power; (3) substrate temperature from about 350 degrees to 450 degrees Celsius; (4) crystal block spacing from about 180 to 280 mils (thousandths of an inch); (5) per About 400 to 600 cubic centimeters per minute (under standard conditions) (seem) of oxygen This paper size is common Chinese National Standard (CNS) A4 specification (210X297 mm) Packing-(Please read the precautions on the back before filling this page)- 5 Line 404017 A7 B7 V. Description of the invention (14 Air flow control or nitrogen flow control of about 2000 to 3,000 cubic centimeters per minute (under standard conditions) (seem); and (6) About 3 to 10 seconds Plasma 24 processing time. Please refer to Figure 5. This cross-sectional view shows the results of subsequent microelectronics manufacturing after the processing procedure in Figure 4. Compared to the fourth figure, the plasma treatment of the silicon oxide dielectric cover An entire array of etched photoresist layers 26a, 26b, and 26c have been formed on layer 22 'to form the etched photoresist layer. The method and the materials used are known in microelectronics manufacturing technology. The traditional method of microelectronics manufacturing is used to etch on the overlying photoresist layer to form an etching pattern photoresist layer. The material used for the overlay photoresist layer is selected. General photoresist materials include (but are not limited to) positive photoresist materials and negative photoresist materials. In the first preferred embodiment of the present invention, the entire array of etched photoresist layers 26a, 26b, and 26c are preferably made of positive light. Resistive material is formed, because in the microelectronic manufacturing, the etched photoresist layer formed by the positive photoresist material usually has enhanced planar stability, but other materials can form the entire etched pattern photoresist layer 26a, 26b and 26c. Preferably, the etched photoresist layers 26a, 26b, and 26c formed on the plasma-treated silicon oxide dielectric layer 22 'have a preferred thickness controlled between about 8000 and 10,000 Angstroms to define A pair of holes having a width W1 between about 0.45 and 0.65 microns, and separated by a photoresist layer having a width W2 between about 0.3 and 0.2 microns, as shown in the fifth figure. Plasma-treated silicon oxide dielectric coating 22 'After the local isotropic etching, a plasma treated silicon oxide dielectric coating 22' of local isotropic etching is formed. When the plasma treated silicon oxide dielectric coating is used, the paper size applies Chinese national standards (CMS) A4 specification (210X297mm) Surface ------------- ^ -------- IT ------. ^ (Please read the note # on the back first, fill in (This page) Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4040 ^ γ Α7 Printed by the Central Standards Bureau of the Ministry of Economics, printed by the Shellfish Consumer Cooperatives B7 V. Description of the invention (15) 22' after partial isotropic etching step The process of forming the electrically-treated silicon oxide dielectric coating 22, which is locally isotropically etched, uses an isotropic etchant used in traditional microelectronics manufacturing. This isotropic etchant includes (but is not limited to) a hydrofluoric acid based etchant used in wet chemical isotropic etching and is performed at a pressure of 350 microtorr (mTon :) above the original reactor pressure. Fluorinated etchant for dry plasma isotropic etching. In the first preferred embodiment of the present invention, the isotropic etchant uses a buffered oxide etchant (BOE) used in traditional microelectronics manufacturing, which is composed of aqueous gasification ammonium aqueous hydrofluoric acid. As shown in the fifth figure, a pair of bowl-shaped holes are formed in the locally-isotropically etched plasma-treated silicon oxide dielectric layer 22 '. In general, the ratio of the horizontal (vertical cross-section) to the vertical etch rate of the holes in the silicon oxide dielectric layer 22 'treated with the plasma isotropically etched plasma is approximately not more than 1.8, and more The ratio is preferably 1: 1 to 1.4: 1. Please refer to Figure 6. This cross-sectional view shows the manufacturing results of the subsequent microelectronics after the processing procedure of Figure 5. Compared to the fifth figure, a pair of bowl-shaped holes are formed in the plasma-treated silicon oxide dielectric layer 22 'with local isotropic etching, which have been completely etched to the substrate to form a pair of wine glass-shaped etching grooves. 29a and 29b, which also enables the plasma-treated silicon oxide dielectric layers 22a, 22b, and 22c with an etching pattern to be formed simultaneously. The pair of wine glass-shaped etching grooves 29a and 29b are formed by plasma treatment of a silicon oxide dielectric layer 22 'on a locally isotropic etching, and the photoresist layers 26a, 26b, and 26c coated with the etching mask are used as an etching mask. 'Formed by the second plasma 28 treatment. In the first preferred embodiment of the present invention, the second plasma 28 treatment uses a typical and better isotropic reactive ion etching (RIE) method, and it mainly uses a fluorine-containing etching ('ΛϋΜΐι' ΙΚ ISwiii Spccilk * ii〇 «« t IM Joe 1 * 7 This paper size is in accordance with China National Standards (CNS) M specifications (210X297) 嫠 404017 A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Explanation (16) The etchant gas is the plasma component. As shown in the cross-sectional view of the sixth figure, the pair of wine glass-shaped etching grooves 29a and 29b do not form photoresist layers 26a, 26b, and 26c due to the entire line of etching patterns Excessive etching due to peeling off of the plasma-treated silicon oxide dielectric layers 22a, 22b, and 22c with an etching pattern. Because the pair of wine glass-shaped etching grooves 29a and 29b do not form photoresist layers 26a, 26b, and 26c due to the entire etching pattern Excessive etching caused by the peeling of the plasma-treated silicon oxide dielectric layers 22a, 22b, and 22c with an etching pattern, which makes a pair of wineglass-type conductors on the pair of wineglass-type etching grooves 29a and 29b contact and level conductive Interbody wiring layer, which can have better Surface stability, thereby enhancing its function and reliability. For the second preferred embodiment, please refer to FIGS. 7 to 11, which reveal a series of cross-sectional views. A preferred embodiment for special applications. It is the result of various steps in the fabrication of integrated circuits, which includes a pair of non-metallic dielectric layers (IMDs) formed in the second preferred embodiment of the present invention. Over-etched wineglass-shaped etching groove. The seventh figure shows a cross-sectional view of an early manufacturing step in the fabrication of integrated circuits. The seventh figure shows a pair of isolation areas formed on the surface and inside of a semiconductor substrate 30, It is used to separate the active regions on the semiconductor substrate 30. Although the semiconductor substrates used in the fabrication of known integrated circuits may have N-type and P-type doping, different doping concentrations and several different crystallization directions. In this second preferred embodiment of the present invention, the semiconductor substrate 30 used is an N-type or P-type silicon semiconductor substrate crystallized in the (100) direction. UitJa l'K Γμ «·· SfMctikatioaAi ih Jo , .. J ^ Paper Zhang scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back-fill out this page first)-Installed * * τ 404017 Printed by A7 B7_ 5 (17) In the same way, in the manufacture of known integrated circuits, an isolation region that separates each active region on a semiconductor substrate can be formed on or inside the semiconductor substrate or coexist, and the formation method includes (instead of Limited to) thermal isolation method and deposition / patterning method. In the second preferred embodiment of the present invention, the isolation regions 32a and 32b preferably adopt an isolation region thermal growth method to generate isolation regions 32a and 32b of silicon oxide on the surface and inside of the semiconductor substrate 30 to separate the semiconductor substrate 30. On each action zone. The seventh figure also reveals that a series of structures are formed on the surface and inside of the active region of the semiconductor substrate 30, which are used to form a field effect transistor (FET). The series of structures includes: (1) a gate dielectric layer 34 formed in the active region of the semiconductor substrate 30; (2) a gate electrode 36 formed and arranged on the gate dielectric layer 34; and (3) In the active region of the semiconductor substrate 30, a pair of source / drain regions 38a and 38b are formed on a portion of the semiconductor substrate 30 that is not covered by the gate dielectric layer 34 and the gate electrode 36. The methods and materials used in the field-effect transistor (FET) manufacturing in the field of traditional integrated circuit manufacturing can be used in the formation of each structure of the field-effect transistor (FET) described above. The formation of the silicon oxide gate dielectric layer 34 is typically better (but not excluded) by using a thermal oxidation method to form a silicon oxide gate dielectric having a thickness of about 80 to 140 angstroms on the active region of the semiconductor substrate 30. Electrical layer 34, and the gate electrode 36 formed and arranged on the gate dielectric layer 34 is typically better (but not excluded) by using a miscellaneous complex crystal sand having a thickness of about 1500 to 2500 angstroms. Or doped polysilicon / metal siliside is used as the gate electrode material. Finally ‘form the semiconductor substrate 30 < ·: UmI · lit 1 9 ^ Paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) '

404017 A7 B7 V. Description of the invention On the source / drain regions 38a and 38b in the active region, the typical preferred one is that the ion beam density is about 1E13 to 1E16 ions per cubic centimeter, and the implantation energy is about In the ion implantation method of 35 to 50 kiloelectron volts (keV), the gate dielectric layer 34 and the gate electrode 36 are used as a mask to form the printed work of the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. It also shows the growth of a metal dielectric layer 40 (PMD) before planarization formed on a semiconductor substrate 30 including a field effect transistor structure, and the growth of the metal dielectric layer (PMD) before planarization. There are a variety of methods and materials available in known integrated circuit manufacturing. In integrated circuit manufacturing, the growth method of metal dielectric layer (PMD) before planarization includes (but is not limited to) chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and physical vapor deposition (Physical Vapor Deposition_PVD) sputtering method, and the dielectric in the metal dielectric layer (PMD) before planarization formed by these methods Materials include, but are not limited to, silicon oxide Dielectric materials, silicon nitride dielectric materials, and silicon oxynitride dielectric materials. In a second preferred embodiment of the present invention, the pre-planarized metal dielectric layer (PMD) 40 is a preferred oxynitride. Silicon material is formed by plasma enhanced chemical vapor deposition (PECVD). This process is similar to that shown in the third figure on the substrate by plasma enhanced chemical vapor deposition (PECVD). A silicon oxide dielectric layer 22 is formed at the location similarly. The thickness of the metal dielectric layer (PMD) 40 formed before the planarization is preferably between about 9000 and 12000 angstroms. Please refer to the seventh figure again, which also reveals A pair of patterned caps are formed over the pre-planarized metal dielectric layer (PMD) 40.

---------- Installation-(Please read the precautions on the back before filling in this page) Binding line 20 This paper size uses China National Standard (CNS) Α4 size (210 × 297 mm) 404017 ΑΊ Β7 V. Description of the invention (1) A conductor layer 42a and 42b ° In the field of known integrated circuit manufacturing [electronic integrated circuit manufacturing, a patterned conductive layer can be formed by a variety of methods and materials. The formation of a patterned conductor layer is a typical method in the traditional integrated circuit manufacturing field by patterning a cover conductor layer, and the cover conductor layer can be selected from various metals, alloys, and doped complex crystals. Silicon and polycrystalline silicon silicide are used as materials. In a second preferred embodiment of the present invention, the patterned first conductor layers 42a and 42b formed above the planarized metal dielectric layer (PMD) 40 are preferably used in the conventional technology to at least The method of patterning the conductive layer by covering some aluminum-containing materials is well known in general in the manufacture of integrated circuits. Typically, the first conductor layers 42a and 42b are formed to have a thickness of about 4500 to 8000 angstroms, a width of about 0.3 to 3 micrometers, and a separator of about 0.3 to 3 micrometers. Finally, in the seventh figure, a series of three overlying dielectric layers are also shown, which are formed on the pre-planarized metal dielectric layer (PMD) 40 and a pair of patterned first conductor layers 42a and 42b. The three covering dielectric layers of this series include: (1)-covering the first inner metal dielectric layer (IMD) 43, which is formed before the planarization of the metal dielectric layer (PMD) 40 and a pair of patterned first On the conductor layers 42a and 42b; (2)-covering the first interstitial charge inner metal dielectric layer (IMD) 44 formed on the first inner metal dielectric layer (IMD) 43; and (3) ) A covering first-planar inner metal dielectric layer (IMD) 45 ′ is formed on the first gap filling inner metal dielectric layer (IMD) 44. Although in the field of traditional integrated circuit manufacturing, the formation process of any of the three dielectric layers described above, the methods and materials used in this paper are suitable for financial standards (CNS) (2iQx297)

n III ^ IIII n I— ^ Line I (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Central Bureau of Standards of the Ministry of Economic Affairs Printed by the Bayer Consumer Cooperatives 404017 A7 __ B7 5 2. Description of the Invention (20) There are many ways to form the material, and the preferred choice for forming the first inner metal dielectric layer (IMD) 43 is the same as that used to form the metal dielectric layer (pMD) 40 before planarization. The method is similar or the same as that of the material, and a desired non-planar covering of the first inner metal dielectric layer (IMD) 43 is obtained. The thickness of the first inner metal dielectric layer (IMD) 43 is preferably about 4000 to 5000 angstroms. Similarly, in the field of traditional integrated circuit manufacturing, there are many ways to choose the method and materials for forming the gap-filled dielectric layer, including (but not limited to) the spin-on-glass coating method (SOG) and fixing. High-pressure ozone-assisted thermochemical vapor deposition (CVD), and the gaps formed by these methods-the dielectric material in the tritium-charged dielectric layer includes (but is not limited to) siloxane spin-on-glass (SOG) dielectric Materials, silicate spin-on-glass (s0G) dielectric materials, and silicon oxide dielectric materials, and in the second preferred embodiment of the present invention, 'the covering first gap is filled with a metal dielectric. The layer (IMD) 44 is formed by using a better siloxane rotating glass (SOG) dielectric material, and is formed by a rotating glass (S0G) coating method, as is commonly used by conventional integrated circuit manufacturing techniques. The preferred thickness of the first interstitial-filled metal dielectric layer (IMD) 44 is between about 6000 and 8000 angstroms. Finally, in the second preferred embodiment of the present invention, the covering first planarized inner metal dielectric layer (IMD) 45 is a silicon oxide dielectric material selected by using tetraethyl orthosilicate (TEOS ) As the source of silicon,

It is formed using a chemical vapor deposition method, which is at least the same as the chemical vapor deposition method used to cover the exposed portion of the silicon oxide dielectric layer 22 formed in the first embodiment of the third embodiment of the present invention. Orthosilicate (TEOS) This paper size is applicable to the Chinese national standard (CNS > Α4 size (210X297 mm) ---------— packing— (Please read the note on the back before filling in this item. Page) Order 404017 V. Description of the invention f1)) As the source of sand, the materials are the same or similar. Duplication—The formation of a planarized internal metal dielectric layer (IMD) 45 is preferably formed at about 4,000 to 5000 angstroms. Please refer now to the eighth figure. This cross-sectional view shows the manufacturing results of the integrated circuit microelectronic structure shown in the seventh figure in subsequent integrated circuit manufacturing. The cross-sectional view of the integrated circuit microelectronic structure in the eighth figure is similar to the integrated circuit microelectronic junction shown in the seventh figure in other respects, but it covers the first planarized metal dielectric layer (IMD) 45 has been processed by the first plasma 46, and it becomes the first plasma-covered plasma treatment of the first plane = inner metal medium (excitation) 45 '. In the second preferred embodiment of the present invention ^ 'the method, materials, conditions, and conditions shown in the fourth -M 46 are shown in the fourth figure, the first embodiment of the present invention, the first-electric win 24 The methods, materials, and conditions used are similar or the same. 'First, please refer to the ninth figure. This cross-sectional view shows the manufacturing results of the integrated circuit microelectronic structure in the subsequent integrated circuit manufacturing shown in FIG. Λ. The sectional view of the integrated circuit microelectronic structure in the ninth figure ， The integrated circuit microelectronic junction axial plane diagram shown in Figure 8 = face = printed by the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs, Du printed: (1) the first planarization of the metal substrate in the covering plasma treatment The electrical layer (_) 45 'has been formed in the entire row of the engraved pattern ~ photoresist layer stealing, sampling and 48c; and 覆盖 the covering plasma treatment of the first-planar metal dielectric layer 45' has been isotropic The isotropic etching is a local isotropic etching covering the first planarized metal dielectric layer (IMD) 45 by plasma treatment to form a pair of wine glass-shaped holes. In the second preferred embodiment of the present invention, the paper size of the entire row of hungry wedding dresses is applicable to the Chinese National Winter Standard (CNS) A4 specification (2iQX 297 public directors) 404017 a? B7 V. Description of the invention f2) The formation of the first photoresist layer 48a, 48b, and 48c printed by the Consumer Bureau of the Standards Bureau. The methods, materials, sizes, and dimensions are shown in the fifth figure and the first embodiment of the present invention. The methods, materials, and dimensions used in the photoresist layers 26a, 26b, and 26c are similar or the same. Similar to the first preferred embodiment of the present invention, the localized isotropic etching overlay formed by the first planarized inner metal dielectric layer (IMD) 45 'is processed by the overlay plasma treatment shown in the eighth figure. The first planarized inner metal dielectric layer (IMD) 45 "is plasma-treated. The method and materials used are the same as those formed by the plasma-treated silicon oxide dielectric layer 22 'shown in the fourth figure. The method and material used for the local isotropic etching to cover the plasma-treated silicon oxide dielectric layer 22 "is similar or the same. As shown in the ninth figure, in the second preferred embodiment of the present invention, the etch-cover plasma treatment is performed on the first planarized inner metal dielectric layer (IMD) 45 'through partial isotropic etching. The partial isotropic etching covers the plasma treatment of the first planarized inner metal dielectric layer (IMD) 45 ", and the etching does not reach the first interstitial filled inner metal dielectric layer (IMD) 44. If the The etching depth is up to covering the first interstitial charge inner metal dielectric layer (IMD) 44 ', then the local isotropic etching covers the plasma treatment to the first to planarized inner metal dielectric layer (IMD) 45 ", and its bowl The bowl-shaped contour of the hole shape will be damaged. Please refer to the tenth figure. This cross-sectional view shows the fabrication results of the integrated circuit microelectronic structure shown in the ninth figure in the subsequent integrated circuit manufacturing. The cross-sectional view of the integrated circuit microelectronic structure shown in the tenth figure is otherwise similar to the cross-sectional view of the integrated circuit microelectronic structure shown in the ninth figure. ). Binding. Binding paper size is common Chinese National Standard (CNS) A4 specification (210X297 mm) A7 404017 B7 V. Description of the invention P) Same, but the local isotropic etching covers the first plane of plasma treatment The bowl-shaped holes on the internal metal dielectric layer (IMD) 45 "have been completely etched with the second plasma 50 to form a pair of wine glass-shaped interconnect wiring etching grooves 51a and 51b, respectively, and patterned the first The conductor layers 42a and 42b communicate with each other, and at the same time: (1) Placing the local isotropic etching to cover the plasma treatment and forming the first planarized inner metal dielectric layer (IMD) 45 "into a patterned plasma treatment. The first planarized inner metal dielectric layer (IMD) 45a, 45b, and 45c; (2) A patterned pattern covering the first gap filled inner metal dielectric layer (IMD) 44 is formed to cover the first gap filled inner metal Dielectric layers (IMD) 44a, 44b, and 44c; and (3) covering the first internal gold Dielectric (IMD) 43 is formed of a first patterned aligned metal dielectric (IMD) 43a, 43b and 43 c. In the second preferred embodiment of the present invention, the preferred method, materials, and conditions used in the second plasma 50 are shown in the sixth embodiment of the second plasma. 28 The methods, materials and conditions used are similar or the same. Similar to the first preferred embodiment of the present invention, the pair of wine glass-type interconnecting etch grooves 51a and 51b shown in the tenth figure does not result in the first photoresist layer 48a, 48b and 48c are excessively engraved due to partial peeling on the first planarized inner metal dielectric layers (IMD) 45a, 45b, and 45c in combination with patterned plasma treatment. Please refer to the eleventh figure. This cross-sectional view shows the manufacturing results of the integrated circuit microelectronic structure shown in the tenth figure. _ The integrated circuit microelectronics shown in the eleventh figure Structural cross-section view, in other $ t'axal IR.itoc 25 This paper size is universal China National Standard (CNS) A4 specification (210X297 mm) '------------ install-(Please (Read the notes on the back before filling out this page)

ΤΨ, '' " Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 404017 A7 A7 B7 Printed by the Shell's Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the Invention f4) The cross-sectional view of the bulk circuit microelectronic structure is the same, but: (1) the first photoresist layers 48a, 48b, and 48c have been removed by one of the steps in the fabrication of the integrated circuit; Corresponding wineglass-shaped etching grooves form a pair of patterned second conductive layers 52a and 52b in contact with the patterned first conductive layers 42a and 42b, respectively. In a second preferred embodiment of the present invention, the first photoresist layers 48a, 48b, and 48c in the etched pattern shown in the tenth figure have been removed by one step in the fabrication of integrated circuits, thereby providing the formation of a A part of the cross-section structure of the integrated circuit manufacturing is shown in the figure ^ and the method used in the traditional technology is typically adopted (but not excluded) in other ways, including wet chemical removal and dry oxygen Atomic plasma removal. Similarly, in the second preferred embodiment of the present invention, the preferred method, material, and size of the first photoresist layers 48a, 48b, and 48c of the etched pattern and the patterned first conductive layer are formed. The methods, materials, and dimensions used in 42a and 42b are similar or the same. By utilizing the function and reliability of the wine glass-shaped etching groove, the patterned second conductive layers 52a and 52b formed there are no defects or impurities remaining therebetween, and the first photoresist layer 48a'48b and 48c is slightly over-etched by the corresponding patterned electrowinning treatment of the first planarized inner metal dielectric layers (IMD) 45a, 45b, and 45c. Example: Using TEOS as the source material, an electric award enhanced chemical vapor deposition method (PECVD) is used to form a layer of oxide sand dielectric on each of a series of four semiconductor substrates . The Electric Award Enhanced Chemistry

is ---------- Loading--(Please read the precautions on the back before filling this page) Thread 26 This paper size applies to China National Standard (CNS) A4 specification (2 丨 0 乂 297mm) Ii) Printed by Shellfish Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs 404017 a? _: _ B7___ V. Description of Invention (25) The vapor deposition method (PECVD) uses the following conditions: (1) a reactor pressure of about 9 Torr (Torr); (2) — RF power with a frequency of 13.56 MHz and a power of about 700 watts; (3) — semiconductor substrate temperature of about 400 degrees Celsius; (4) — a concentration of about 800 milligrams (mgm) per cubic meter TEOS; and (5) —Oxygen with a flow rate of about 500 cubic centimeters per minute (under standard conditions) is used as the oxidant. On the four semiconductor substrates, the silicon oxide dielectric layers formed on three of them are treated with an oxygen atom plasma or a nitrogen atom plasma, respectively, under the following conditions: (1) a reactor pressure of about 9 Torr ( torr); and (2) —RF power with a frequency of 13.56 MHz and a power of about 700 watts. In this way, the silicon oxide dielectric layer will be formed into a plasma-treated silicon oxide dielectric layer. The oxygen atom plasma treatment or nitrogen atom plasma treatment may use different exposure times and different oxygen or nitrogen flow rates. An etched photoresist layer is formed on each of the plasma-treated silicon oxide dielectric layer and another silicon oxide dielectric layer that has not been treated. The photoresist layer is made of PF158 positive photoresist material provided by Sumitono Chemical Company. . Each etched photoresist layer is formed to a thickness of about 8700 angstroms, and has a plurality of circular holes with a diameter of about 0.55 micrometers. Each circular hole is separated from its neighbor by about 0.4 micrometers: On the photoresist layer of each of the plasma-treated silicon oxide dielectric layers and another silicon oxide dielectric layer that has not been treated, 20: 1 ratio of buffered oxidizing etchant (BOE), to etch its circular holes. (Note: 20: 1 refers to the ratio of 20% aqueous ammonium fluoride to 49% aqueous hydrofluoric acid. At 20: 1), the etching time is about 225 seconds at about 23 degrees Celsius. The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) 404017 A7 B7 V. Description of the invention (27) Via electricity The efficacy shown by the pulp treatment can be shown in the scanning electron microscope (SEM) test result report shown in Table 1. Table 1 Sample electric purple treatment horizontal to vertical touch Hai! 1 speed ratio printed by the Consumer Cooperatives of the Central Economic and Technical Standards Bureau, Ministry of Economic Affairs 1 02—flow 500 seem / processing time 5 seconds 2 02—flow 500 seem / processing time 25 seconds 3 N2 —Flow rate 1000 seem / Processing time 5 seconds 4 Without the information shown in Table 1, it is applied in the preferred embodiment of the present invention. The silicon oxide dielectric layer is treated with an oxygen atom or nitrogen atom plasma, which can provide A plasma-treated silicon oxide dielectric layer is formed, and the wine glass-shaped etching groove formed through the plasma treatment layer is less likely to be over-etched. It can be known that the patterned conductive layer formed on the wine glass-shaped etching groove need not be shortened in depth ratio. Although the preferred embodiment of the present invention and the embodiment of the present invention have been disclosed in the foregoing description, it can be understood by those skilled in the art. However, it is not intended to limit the invention. Without departing from the spirit and scope of the present invention, various changes and modifications can be made to the preferred embodiments of the present invention and the methods, materials, structures, and sizes provided in the embodiments of the present invention. The scope of protection shall be determined by the scope of the attached patent application. 1.35 1.00 1.65 3.35

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Installed.

1T line 29 This paper size is applicable to China National Sample (CNS) A4 specification (210 × 297)

Claims (1)

404017 ABCD Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. Scope of Patent Application 1. A method for enhancing the adhesion of a photoresist layer to a dielectric layer in microelectronic manufacturing, which includes the following steps: Provide a microelectronic Manufacturing substrate; a silicon oxide dielectric layer is formed on the substrate, the silicon oxide dielectric layer uses tetraethyl orthosilicate (TEOS) as the source material of silicon, and chemical vapor deposition (CVD) is used Making; treating the silicon oxide dielectric layer with a plasma, so that the silicon oxide dielectric layer becomes a plasma-treated silicon oxide dielectric layer; and forming on the plasma-treated silicon oxide dielectric layer, forming An etched photoresist layer, so the step of using the silicon oxide dielectric layer as a plasma treatment can enhance the adhesion of the etched photoresist layer to the plasma treated silicon oxide dielectric layer. 2. The method according to item 1 of the scope of the patent application, wherein the microelectronics manufacturing method is selected from the group consisting of integrated circuit microelectronics manufacturing, solar cell microelectronics manufacturing, ceramic-based microelectronics manufacturing, and flat display microelectronics. Microelectronics manufacturing group consisting of electronics manufacturing. 3. The method according to item 1 of the scope of patent application: wherein the chemical vapor deposition (CVD) method is selected from the group consisting of thermochemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD). A CVD group is formed, and the silicon oxide dielectric layer is selected from the group consisting of a doped silicon oxide dielectric layer and an undoped silicon oxide dielectric layer. 4. The method according to item 1 of the scope of patent application, wherein the plasma used for plasma treatment is selected from the group consisting of an oxygen atom plasma and a nitrogen atom plasma ------------ --------, · 1 pack ----- (Please read the precautions on the back before filling this page), 11: National paper size of this paper applies Chinese National Standard (CNS) A4 specification (210X297) (B) ABCD 404017 6. Patent application plasma group. 5. The method according to item 1 of the scope of patent application, wherein the adhesion between the photoresist layer of the etched pattern and the plasma-treated silicon oxide dielectric layer can be isotropic in the exposure of the electro-treated silicon oxide dielectric layer upon exposure. It is enhanced during isotropic etching. The isotropic etching is selected from the group of isotropic etching composed of wet chemical etching and high pressure reactive ion etching (RIE). 6. A silicon oxide dielectric layer is formed in the manufacture of microelectronics, which is made according to the method of the first patent application. 7. A method for forming an etching groove on a dielectric layer in microelectronic manufacturing, comprising the following steps: providing a substrate for microelectronic manufacturing; forming a silicon oxide dielectric layer on the substrate, the oxidation The silicon dielectric layer is made of tetraethyl orthosilicate (TEOS) as the source material of silicon and is prepared by chemical vapor deposition method. The silicon oxide dielectric layer is treated with a plasma to make the silicon oxide dielectric The electric layer becomes a plasma-treated silicon oxide dielectric layer; an etching pattern photoresist layer is formed on the plasma-treated silicon oxide dielectric layer to locate the etching grooves on the plasma-treated silicon oxide dielectric layer. Position, this step of using the oxide sand dielectric layer as an electric treatment step can enhance the adhesion of the photoresist layer on the plasma-treated silicon oxide dielectric layer; and the isotropic etching method is used to etch the electricity. The slurry processes the silicon oxide dielectric layer to form an etched trench. 8. According to the method described in item 7 of the scope of patent application, wherein the microelectronic paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) --------------- --- ^ — (Please read the notes on the back before copying this page) ——Order-Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs --- J 7 01 4 ο 4 ABCD Patent Application Scope Central Standards of the Ministry of Economic Affairs The Bureau ’s consumer cooperative print manufacturing is selected from the microelectronics manufacturing group consisting of integrated circuit microelectronics manufacturing, solar cell microelectronics manufacturing, ceramic-based microelectronics manufacturing, and flat display microelectronics manufacturing. 'The method according to item 7 of the scope of the patent application, wherein the chemical vapor deposition method (CVD) is selected from the group consisting of a thermal chemical vapor deposition method (CVD) and a plasma enhanced chemical vapor deposition method (PECVD) The vapor phase deposition (CVD) group, and the silicon oxide dielectric layer is selected from the group consisting of a doped silicon oxide dielectric layer and an undoped silicon oxide dielectric layer. 〇 According to the method described in item 7 of the scope of the patent application, the plasma used for plasma treatment is selected from the group consisting of an oxygen atom plasma and a nitrogen atom plasma. 1. The method according to item 7 of the scope of patent application, wherein the isotropic etching method is selected from the group of isotropic etching methods composed of a wet chemical etching method and a high-pressure reactive ion etching method (RIE). 2. An etching groove formed on a silicon oxide dielectric layer in microelectronics manufacturing according to the method described in item 7 of the scope of patent application. 3. A method for forming an etching groove on a dielectric layer in the manufacture of a microelectronic substrate circuit, comprising the following steps: providing a semiconductor substrate; forming a silicon oxide dielectric layer on the semiconductor substrate, the silicon oxide The dielectric layer is made of tetraethyl orthosilicate (TEOS) as the source material of silicon, and is made by chemical vapor deposition (CVD). The silicon oxide dielectric layer is treated with a plasma to make the oxide The silicon dielectric layer 32 uses the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ...... Γ: .installation ... (Please read the note on the back first (Please fill in this page again for details) Thread A8 B8 C8 D8 404017 VI. The scope of patent application becomes a plasma-treated silicon oxide dielectric layer; on the plasma-treated silicon oxide dielectric layer, an etched photoresist layer is formed In order to define the position of the wine glass-shaped etching groove on the plasma-treated silicon oxide dielectric layer, this step of using the silicon oxide dielectric layer as a plasma treatment can enhance the etching pattern of the photoresist layer in the plasma-treated silicon oxide dielectric. Adhesion on the layer; and etching plasma treated silicon oxide dielectric layer with isotropic etching to A wine glass-shaped etching groove is formed. 14. The method according to item 13 of the scope of the patent application, wherein the chemical vapor deposition (CVD) method is selected from the group consisting of thermochemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD). ) Group composed of vapor phase deposition (CVD), and the silicon oxide dielectric layer is selected from the group consisting of a doped silicon oxide dielectric layer and an undoped silicon oxide dielectric layer. group. 15. According to the method described in item 13 of the scope of the patent application, wherein the plasma is selected from the group of plasma consisting of an oxygen atom plasma and a nitrogen atom plasma 0 1. According to item 7 of the scope of patent application In the method, the isotropic etching method is selected from the group of isotropic etching methods composed of a wet chemical etching method and a high-pressure reactive ion etching method (RIE). 17. An etching groove formed in a silicon oxide dielectric layer in the fabrication of integrated circuit microelectronics, which is made according to the method of the 13th scope of the patent application. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). Mm) ---------------- -------- I ---- (Please read the notes on the back before writing this page), 1T line economy Printed by the Consumers' Cooperatives of the Ministry of Standards of the People's Republic of China --- I