552673 經濟部智慧財產局員工消費合作社印製 五、發明說明（/ ) 發明領域 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種藉由去除接觸窗插塞其上表面之損壞層，以 減少接觸阻値之半導體元件的製造方法。 發明背景 在半導體元件的製造技術中，形成半導體基底其主動 元件區與主動元件區上之覆蓋層的連接線是重要的技術之 一。在低積集密度的半導體元件中，接觸窗開口（Contact Hole)可以具有低的高寬比（Aspect Ratio)，也就是與深度比 較具有較大的面積。因此，接觸窗開口可以塡入諸如鋁之 類的金屬。 另一方面，隨著高密度之動態隨機存取記憶體（DRAM) 不斷地推展，記憶胞的面積將變得愈來愈小。因此，元件 積集密度增加的結果，將導致接觸窗尺寸的縮小。故而， 在高積集密度的元件中，例如是記憶元件，其接觸窗開口 的高寬比（Aspect Ratio)必將隨之而變高，亦即，與深度比 較，具有較小的面積。因此，需要一種所謂的埋入式接觸 窗技術（Buried Contact Technique)，此技術係以多結晶矽 (在後文中稱之爲複晶矽）作爲埋入於接觸窗開口中的內連 線材質。然而，高積集密度的需求下，縮小接觸窗開口的 尺寸，卻會導致接觸阻値的增加。 爲解決上述之問題，已有一種以高雜質濃度之摻雜複 晶矽塡入接觸窗開口的方法。然而，複晶矽插塞仍然存在 一些問題。例如是以乾式蝕刻法蝕刻摻雜複晶矽層的過程 (請先閱讀背面之注意. 裝—— 填寫本頁)552673 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (/) FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method of removing damage to the upper surface of a plug by removing a contact window. Layer to reduce the contact resistance of the semiconductor device. BACKGROUND OF THE INVENTION In the manufacturing technology of a semiconductor device, forming a connection line between an active device region and a cover layer on the active device region of a semiconductor substrate is one of the important technologies. In a semiconductor element with a low accumulation density, the contact hole opening may have a low aspect ratio, that is, a larger area compared with the depth. Therefore, the contact window opening can be pierced with a metal such as aluminum. On the other hand, as high-density dynamic random access memory (DRAM) continues to expand, the area of memory cells will become smaller and smaller. Therefore, as a result of an increase in the component density, the size of the contact window will be reduced. Therefore, in a device with a high accumulation density, such as a memory device, the aspect ratio of the opening of the contact window will inevitably become higher, that is, it has a smaller area compared with the depth. Therefore, there is a need for a so-called buried contact technique, which uses polycrystalline silicon (hereinafter referred to as polycrystalline silicon) as the material of the interconnects buried in the opening of the contact window. However, under the requirement of high accumulation density, reducing the size of the opening of the contact window will lead to an increase in contact resistance. In order to solve the above-mentioned problems, there has been a method in which doped polycrystalline silicon with a high impurity concentration is inserted into the opening of the contact window. However, there are still some problems with polycrystalline silicon plugs. For example, the process of etching the doped polycrystalline silicon layer by dry etching (please read the note on the back first. Installation-fill in this page)
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 552673 4731pifdoc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 中，複晶矽層的上表面會因爲電漿中順流而下的離子的作 用而形成一層多餘的材料層（Unwanted Layer )，也就是損 壞層（Damage Layer)。而損壞層的存在，卻會增加複晶矽 與後續製程中覆蓋於主動元件區上方之材料層，例如是形 成電容器之儲存節點（Storage Node)其彼此之間的阻値。 有鑒於此，目前仍需要一種可以降低接觸阻値之半導 體元件的製造方法。 發明摘要 爲了解決上述之問題，本發明之主要目的係提供一種 無損壞層形成於其之上之複晶矽接觸窗插塞的製造方法， 以降低導體材料之間的接觸阻値。 本發明之另一目的係提供一種在複晶矽接觸窗插塞上 形成電容器的方法，以降低其間的接觸阻値。 本發明係去除電漿蝕刻製程所形成的損壞層，以降低 接觸阻値。損壞層係以含有〇2氣體或是在具有〇2與含氟 氣體，例如CF4、C2F6、CHF3與NF3，之混合氣體的電漿 蝕刻去除。= 更詳言之，電容器的形成方法之步驟包括在半導體基 底上形成一層第一絕緣層。以預定之光阻圖案進行第一絕 緣層的蝕刻製程，以在第一絕緣層之中形成裸露出半導體 基底之主動兀件區的接觸窗開口。在第一絕緣層上沉積第 一導體層，例如摻雜複晶矽層，以塡滿接觸窗開口。摻雜 複晶矽層的濃度約爲1.5X 102()at〇mS/cm3或更高，以降低接 觸阻値。其後，以含碳或是含氟氣體之電漿回蝕摻雜複晶 (請先閱讀背面之注意事 裝—— 填寫本頁) 訂·-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 552673 4731pifdoc / 002 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. In the description of the invention (2), the top of the polycrystalline silicon layer The surface will form a layer of excess material (Unwanted Layer) due to the action of the ions flowing down in the plasma, that is, the damage layer. The existence of the damaged layer will increase the resistance between the polycrystalline silicon and the material layer covering the active device area in the subsequent processes, such as the storage node forming the capacitor. In view of this, there is still a need for a method of manufacturing a semiconductor device that can reduce contact resistance. Summary of the Invention In order to solve the above problems, a main object of the present invention is to provide a method for manufacturing a polycrystalline silicon contact window plug with no damage layer formed thereon, so as to reduce the contact resistance between conductive materials. Another object of the present invention is to provide a method for forming a capacitor on a polycrystalline silicon contact window plug to reduce the contact resistance therebetween. The invention removes the damaged layer formed by the plasma etching process to reduce the contact resistance. The damaged layer is removed by plasma etching containing a gas of 0 2 or a mixed gas of 0 2 and a fluorine-containing gas, such as CF4, C2F6, CHF3, and NF3. = In more detail, the method of forming a capacitor includes forming a first insulating layer on a semiconductor substrate. An etching process of the first insulating layer is performed with a predetermined photoresist pattern to form a contact window opening in the first insulating layer that exposes the active element region of the semiconductor substrate. A first conductor layer, such as a doped polycrystalline silicon layer, is deposited on the first insulating layer to fill the contact window opening. The concentration of the doped polycrystalline silicon layer is about 1.5X 102 () atOmS / cm3 or higher to reduce the contact resistance. Afterwards, the doped polycrystals are etched back with a plasma containing carbon or fluorine gas (please read the precautions on the back first-fill in this page) Order ·-
本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 552673 A7 B7 473 丨 pifdoc/〇()2 五、發明說明（,） 砂層，以形成一複晶砂插塞。在此時，因爲電漿能量造成 之順流而下的離子會在複晶矽層的表面上形成一層損壞 --裝--- (請先閱讀背面之注意事t填寫本頁) 層。 在第一絕緣層與複晶矽插塞上覆蓋一層第二絕緣層。 在第二絕緣層上沉積一層光阻層，並定義其圖案，以在光 阻層中界定出預定用以定義儲存節點其區域的圖案（亦即 光阻圖案）。以圖案化之光阻層爲蝕刻罩幕’蝕刻第二絕緣 層，以在其中形成一開口。此開口裸露出複晶砂接觸窗插 塞之上的損壞層以及損壞層外部之第一絕緣層的一部份。 然後，將圖案化的光阻層自半導體基底之中移除。 之後，以乾式蝕刻技術移除位於複晶矽插塞上方、且 裸露於開口的損壞層。乾式蝕刻係使用含有02之氣體，或 是使用混合氣體，此混合氣體係含有氣體以及選自於 cf4、c2f6、chf3與NF3所組成族群中的至少一種含氟氣 體。This paper size is in accordance with Chinese National Standard (CNS) A4 (210 x 297 mm) 552673 A7 B7 473 丨 pifdoc / 〇 () 2 5. Description of the invention (,) Sand layer to form a polycrystalline sand plug. At this time, the ions flowing down due to the energy of the plasma will form a layer of damage on the surface of the polycrystalline silicon layer. (Please read the precautions on the back to fill in this page). A second insulating layer is covered on the first insulating layer and the polycrystalline silicon plug. A photoresist layer is deposited on the second insulating layer and its pattern is defined, so as to define a pattern (ie, a photoresist pattern) in the photoresist layer that is intended to define a region of the storage node. The second insulating layer is etched using the patterned photoresist layer as an etching mask 'to form an opening therein. This opening exposes the damaged layer above the polycrystalline sand contact window plug and a portion of the first insulating layer outside the damaged layer. Then, the patterned photoresist layer is removed from the semiconductor substrate. Then, the dry-etching technique is used to remove the damaged layer above the polycrystalline silicon plug and exposed to the opening. Dry etching uses a gas containing 02 or a mixed gas. The mixed gas system contains a gas and at least one fluorine-containing gas selected from the group consisting of cf4, c2f6, chf3, and NF3.
在去除損壞層之後，在開口之中塡入第二導體層。較 佳的第二導體層爲複晶矽層。 經濟部智慧財產局員工消費合作社印製 在上述方法中，摻雜複晶矽層上表面所形的損壞層， 係在回蝕刻摻雜複晶矽層以形成複晶矽插塞的過程中，因 爲遭受電漿能量所致。而且，在蝕刻第二絕緣層以形成開 口的餓刻過程中’在複晶砂插塞上亦有可能產生另一屏損 壞層。因此，有鑒於製程經濟效益的考量，在触刻第一絕 緣層以形成開口的製程之後，以一次的乾式蝕刻製程將所 有的損壞層一倂去除◦不過，在蝕刻摻雜複晶矽層以形成 表紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公爱） 552673 4731pifdoc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（p) 複晶矽插塞的步驟之後，可以額外再進行一次乾式蝕刻製 程。 根據本發明之目的，在第一絕緣層中形成接觸窗開口 之後，係在基底的結構上沉積一層摻雜複晶矽層。其後， 摻雜複晶矽層，係以含碳或是含氟的氣體進行電漿回蝕 刻，以形成複晶矽插塞。此時，在電漿能量造成的加速離 子會在複晶矽接觸窗插塞的表面上形成一層損壞層。因 此，以上述之乾式飩刻技術去除會增加複晶矽接觸窗插塞 與後續形成之第二導體層其彼此之間之接觸阻値的損壞 〇 圖式之簡單說明 參照以下所附之圖式，熟悉此技藝者可以更瞭解本發 明，並且可以更明白本明之目的。 第1A圖至第1F圖，係繪示繪示依照本發明第一實施 例，一種製造半導體元件之新方法的流程圖； 第2A圖至第2B圖，係繪示繪示依照本發明第二實施 例，一種製造半導體元件之新方法的流程圖；以及 第3A圖至第3C圖，係繪示繪示依照本發明第三實施 例，一種製造半導體元件之新方法的流程圖。 圖式標記說明： 10 半導體基底 11 隔離區 12 閘極氧化層 13 閘極 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事 JI: 裝—— 填寫本頁) .After removing the damaged layer, a second conductor layer is inserted into the opening. A preferred second conductor layer is a polycrystalline silicon layer. In the above method, the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the damage layer formed on the upper surface of the doped polycrystalline silicon layer during the process of etching back the doped polycrystalline silicon layer to form a polycrystalline silicon plug. Because of suffering from plasma energy. Moreover, in the process of etching the second insulating layer to form an opening, there may be another layer of screen damage on the polycrystalline sand plug. Therefore, in consideration of the economic benefits of the process, after the process of etching the first insulating layer to form an opening, all the damaged layers are removed in a single dry etching process. However, the doped polycrystalline silicon layer is etched to Form sheet paper size applies Chinese National Standard (CNS) A4 specification (210 χ 297 public love) 552673 4731pifdoc / 002 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (p) Steps of polycrystalline silicon plug After that, an additional dry etching process can be performed. According to the purpose of the present invention, after a contact window opening is formed in the first insulating layer, a doped polycrystalline silicon layer is deposited on the structure of the substrate. Thereafter, the doped polycrystalline silicon layer is plasma etched with a gas containing carbon or fluorine to form a polycrystalline silicon plug. At this time, the accelerated ion caused by the plasma energy will form a layer of damage on the surface of the polycrystalline silicon contact window plug. Therefore, the removal of the dry-etching technique described above will increase the damage of the contact resistance between the polycrystalline silicon contact window plug and the second conductor layer formed subsequently. For a brief description of the drawings, please refer to the attached drawings below. Those skilled in the art can better understand the present invention and can better understand the purpose of the present invention. 1A to 1F are flowcharts showing a new method for manufacturing a semiconductor device according to a first embodiment of the present invention; and FIGS. 2A to 2B are diagrams showing a second method according to the present invention The embodiment is a flowchart of a new method for manufacturing a semiconductor device; and FIGS. 3A to 3C are flowcharts showing a new method for manufacturing a semiconductor device according to a third embodiment of the present invention. Description of graphical symbols: 10 Semiconductor substrate 11 Isolation area 12 Gate oxide 13 Gate 7 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back first JI: Installation -Fill out this page).
552673 4731 pit、doc/002 ^ 五、發明說明（夕） 14 第一*絕緣層 1 5 接觸窗開口 16 第一導體層 16a 複晶矽插塞 16b、37b 損壞層 17、35 第二絕緣層 18 第二圖案化光阻層 19 開口 20、38 第二導體層 20a 儲存節點 36 複晶矽插塞 3 8 第二複晶砂層 較佳實施例之詳細說明 本發明將以較佳實施例並配合所附圖式作詳細說明如 下。然而，本發明可以不同的形式加以潤飾，而且後述之 實施例亦並非用以限定本發明。對於熟習此技藝者而言， 這些實施例係用以詳細且完整地揭露本發明，並完全地表 達本發明的範圍◦圖式中，各層的厚度與區域係誇張化以 淸楚地表達本發明。任何熟悉此技藝者當明白，當一材料 層被述及位於另一材料層”上”或位於基底”上”，可以是指 直接覆蓋在另一材料層上或基底上，或是指其彼此之間存 在一層插入層（Intervening Layer) ◦相反地，當一元件被述 及”直接”覆蓋於另一元件”之上”，則是在兩元件之間並不 存在另一個插入元件。而且，每一個實施例的說明與圖示 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -I I I 4. I I It I I (請先閱讀背面之注意事項再填寫本頁) .裝 ----訂--------秦 經濟部智慧財產局員工消費合作社印製 552673 473 1 pif doc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 ) 亦包含與其互補的導體形式。 (第一實施例） 第1A圖至第1F圖係繪示依照本發明第一實施例之一 種半導體元件，且特別是堆疊電容器之製造方法的流程 圖。請參照第〗A圖，在半導體基底10之中形成隔離區（亦 即，場氧化層）Π，以界定出主動區與非主動區。在半導體 基底10的主動區上形成閘極13。眾所皆知，在基底10與 閘極Π之間的閘極氧化層12係用以電性隔絕基底10與閘 極13。在閘極13外側、半導體基底10的主動區上形成源 極/汲極區（未繪示出）。以習知的化學氣相沉積法（CVD)， 在半導體基底10以及閘極13上形成一層第一絕緣層14， 此絕緣層14例如是硼磷矽玻璃（BPSG)層、USG層或與其 性質相似者。接著，可以在第一絕緣層14上進一步形成一 層氮化層，較佳的是形成一層氮化矽層。氮化矽層與第一 絕緣層14以及第二絕緣層17具有不同的蝕刻特性，因此， 在進行蝕刻程序的過程中可以作爲蝕刻終止層（Stopper Layer )。在第一絕緣層14上形成一層第一光阻層（未繪示 出），並將其圖案化成預定之圖案（第一光阻圖案），以用以 定義形成接觸窗之區域。接著，以第一光阻圖案爲罩幕， 蝕刻第一絕緣層14，以形成接觸窗開口 15，此接觸窗開口 15係裸露出源極/汲極區的上表面。蝕刻的方法例如是以活 性離子軸刻法（Reactive Ion Etching，RIE)，其可以以CF4、 CHF3與氬施行之。在接觸窗開口 15與第一絕緣層14上沉 積一層第一導體層16。較佳的第一導體層16爲摻雜複晶 「裝 (請先閱讀背面之注意事填寫本頁) y; 1111111 552673 4731pifdoc/002 A7 -- --_B7__一^ - 五、發明說明（9 ) 矽層16。摻雜複晶矽層16之濃度約略爲1.5 X l〇2()atoms/cm。或更大者，以解決積體電路高度積集化之 後，因爲縮小接觸窗尺寸所造成之接觸阻値增加的問題。 其後，以回蝕刻製程去除接觸窗開口 15以外的掺雑複晶矽 層16，以形成複晶矽插塞16a ◦回蝕刻製程係使用含氟之 化合物，所使用之氣體包括和〇2、N2、SF6、HBr或其 相似物。 經濟部智慧財產局員工消費合作社印制衣 請參照第圖，在此步驟中，複晶矽接觸窗插塞16a 的上表面會因爲電槳能量下所造成的加速離子，而形成一 層損壞層l6b。而此損壞層16b卻會增加複晶砂接觸窗插 塞16a與後續用以形成儲存節點之摻雜複晶矽層其彼此之 間的接觸阻値。由於在蝕刻後續形成之第二絕緣層（請參照 第1C圖標記17)，以形成用以製作儲存節點之開口 19的 過程中’在複晶矽接觸窗插塞16a的表面上亦有可能產生 另一層損壞層’因此，爲了製程的經濟效益，較佳的方法 並不在此步驟中，以乾式蝕刻法去除損壞層16b，而是依 照本發明實施例，蝕刻第二絕緣層1 7以在其中形成開口 19 之後，再以乾式蝕刻法去除損壞層16b。不過，損壞層16b 亦可以在此步驟中以乾式蝕刻製程去除之。 請參照第1C圖，以習知的方法，例如是電漿增強型 化學氣相沉積法（PECVD)在第一絕緣層14上形成一層第二 絕緣層17。第二絕緣層π例如是磷矽玻璃（PSG)層、硼砂 玻璃（BSG)層或是其相似物。第二絕緣層n之厚度係用以 界定儲存節點的高度。接著，以傳統的微影製程，在第二 10 本紙張尺度適用中國國家標準（CNS〉A4規格⑵G X 297公髮) -- 552673 4731pifdoc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（分） 絕緣層17上形成一層第二光阻圖案18，以用以定義儲存 節點之開口區域。其後，以第二光阻圖案18爲罩幕，蝕刻 第二絕緣層17，以形成開口 19 ◦開口 19係裸露出複晶矽 插塞16a的損壞層16b並且裸露出損壞層16b以外之第一 絕緣層14的一部份，如第id圖所示。蝕刻第二絕緣層π 的方法可以使用含有CF4或CHF3之氣體。其後，將第二光 阻層1 8自第二絕緣層1 7上移除。 之後，以乾式蝕刻製程移除損壞層16b。乾式蝕刻製 程係在含有〇2的蝕刻配方之下施行。而且在上述蝕刻配方 之中更進一步加入至少一種含氟的氣體。含氟氣體係選自 於CF4、C2F6、CHF3與NF3所組成之族群的其中之一 ◦乾 式蝕刻製程的條件如下：功率（Power)約爲30瓦至500瓦 的，較佳的功率約爲200瓦；氬氣的流量約爲l〇sccm至 200sccm，較佳的流量約爲200sccm ;壓力約爲30毫托至 300毫托，較佳的壓力約爲15〇毫托；氧氣的流量約爲5sccm 至lOOsccm，較佳的流量約爲50sccm ; CF4的流量約爲 5sccm至200sccm，較佳的流量約爲5sccm。 經由上述之乾式蝕刻步驟之後，複晶矽接觸窗插塞16a 與覆蓋於其之上的第二導體層之間具有良好的接觸性質。 在去除損壞層之後，在開口 19之中沉積一層第二導體 層2〇，以作爲儲存電極之用，如第1E圖所示。較佳的第 二導體層20之材質爲摻雜複晶矽層20。接著，將開口 19 以外的摻雜複晶矽層2〇平面性蝕刻去除，以形成堆疊儲存 節點（Stacked Storage Node)2〇a。平面性去除的方法例如是 (請先閱讀背面之注意事填寫本頁) 裝 一al，I' /^>χτο\ 552673 A7 B7 473lpird〇c/002 五、發明說明（了） 化學機械硏磨法或乾式回蝕刻法。其後，將堆疊儲存節點 20a以外的第二絕緣層17蝕刻去除，如第1F圖所示。飩 刻去除第一絕緣層i 7的較佳方法係使用HF作爲蝕刻液。 第一貫施例 柱狀電容器之儲存節點2〇亦可以採用第2A圖至第2B 圖所繪示之方法予以製造。圖示中與第丨A圖至第1F圖中 具有相同功能的部分係以相同的標記表示，而且亦省略其 說明。 第2A圖至第2B圖係繪示根據本發明第二實施例之一 種半導體元件，且特別是一種柱狀電容器的製造方法的流 程圖。請爹照第2A圖，以上述之乾式蝕刻技術，蝕刻去 除如第1D圖所示之損壞層16b之後，在部分的開口 19之 中塡入第二導體層2〇，以作爲儲存節點。較佳的第二導體 層20之材質爲摻雜複晶矽20。接著，以例如化學機械硏 磨法或乾式回蝕刻法去除位於開口 1 9以外之摻雜複晶砂 層20，以形成柱狀的儲存節點20a。。其後，触刻去除柱 狀儲存節點2〇a以外之第一絕緣層1 7，如第2B圖所示。 倉虫刻去除第二絕緣層1 7的較佳方法係使用HF做爲触刻製 程之融刻液◦另，依照製程的需求，絕緣層亦可沉積於開 口之餘存部份。 第3 A圖至第3 C圖係繪不根據本發明第三眚施例之一 種複晶砂接觸窗插塞之製造方法的流程圖。在第三眚施例 中，係省略與第1 A圖至第1B圖相同的製程步驟。請參照 第3B圖，損壞層37b係形成在複晶矽插塞37a的表面上。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） t f — I ^^^^1 · I I I I I I I ^ ·111111 —I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 552673 473 丨—_B7_ 五、發明說明（im 接著，以上述之乾式蝕刻法蝕刻去除損壞層37b。在去除 損壞層37b之後，在第二絕緣層35與蝕刻後的複晶矽插塞 上沉積一層第二導體層38，如第3C圖所示。第二導體層 38可以是複晶矽層。因此，可以使複晶矽插塞36與第二 複晶矽層38之間的接觸阻値較低於損壞層存在於其二者 之間者。 另，可以以傳統的微影方法形成堆疊電容器。首先， 沉積一層複晶矽層（未繪示出），其厚度係足以定義電容器 之儲存節點的高度者。接著，在複晶矽層上沉積一層光阻 層（未繪示出），並將其圖案化，以形成光阻圖案。其後， 以光阻圖案爲罩幕，蝕刻複晶矽層，以形成儲存節點。 本發明之方法，係以乾式蝕刻技術去除形成於複晶矽 接觸窗插塞其表面上多餘的損壞層，以降低接觸阻値。 雖然本發明已以較佳實施例詳細說明如上，然而任何 熟習此技藝者當明白，在不脫離本發明的精神與範圍，當 可作各種的更動與潤飾。 經濟部智慧財產局員工消費合作社印製 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）552673 4731 pit, doc / 002 ^ V. Description of the invention (Even) 14 First * Insulating layer 1 5 Contact window opening 16 First conductor layer 16a Polycrystalline silicon plug 16b, 37b Damage layer 17, 35 Second insulating layer 18 Second patterned photoresist layer 19 openings 20, 38 second conductor layer 20a storage node 36 polycrystalline silicon plug 3 8 detailed description of the preferred embodiment of the second complex crystal sand layer The drawings are explained in detail as follows. However, the present invention can be decorated in different forms, and the embodiments described later are not intended to limit the present invention. For those skilled in the art, these embodiments are used to disclose the present invention in detail and completely, and fully express the scope of the present invention. In the figure, the thickness and area of each layer are exaggerated to express the present invention clearly. . Anyone familiar with this art should understand that when a material layer is referred to as being "on" or "on a substrate" another material layer, it can mean directly covering another material layer or substrate, or referring to each other. There is an intervening layer between them. Conversely, when an element is referred to as "directly" covering another element, there is no other intervening element between the two elements. In addition, the description and illustration of each embodiment are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -III 4. II It II (Please read the precautions on the back before filling this page) Packing ---- Order -------- Printed by the Consumers 'Cooperative of Intellectual Property Bureau of Qin Ministry of Economic Affairs 552673 473 1 pif doc / 002 A7 B7 Printed by the Consumers' Cooperative of Intellectual Property Bureau of Ministry of Economic Affairs 6) It also includes complementary conductor forms. (First Embodiment) FIGS. 1A to 1F are flowcharts showing a method for manufacturing a semiconductor element, and particularly a stacked capacitor, according to a first embodiment of the present invention. Referring to FIG. A, an isolation region (ie, a field oxide layer) is formed in the semiconductor substrate 10 to define an active region and an inactive region. A gate electrode 13 is formed on the active region of the semiconductor substrate 10. It is well known that the gate oxide layer 12 between the substrate 10 and the gate Π is used to electrically isolate the substrate 10 and the gate 13. A source / drain region (not shown) is formed on the active region of the semiconductor substrate 10 outside the gate electrode 13. A conventional chemical vapor deposition (CVD) method is used to form a first insulating layer 14 on the semiconductor substrate 10 and the gate electrode 13. The insulating layer 14 is, for example, a borophosphosilicate glass (BPSG) layer, a USG layer, or a combination thereof. Similar. Next, a nitride layer may be further formed on the first insulating layer 14, and a silicon nitride layer is preferably formed. The silicon nitride layer has different etching characteristics from the first insulating layer 14 and the second insulating layer 17. Therefore, the silicon nitride layer can be used as an etching stopper (Stopper Layer) during an etching process. A first photoresist layer (not shown) is formed on the first insulating layer 14 and patterned into a predetermined pattern (first photoresist pattern) to define a region where the contact window is formed. Next, using the first photoresist pattern as a mask, the first insulating layer 14 is etched to form a contact window opening 15. The contact window opening 15 exposes the upper surface of the source / drain region. The etching method is, for example, Reactive Ion Etching (RIE), which can be performed using CF4, CHF3, and argon. A first conductor layer 16 is deposited on the contact window opening 15 and the first insulating layer 14. The preferred first conductor layer 16 is doped polycrystalline (loaded (please read the notes on the back and fill in this page) y; 1111111 552673 4731pifdoc / 002 A7---_ B7__ 一 ^-5. Description of the invention (9 ) Silicon layer 16. The concentration of doped polycrystalline silicon layer 16 is approximately 1.5 X 10 (atoms / cm. Or greater) to solve the problem caused by the reduction of the contact window size after the integration of the integrated circuit height. After that, the erbium-doped polycrystalline silicon layer 16 other than the contact window opening 15 is removed by an etch-back process to form a poly-crystalline silicon plug 16a. The etch-back process uses a fluorine-containing compound. The gases used include 〇2, N2, SF6, HBr or the like. Please refer to the figure for the printed clothing of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In this step, the polycrystalline silicon contact window plug 16a is on the upper surface. A damaged layer 16b will be formed due to the accelerated ions caused by the electric paddle energy. This damaged layer 16b will increase the polycrystalline sand contact window plug 16a and the subsequent doped polycrystalline silicon layer used to form the storage node. The contact resistance between each other. Because of the second Insulating layer (please refer to Fig. 1C mark 17) in the process of forming the opening 19 used to make the storage node 'another layer of damage may be generated on the surface of the polycrystalline silicon contact window plug 16a'. Therefore, in order to The economic benefits of the process. The preferred method is not to remove the damaged layer 16b by dry etching in this step, but to etch the second insulating layer 17 to form the opening 19 therein according to the embodiment of the present invention, and then dry the The damaged layer 16b is removed by etching. However, the damaged layer 16b can also be removed in this step by a dry etching process. Please refer to FIG. 1C for a conventional method such as a plasma enhanced chemical vapor deposition (PECVD) ) A second insulating layer 17 is formed on the first insulating layer 14. The second insulating layer π is, for example, a phosphosilicate glass (PSG) layer, a borax glass (BSG) layer, or the like. The thickness of the second insulating layer n It is used to define the height of the storage node. Then, using the traditional lithographic process, the Chinese national standard (CNS> A4 size⑵G X 297 issued) is applied on the second 10th paper scale-552673 4731pifdoc / 002 A7 B7 Ministry of Economic Affairs wisdom Printed by the employee's consumer cooperative of the Property Bureau V. Description of the invention (minutes) A second photoresist pattern 18 is formed on the insulating layer 17 to define the opening area of the storage node. Thereafter, the second photoresist pattern 18 is used as a screen The second insulating layer 17 is etched to form an opening 19. The opening 19 exposes the damaged layer 16b of the polycrystalline silicon plug 16a and exposes a part of the first insulating layer 14 other than the damaged layer 16b, as shown in FIG. As shown, the method of etching the second insulating layer π can use a gas containing CF4 or CHF3. Thereafter, the second photoresist layer 18 is removed from the second insulating layer 17. Thereafter, the damaged layer 16b is removed by a dry etching process. The dry etching process is performed under an etching recipe containing 0 2. Furthermore, at least one fluorine-containing gas is further added to the above-mentioned etching recipe. The fluorine-containing gas system is selected from one of the groups consisting of CF4, C2F6, CHF3 and NF3. The conditions of the dry etching process are as follows: The power is about 30 to 500 watts, and the preferred power is about 200. Watt; argon flow rate is about 10 sccm to 200 sccm, the preferred flow rate is about 200 sccm; pressure is about 30 mTorr to 300 mTorr, the preferred pressure is about 15 mTorr; oxygen flow rate is about 5 sccm To 100 sccm, the preferred flow rate is about 50 sccm; CF4 flow rate is about 5 sccm to 200 sccm, and the preferred flow rate is about 5 sccm. After the dry etching step described above, the polycrystalline silicon contact window plug 16a and the second conductor layer covering it have good contact properties. After removing the damaged layer, a second conductor layer 20 is deposited in the opening 19 as a storage electrode, as shown in FIG. 1E. A preferred material of the second conductor layer 20 is a doped polycrystalline silicon layer 20. Next, the doped polycrystalline silicon layer 20 other than the opening 19 is planarized and removed to form a stacked storage node 20a. The method for removing flatness is (please read the precautions on the back and fill in this page). Install an al, I '/ ^ > χτο \ 552673 A7 B7 473lpird〇c / 002 5. Description of the invention Method or dry etch-back method. Thereafter, the second insulating layer 17 other than the stacked storage node 20a is etched away, as shown in FIG. 1F. A preferred method for etch-off removing the first insulating layer i 7 is to use HF as an etchant. In the first embodiment, the storage node 20 of the columnar capacitor can also be manufactured by the methods shown in FIGS. 2A to 2B. In the figure, parts having the same functions as those in FIGS. 丨 A to 1F are denoted by the same reference numerals, and descriptions thereof are also omitted. FIGS. 2A to 2B are flowcharts showing a method for manufacturing a semiconductor device and, in particular, a cylindrical capacitor according to a second embodiment of the present invention. Please refer to FIG. 2A, and use the dry etching technique described above to remove the damaged layer 16b as shown in FIG. 1D, and then insert a second conductive layer 20 into part of the opening 19 as a storage node. A preferred material of the second conductor layer 20 is doped polycrystalline silicon 20. Next, the doped polycrystalline sand layer 20 located outside the opening 19 is removed by, for example, a chemical mechanical honing method or a dry etch-back method to form a columnar storage node 20a. . After that, the first insulating layer 17 other than the columnar storage node 20a is removed by touch engraving, as shown in FIG. 2B. The best method for removing the second insulating layer 17 by the worm-cutter method is to use HF as the melting solution for the touch-etching process. In addition, according to the requirements of the process, the insulating layer can also be deposited on the remaining part of the opening. FIG. 3A to FIG. 3C are flowcharts illustrating a method for manufacturing a polycrystalline sand contact window plug according to a third embodiment of the present invention. In the third embodiment, the same process steps as those in FIGS. 1A to 1B are omitted. Referring to FIG. 3B, the damage layer 37b is formed on the surface of the polycrystalline silicon plug 37a. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) tf — I ^^^^ 1 · IIIIIII ^ · 111111 —I (Please read the precautions on the back before filling this page) Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau 552673 473 丨 __B7_ V. Description of the invention (im Next, the damaged layer 37b is removed by etching using the dry etching method described above. After removing the damaged layer 37b, the second insulating layer 35 and the etched layer A second conductor layer 38 is deposited on the crystalline silicon plug, as shown in FIG. 3C. The second conductor layer 38 may be a polycrystalline silicon layer. Therefore, the polycrystalline silicon plug 36 and the second polycrystalline silicon layer 38 may be formed. The contact resistance between them is lower than that if the damage layer exists between them. In addition, a stacked capacitor can be formed by a conventional lithography method. First, a polycrystalline silicon layer (not shown) is deposited with a thickness It is sufficient to define the height of the storage node of the capacitor. Next, a photoresist layer (not shown) is deposited on the polycrystalline silicon layer and patterned to form a photoresist pattern. Thereafter, a photoresist pattern is used For the mask, etching the polycrystalline silicon layer, The storage node is formed. The method of the present invention uses dry etching technology to remove the excess damaged layer formed on the surface of the polycrystalline silicon contact window plug to reduce the contact resistance. Although the present invention has been described in detail in the preferred embodiment as above However, any person skilled in the art should understand that various modifications and retouching can be made without departing from the spirit and scope of the present invention. Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economics 3 This paper applies the Chinese National Standard (CNS) A4 size (210 X 297 mm)