經濟部中央標準局員工消资合作杜印裝 416140 A7 B7 五、發明説明（/ ) 發明背景： (1) 發明技術領域： 本發明係有關於一種用以製造動態隨機存 取記億體（dram )半導體裝置的方法*尤指 一種有關於用以產生有關周邊區域之接觸結 構並同時形成DRAM記億體單元之電容節點 結構的方法 (2) 先前技術說明： 由於DRAM晶片的密度增加至十億位元的 水平，所以DRAM單元的面積必須被減少。所 減少的DRAM單元面積係使用大約0.15微米 或更低之設計準則而獲致。該先進的設計準則 對於DRAM單元，以及DRAM晶片周邊區域 之特殊元件有所要求。例如，爲了獲得所欲之 性能，DRAM裝置的電容量必須藉由具有至 少一微米髙度之電容節點的使用而被維持。在 試圖開啓連接至DRAM電容結構下方特徵 (feature)之接觸孔時，被用以保護髙電容結構 的厚絕緣層將導致製程的複雜性。此外，該厚 絕緣層亦將產生高縱橫比之使用於互連結構 與DRAM晶片周邊區域之基板元件間連通的 接觸（contact)或介層孔（via hole)。本發明將說 明一使用雙重鑲嵌製程之嶄新製程，其中該第 2 ---I-丨-^----裝--^----訂------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公i) 經濟部中央標準局員工消費合作社印聚 416140 A7 B7 五、發明説明（» 一道鑲嵌製程將使得dram單元區域中的髙 電容節點與周邊區域中的下互連結構同時產 生〃第二道鑲嵌製程則允許連接至DRAM電容 結構與下互連結構之爲金靥所塡充的窄介層 孔的產生被完成。諸如Chou等人在11.8.1^1.]\〇· 5,731,236 與 Jeng 等人在 U.S. Pat. No. 5,710,073之習知技術所揭示電容結構、自行校 準接觸（self-aligned contact，SAC)結構與互 連結構之結合，然而，這些習知技術並未提供 使甩於本發明之以dram單元、電容節點結構 以及使用於dram晶片周邊區域之互連結構 同時形成爲特徵之雙重嫌嵌製程。 發明之簡要說明： 本發明主要目的係爲提供一種同時產生髙 密度DRAM單元之電容節點結構以及周邊裝 置之互連結構。 本發明之次一目的係爲使用一雙重鑲嵌技 術以允許接觸和介層孔被產生於厚絕緣層 中，並以髙縱橫比的結構被塡充。 本發明之另一目的係爲刻劃一氮化矽層， 並使用下面爲厚氧化矽層之經刻剴的氮化矽 層作爲第二道鑲嵌製程中的阻絕層（stop layer)，該第二道鑲嵌製程係被使用以開啓連 3 本紙張尺度適用中國國家標準（ CNS ) Λ4規格（210 X 297公釐) ---------t--,----ΐτ------.^ (锜先閱讀背面之注意事項再填寫本頁) 416140 Α7 Β7 經濟部中央標準局員工消费合作社印製 五、發明説明（/) 接至周邊字元線結構與半導體基板中之一區 域的接觸孔。 本發明之又一目的係爲使用二層的自行校 準接觸（SAC )窗口，以允許髙電容節點結構 與半導體基板中的源極/汲極區域接觸。 根據本發明之同時產生髙密度DRAM單元 電容節點結構與周邊區域中之互連結構之以 雙重錶嵌製程與二層SAC窗口的使用爲特徵 的方法已被開發。爲一層氮化矽層與位於多晶 矽化金靥閘極結構邊緣之氮化矽間隙壁 (spacer)所覆蓋之第一層多晶矽化金屬（金屬 矽化物-多晶矽）閘極結構係被形成於DRAM 單元區域，而爲一第二氮化矽所覆蓋之多晶矽 化金屬閘極結構係被形成於DRAM晶片周邊 區域》在不爲多晶矽化金羼閘極結構所覆蓋之 DRAM單元區域中形成源極/汲極區域後，暴露 出金靥矽化物層頂端表面的一部份之窗口係 被形成於周邊區域之多晶矽化金靥閘極結構 之覆蓋（cap ping)氮化砂層中。第一氧化政層係 被沈積並刻劃以形成第一層之SAC窗口，該窗 口之寬度係大於DRAM單元逦域中之爲氮化 矽所覆蓋的多晶矽化金屬閘極結構之間距，以 暴露出爲氮化矽所覆蓋之多晶矽化金屬閘極 結構間的源極/汲極區域*並暴露出爲氮化矽所 4 本紙張尺度適用中國國家標ίΤϋ) Λ4規格（210X297公釐） "~' ---------f------"------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員4消費合作社印製 416140 A7 _B7_ 五、發明説明（P ) 覆蓋之多晶閛極結構頂端表面的一部份。該刻 劃程序亦被使用於開啓第一氧化矽層中的接 觸孔，以暴露出在周邊區域中之半導體基板的 第一區域。導電插塞（conductive plug)係於後 序被形成於SAC窗口中，以形成SAC結構， 而一導電插塞結構亦被形成於周邊區域中的 接觸孔。 第二氧化矽層係被沈稹並刻劃，以在第二 氧化矽層中開啓位元線接觸孔，而暴露出 DRAM單元區域中的SAC結構，以被使用爲後 序位元線接觸結構；並在第二氧化矽層中開啓 接觸孔，以暴露出周邊區域中的導電插塞結 構。爲氮化矽層所覆蓋之第二層多晶矽化金靥 結構係被形成於DRAM區域中，該爲氮化矽所 覆蓋之第二層多晶矽化金屬閘極結構其中之 一的下面多晶矽元件係與位元線接觸孔中的 SAC結構接觸，而另一爲氮化矽所覆蓋之第二 層多晶矽化金靥閘極結構的下面多晶矽元件 係與周邊區域中的導電插塞結構接觸。氮化矽 間隙壁係被形成於爲氮化矽所覆蓋之第二層 多晶矽化金靥閘極結構邊緣。一第三氧化矽層 與位於其上的氮化矽層係被沈積，並接著將氮 化矽層刻劃以形成氮化矽硬式罩幕。在dram 單元區域之氮化矽硬式罩幕中的窗口將暴露 5 本紙張尺度適用中國國家標準IcNS ) A4規格（2HT/297公f ) '~ ----：-----^--„----.-1T------Φ, (請先閱讀背面之注意事項再填寫本頁) 416140 Α7 Β7 經濟部中央標準局員工消費合作杜印裝 五、發明説明（y) 出位於爲氮化矽所覆蓋之第二層多晶矽化金 靥閘極結構間距正上方以及位於爲氮化矽所 覆蓋之第一層多晶矽化金靥閘極結構間之 SAC結構正上方區域中之第三氧化矽層的頂 端表面*其將被使用爲電容節點接觸。氮化矽 硬式罩幕中之其他的窗口則位於周邊區域中 爲氮化矽所覆蓋之多晶矽化金羼閘極結構之 氮化矽層中的窗口的正上方，並位於周邊區域 中半導髏基板之第二通域的正上方。 一第四氧化矽層係被沈積並刻劃以產生第 二層SAC窗口於第四氧化矽層與爲氮化矽硬 式罩幕之窗口所暴露之第三氧化矽層中，而該 暴露出SAC結構的第二層SAC窗口係被使用 爲DRAM單元區域中的電容節點接觸。第四氧 化矽層以及爲氮化矽硬式罩幕之窗口所暴露 出之第三氧化矽層、第二氧化矽層與第一氧化 矽層之刻劃將使多晶矽化金靥閘極結構與位 於周邊區域之半導體基板的第二區域暴露 出鎢層係被沈積並施以化學機械硏磨製程 (CMP ) *以將鎢自第四氧化矽層的頂端表 面移除，而產生鑲嵌電容節點結構於第四氧化 矽窗口與第二層SAC窗口中，其係與位於第一 層SAC窗口之用於電容節點接觸的SAC結構 接觸並位於其上方。該CMP製程亦在周邊區 6 本紙張尺度適用中國國家標導（CNsTXl規格（2ί〇Χ297公釐） ----μ,-----裝—；----訂------線 (請先閱讀背面之注意事項再填寫本頁) 416140 A7 B7 M濟部中央標準局員工消費合作社印製 五、發明説明（>) 域中產生鑲嵌下互連結構，以接觸多晶矽化金 靥閘極結構之金靥矽化物層並接觸半導體基 板的第二區域。第四氧化矽層所暴露出的區域 係被選擇性地移除，並於下面氮化矽硬式罩幕 上終止，以產生由氮化矽硬式罩幕向上延伸的 電容節點結構以及下互連結構。 電容介電層與電容單元電極板結構係被形 成於電容節點結構上，以產生DRAM電容結 構。一第五氧化係層係被沈積，被以CMP製 程平坦化，並被刻劃，以開啓連接至DRAM單 元中電容單元電極板結構頂端表面、錶嵌下互 連結構，以及爲氮化矽所覆蓋之第二層多晶矽 化金靥之金靥矽化物層的介層孔，其將在周邊 區域與導電插塞結構接觸。其次，一鎢層係被 沈積並接著施以CMP製程，以產生鑲嵌上插 塞結構，而接觸DRAM單元中的電容單元電極 板以及下互連結構以及周邊區域中之爲氮化 矽所覆蓋之第二層多晶矽化金觴閘極電極。上 互連結構係於後序被形成，以位於上鎮嵌插塞 結構上方並與其接觸。 圖示之簡要說明： 本發明之目的與其他優點係參考附圖而被 說明於較佳實施例中，其中： 7 本紙張尺度適疋中國國家標準（CNS ) A4規格（210X2W公釐7 — — ----------¾.--.----1T------1 {請先閱讀背面之注意事項再填寫本頁) 416140 A7 B7 經濟部中央標準局員工消費合作杜印製 五、發明説明（7 ) 圖1-20係以示意剖面圖示用以同時產生 DRAM單元之電容節點以及位於DRAM晶片 周邊區域之元件甩的互連結構之主要製造步 驟。 發明詳細說明： 本發明爲一種同時形成DRAM軍元之電容 節點結構與位於DRAM晶片周邊通域之互連 結構之以使用雙重錶嵌製程爲特徵的方法。一 由具有<100>結晶取向之單晶矽所組成的半導 體基板1係被使用並示意地於圖1中。半導體 基板1之區域80將被使用爲髙密度DRAM單 元的舉例，而區域則被使用以說明DRAM 晶片之周邊元件的製造。區域2之場氧化物 (field oxide，FOX)將被使用爲隔離的用途。 FOX區域2係藉由不爲一上層抗氧化之氮化矽 層與一下層氧化矽層所組成之複合絕緣體圖 案所覆蓋之半導體基板1之區域的熱氧化作用 而被簡單地形成。藉由在氧氣-蒸汽氣氛中執行 的熱氧化製程，而將厚度介於至⑽A 的FOX區域2形成後，該複合絕緣體圖案係被 移除；接著藉由在氧氣-蒸汽氣氛中執行的熱氧 化製程，而將厚度介於大約50至200A的二氧 化砂蘭極絕緣體層3成長。其次’ 一多晶敬層 (請先閲讀背面之注意事項再填寫本頁) -5 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2丨0X297公釐） 416140 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（γ) 4係使用低壓化學氣項沈積（LPCVD )製程而 被沈積至大約500至isooA的厚度。多晶矽層4 可在沈積期間藉著將砷或磷添加於矽烷氣氛 中而於原位置被摻雜（doped);或者多晶矽層4 可被本質地沈積（deP〇sited intrinsically)，並 經由砷或磷離子的離子植入implantation) 而被摻雜。其次，一諸如矽化鎢等金屬矽化物 層5係藉由LPCVD製程而被沈積至介於大約 500至1500A的厚度。最後，一氮化矽層6係 經由LPCVD或電漿輔助化學氣相沈積而被沈 積至大約1〇〇〇至2S00A間的厚度。傳統光學微 影以及非等向性活性離子蝕刻（reactive ion etching，RIE)係被使用以產生爲氮化矽層所 覆蓋之多晶矽化金靥（金雇矽化物-多晶矽）閘 極結構7於周邊區域70中，並產生爲氮化矽所 覆蓋之多晶矽化金靥閘極結構於DRAM 單元區域80中*其中該RIE在氮化矽層6時係 使用CF4作爲蝕刻物質，在金屬矽化物層5與 多晶矽層4係使用Cl2作爲蝕刻物質》在將用 以刻劃爲氮化矽所覆蓋之多晶矽化金靥閘極 結構之光阻罩幕移除後後，這些製程的結果係 被示意地表示於圖1中。 氮化矽絕緣體間隙壁（spaced2係藉由使 用一 LPCVD或一 PECVD製程將一氮化矽層沈 ____ __ 9 本^紙^尺度適用中國國家標準（〔Ν^Γλ4規格（2】0X297公釐) ---------批衣--^-----1τ------線 (#先閲讀背面之注意事項再填寫本頁) 416140 Α7 Α7 Β7 五、發明説明（y ) 經濟部中央標隼局員Η消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 積至大約200至1000A的厚度，接著藉由執行 一使用CHF3爲蝕刻物質的非等向性RIE製 程，而形成於爲氮化矽所覆蓋之多晶係閘極結 構邊緣上。其次，一光阻隔離罩幕（Photoresist blockout mask)係被用以允許源極/汲極區域I3 被形成於半導體基板1中未爲氮化矽所覆蓋之 多晶矽化金屬閘極結構8-11而覆蓋之DRAM 單元區域80中。圖2所示意表示之源極/汲極 區域13係藉由使用砷或磷離子以介於大約3〇 至50KeV的能量被執行之離子植入製程，而被 植入大約1E14至1E16 atoms/cm2的劑量。（先 前微量摻雜的源極/汲極區域係被產生於多晶 矽化金屬閘極結構7-11被定義後，以及絕緣體 間隙壁I2形成之前。未表示於圖示中之微量摻 雜源極/汲極區域係藉由使用砷或磷離子以介 於大約10至4〇KeV的能量被執行之離子植入 製程，而被植入大約1E12至1E14 atoms/ cm2 的劑量）。用以在DRAM單元區域8〇中產生 源極/汲極區域13的光阻隔離罩幕係經由電漿 氧氣灰化（ashing)與仔細的濕式淸除製程而被 移除。具有窗口 I5的另一光阻輪廓I4係於後 序被使用爲罩幕以允許在周邊區域之爲氮 化矽所覆蓋之多晶矽化金羼閘極結構7的氮化 矽層區域6，藉由使兩CHF3g蝕刻物質的非 10 本紙張尺度適用中國國家標準（CNS M4規格ί IM0X297公釐) 416140 A7 B7 經濟部中央標準局—工消費合作社印策Employees' cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China Du Yinzhuang 416140 A7 B7 V. Description of the invention (/) Background of the invention: (1) Field of the invention: The present invention relates to a method for manufacturing dynamic random access memory (dram) ) Method of semiconductor device * Especially a method for generating a contact structure in a peripheral area and simultaneously forming a capacitive node structure of a DRAM memory cell (2) Previous technical description: As the density of a DRAM chip increases to one billion Bit level, so the area of the DRAM cell must be reduced. The reduced DRAM cell area was achieved using design guidelines of approximately 0.15 microns or less. This advanced design criterion places requirements on DRAM cells and special components in the peripheral area of the DRAM chip. For example, in order to achieve the desired performance, the capacitance of a DRAM device must be maintained through the use of a capacitor node having at least a micron degree of power. When attempting to open a contact hole connected to a feature below the DRAM capacitor structure, the thick insulating layer used to protect the rubidium capacitor structure will complicate the process. In addition, the thick insulating layer will also generate a high aspect ratio contact or via hole used for the interconnection between the interconnect structure and the substrate components in the peripheral area of the DRAM wafer. The present invention will explain a brand new process using a dual inlay process, in which the second --- I- 丨-^ ---- install-^ ---- order ------ line (please read the back first Note: Please fill in this page again.) This paper size is applicable to Chinese national standard (CNS> A4 size (210X297).) Staff Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs, Printing Co., Ltd. 416140 A7 B7 V. Description of the invention (»A mosaic process will make dram The 髙 capacitor node in the cell area and the lower interconnect structure in the peripheral area are generated simultaneously. The second damascene process allows the generation of narrow vias filled by gold that are connected to the DRAM capacitor structure and the lower interconnect structure. Completed. Such as Chou et al. 11.8.1 ^ 1.] \ 〇 · 5,731,236 and Jeng et al. US Pat. No. 5,710,073 revealed the capacitor structure, self-aligned contact (SAC) The combination of the structure and the interconnect structure, however, these conventional technologies do not provide a dual-embedded manufacturing process characterized by the simultaneous formation of the dram unit, the capacitor node structure, and the interconnect structure used in the peripheral area of the dram chip of the present invention. Brief introduction of the invention Description: The main object of the present invention is to provide a capacitor node structure and peripheral device interconnect structure that simultaneously generate a 髙 density DRAM cell. A second object of the present invention is to use a dual damascene technology to allow contacts and vias to be created. It is filled in a thick insulating layer with a 髙 aspect ratio structure. Another object of the present invention is to scribe a silicon nitride layer and use the etched silicon nitride layer with a thick silicon oxide layer underneath. As a stop layer in the second inlay process, the second inlay process is used to open and connect 3 paper sizes to the Chinese National Standard (CNS) Λ4 specification (210 X 297 mm) --- ------ t-, ---- ΐτ ------. ^ (锜 Please read the notes on the back before filling out this page) 416140 Α7 Β7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Explanation of the invention (/) A contact hole connected to a peripheral word line structure and a region in a semiconductor substrate. Another object of the present invention is to use a two-layer self-aligned contact (SAC) window to allow a capacitor node structure. And source / drain regions in a semiconductor substrate Contact. A method featuring a dual surface-mount process and the use of a two-layer SAC window, which simultaneously produces a 节点 density DRAM cell capacitor node structure and an interconnect structure in the surrounding area according to the present invention, has been developed. It is a silicon nitride layer The first layer of polysilicon metal (metal silicide-polysilicon) gate structure covered with a silicon nitride spacer located on the edge of the polysilicon gold gate structure is formed in the DRAM cell area, and is a first The polycrystalline silicon silicide gate structure covered by silicon nitride is formed in the peripheral area of the DRAM chip. After the source / drain region is formed in the DRAM cell area not covered by the polycrystalline silicon silicide gate structure, it is exposed. A portion of the window on the top surface of the gold-silicide silicide layer is capped in a nitrided sand layer formed by a polycrystalline gold-silicide silicide gate structure in a peripheral region. The first oxide layer is deposited and scribed to form a first layer of SAC window, the width of the window is greater than the distance between the polycrystalline silicon silicide metal gate structures covered by silicon nitride in the DRAM cell area to expose The source / drain region between the polysilicon silicided metal gate structures covered by silicon nitride is exposed * and the silicon nitride is exposed. 4 The paper size is applicable to the Chinese national standard ίΤϋ) Λ4 specification (210X297 mm) " ~ '--------- f ------ " ------ ^ (Please read the notes on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs 4Consumer Cooperative 416140 A7 _B7_ V. Description of the Invention (P) A part of the top surface of the polycrystalline dysprosium structure covered. This scribe process is also used to open the contact holes in the first silicon oxide layer to expose the first area of the semiconductor substrate in the peripheral area. A conductive plug is sequentially formed in the SAC window to form a SAC structure, and a conductive plug structure is also formed in the contact hole in the peripheral area. The second silicon oxide layer is sunk and scribed to open the bit line contact holes in the second silicon oxide layer, and the SAC structure in the DRAM cell region is exposed, and is used as a post-sequence bit line contact structure. And opening a contact hole in the second silicon oxide layer to expose the conductive plug structure in the peripheral region. A second layer of polycrystalline silicon silicide structure covered by a silicon nitride layer is formed in the DRAM area. The underlying polycrystalline silicon element system is one of the second layer of polycrystalline silicon silicide metal gate structure covered by silicon nitride. The SAC structure in the bit line contact hole is in contact, and another polycrystalline silicon element under the second polycrystalline gold silicide gate structure covered by silicon nitride is in contact with the conductive plug structure in the peripheral region. The silicon nitride spacer is formed on the edge of the second layer of polycrystalline gold silicide gate structure covered by silicon nitride. A third silicon oxide layer and a silicon nitride layer thereon are deposited, and then the silicon nitride layer is scribed to form a silicon nitride hard mask. The window in the silicon nitride hard mask in the dram unit area will expose 5 paper sizes applicable to the Chinese national standard IcNS) A4 specification (2HT / 297 male f) '~ ----: -------- ^- „----.- 1T ------ Φ, (Please read the notes on the back before filling out this page) 416140 Α7 Β7 Consumption cooperation between employees of the Central Bureau of Standards of the Ministry of Economy Du Yinzhuang 5. Description of the invention (y) In the area directly above the space between the second layer of polycrystalline gold silicide gate structure covered by silicon nitride and in the area directly above the SAC structure between the first layer of polycrystalline gold silicide structure covered by silicon nitride The top surface of the third silicon oxide layer * will be used as a capacitor node contact. The other windows in the silicon nitride hard mask are located in the peripheral area and are covered with silicon nitride. The siliconized layer is directly above the window and directly above the second pass area of the semiconductor substrate in the peripheral area. A fourth silicon oxide layer is deposited and scored to generate a second SAC window on the fourth layer. In the silicon oxide layer and the third silicon oxide layer exposed by the window of the silicon nitride hard mask, and The second layer of SAC window exposing the SAC structure is used as the capacitor node contact in the DRAM cell area. The fourth silicon oxide layer and the third silicon oxide layer exposed by the window of the silicon nitride hard mask, the second The scoring of the silicon oxide layer and the first silicon oxide layer will expose the polycrystalline gold silicide gate structure and the second region of the semiconductor substrate located in the peripheral region to expose a tungsten layer that is deposited and subjected to a chemical mechanical honing process (CMP). * In order to remove tungsten from the top surface of the fourth silicon oxide layer, a mosaic capacitor node structure is generated in the fourth silicon oxide window and the second SAC window, which is the same as the capacitor node located in the first SAC window. The contacting SAC structure is in contact with and is located above it. The CMP process is also in the surrounding area. The paper size is applicable to the Chinese national standard (CNsTXl specification (2ί〇 × 297 mm) ---- μ, ----- installation—; ---- Order ------ line (please read the precautions on the back before filling this page) 416140 A7 B7 M Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Mosaic interconnect structure to contact polysilicon gate The gold structure silicide layer of the polar structure contacts the second area of the semiconductor substrate. The area exposed by the fourth silicon oxide layer is selectively removed and terminated on the lower silicon nitride hard mask to produce Capacitor node structure and lower interconnect structure extending upward from silicon nitride hard mask. Capacitor dielectric layer and capacitor unit electrode plate structure are formed on capacitor node structure to produce DRAM capacitor structure. A fifth oxide layer system Is deposited, planarized by the CMP process, and scribed to open the top surface of the capacitor cell electrode plate structure connected to the DRAM cell, the surface-embedded interconnect structure, and the second layer of polysilicidation covered by silicon nitride The interstitial holes of the gold / silicon / silicide layer will contact the conductive plug structure in the peripheral area. Secondly, a tungsten layer is deposited and then subjected to a CMP process to generate a damascene plug structure, which contacts the capacitor cell electrode plate in the DRAM cell, the lower interconnect structure, and the surrounding area which is covered by silicon nitride. The second layer of polycrystalline silicon silicide gate electrode. The upper interconnect structure is formed in a subsequent sequence so as to be positioned above and in contact with the upper town plug structure. Brief description of the figure: The purpose and other advantages of the present invention are described in the preferred embodiments with reference to the accompanying drawings, among which: 7 paper sizes are in accordance with the Chinese National Standard (CNS) A4 specification (210X2W mm 7-- ---------- ¾ .--.---- 1T ------ 1 (Please read the notes on the back before filling out this page) 416140 A7 B7 Staff Consumption of Central Standards Bureau, Ministry of Economic Affairs Cooperative Du Printing 5. Description of the Invention (7) Figures 1-20 are schematic cross-section diagrams showing the main manufacturing steps of the interconnection structure used to simultaneously generate the capacitor nodes of the DRAM cell and the components located in the peripheral area of the DRAM chip. Detailed description of the invention: The present invention is a method for simultaneously forming a capacitor node structure of a DRAM army and an interconnect structure located in a peripheral area of a DRAM chip, which is characterized by the use of a dual table-embedding process. A semiconductor substrate 1 composed of single crystal silicon having a crystal orientation of < 100 > is used and is schematically shown in FIG. The region 80 of the semiconductor substrate 1 will be used as an example of a high-density DRAM cell, and the region will be used to illustrate the manufacture of peripheral components of a DRAM wafer. Field oxide (FOX) in area 2 will be used for isolation. The FOX region 2 is simply formed by thermal oxidation of a region of the semiconductor substrate 1 covered by a compound insulator pattern composed of an upper oxidation-resistant silicon nitride layer and a lower silicon oxide layer. The composite insulator pattern is removed by forming a FOX region 2 with a thickness of ⑽A by a thermal oxidation process performed in an oxygen-steam atmosphere; then, by a thermal oxidation performed in an oxygen-steam atmosphere In the manufacturing process, a Sarnia dioxide insulator layer 3 having a thickness of about 50 to 200 A is grown. Secondly, a polycrystalline layer (please read the precautions on the back before filling this page) -5 This paper size applies to Chinese National Standard (CNS) Λ4 specification (2 丨 0X297 mm) 416140 A7 B7 Central Standards Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative. 5. Description of the Invention (γ) 4 is deposited to a thickness of about 500 to isooA using a low pressure chemical gas deposition (LPCVD) process. The polycrystalline silicon layer 4 may be doped in situ by adding arsenic or phosphorus to the silane atmosphere during the deposition; or the polycrystalline silicon layer 4 may be deposited intrinsically and via arsenic or phosphorus The ions are doped by ion implantation. Second, a metal silicide layer 5 such as tungsten silicide is deposited to a thickness of about 500 to 1500 A by a LPCVD process. Finally, a silicon nitride layer 6 is deposited to a thickness of about 1000 to 2S00A via LPCVD or plasma-assisted chemical vapor deposition. Traditional optical lithography and anisotropic reactive ion etching (RIE) are used to produce polycrystalline Au silicide (gold silicide-polycrystalline silicon) gate structures covered by a silicon nitride layer. 7 In the region 70, a polycrystalline gold silicide gate structure covered by silicon nitride is generated in the DRAM cell region 80. The RIE uses CF4 as an etching substance when the silicon nitride layer 6 is used, and the metal silicide layer 5 The polycrystalline silicon layer 4 uses Cl2 as an etching substance. "After removing the photoresist mask used to characterize the polycrystalline gold silicide gate structure covered by silicon nitride, the results of these processes are schematically shown. In Figure 1. Silicon nitride insulator spacer (spaced2 is used to sink a silicon nitride layer by using an LPCVD or a PECVD process. __ __ 9 This paper ^ standard applies to Chinese national standards ([N ^ Γλ4 specification (2) 0X297 mm ) --------- batch clothes-^ ----- 1τ ------ line (#Read the precautions on the back before filling this page) 416140 Α7 Α7 Β7 V. Description of the invention ( y) Printed by a member of the Central Bureau of Standards of the Ministry of Economic Affairs and a Consumer Cooperative (please read the notes on the back before filling this page) to a thickness of about 200 to 1000A, and then implement an anisotropy using CHF3 as an etching substance RIE process, and is formed on the edge of the polycrystalline gate structure covered by silicon nitride. Second, a photoresist blockout mask is used to allow the source / drain region I3 to be formed on The semiconductor substrate 1 is not covered by the polysilicon metal gate structure 8-11 covered by silicon nitride in the DRAM cell region 80. The source / drain region 13 shown schematically in FIG. 2 is made by using arsenic or phosphorus An ion implantation process in which ions are performed at an energy between about 30 and 50 KeV, and are implanted at about 1E14 to The dose of 1E16 atoms / cm2. (The previous micro-doped source / drain regions were generated after the polysilicon gate structure 7-11 was defined, and before the insulator spacer I2 was formed. Not shown in the figure The micro-doped source / drain regions are implanted at a dose of approximately 1E12 to 1E14 atoms / cm2 by an ion implantation process performed using arsenic or phosphorus ions at an energy between approximately 10 and 40 KeV. ). The photoresist isolation mask used to generate the source / drain regions 13 in the DRAM cell region 80 is removed via plasma oxygen ashing and a careful wet depletion process. It has a window Another photoresistance profile I4 of I5 is used in the subsequent sequence as a mask to allow the silicon nitride layer region 6 of the polycrystalline Au silicide gate structure 7 to be covered by silicon nitride in the peripheral region. Non-10 CHF3g etching material This paper size is applicable to Chinese national standard (CNS M4 specification IM0X297 mm) 416140 A7 B7 Printing policy of the Central Standards Bureau of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives
五、發明説明) 等向性RIE製程而被移除，以暴露出爲氮化矽 所覆蓋之多晶矽化金屬閘極結構7中的金靥矽 化物層5的頂端表面的一部份。此係示意地被 表示於圖3中。光阻輪廓I4係使用電漿氧氣灰 化與仔細的濕式淸除而被移除。 其次，示意表示於圖4中的一層氧化矽層 16係經由LPCVD或PECVD製程而被沈稹至大 約5000至ΙΟΟΟΟΑ的厚度·»光阻輪廓I7係於後 序被用以在DRAM單元匾域80中產生第一層 的自行校準接觸（SAC )窗口 18 »示意地表 示於圖5中並藉由使甩（：111'3爲蝕刻物質之非 等向性RIE製程而產生的SAC窗口 18具有較 爲氮化矽所覆蓋之多晶矽化金靥閘極結構8-11之間距更大的寬度。因此，該使用CHF3作 爲蝕刻物質的選擇性RIE製程並不會在SAC 窗口製程中侵蝕氮化矽層6或氮化矽間隙壁 12，因此，其不僅暴露出位於爲氮化矽所覆蓋 之多晶矽化金靥閘極結構間的源極/汲極區域 13，且亦暴露出作爲多晶矽化金龎閘極結構之 覆蓋層（capping layer)之氮化较層6頂端表面 的一部份。使用較多晶矽化金屬閘極結構間距 爲寬之寬度設計的SAC窗口將允許這些間距 被維持於較最小設計準則（design rule)更窄的 尺寸*因爲後序的SAC結構將自行校準於SAC ----^------^--^----1T------^ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 416140 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（) 窗a is中並完全座落於其中。相同的非等向性 RIE製程亦被使用於在周邊區域70之氧化矽 層16中產生窗口 I9。在藉由電漿氧氣灰化與 仔細的濕式淸除而將光阻輪廓17移除後， SAC結構20係被形成於DRAM單元區域80中 的SAC窗口 1S中，而導電插塞結構21係被形 成於周邊區域7〇的窗口 I9中。SAC結構2〇 與接觸插塞21的形成係經由多晶矽層的沈積 且在沈稹過程中將砷或磷添加至矽烷氣氛 中，接著以<：12作爲蝕刻物質之選擇性RIE製 程將多晶矽由氧化矽層16頂端表面移除，而形 成SAC結構2〇以及導電插塞結構21。一下面 爲氮化鈦層的鎢層將可被用以取代多晶矽作 爲SAC與接觸插塞結構。此外，一化學機械硏 磨（CMP )製程可被用以取代選擇性RIE製 程，以將所不欲的多晶矽或鎢由氧化矽層16 的頂端表面移除》此係示意地表示於圖6中。 一層氧化矽層60係經由LPCVD或PECVD 製程被沈積至大約至6000A間的厚度，接 著以CMP製程產生一平順頂端表面形貌的氧 化矽層60。光阻輪廓23係於後序被使用爲單 幕，而允許使用CHF3作爲蝕刻物質的非等向 性RIE製程產生暴露出SAC結構20頂端表面 的窗口 25，以作爲DRAM單元區域80中之後 -____±2__ 本紙張尺度適用中國國家標隼（CNS〉/\4現格（210X297公釐） ---------裝—,----訂------旅 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印製 416140 A7 B7 五、發明説明（/ >) 序位元線結構的接觸焊墊（contact Pad);此外 亦在周邊區域7〇產生暴鳝出導電插塞結構21 頂端表面的窗口 24。此係示意地被舉例於圖7 中》經由電漿氧氣灰化與仔細的濕式淸除而將 光阻輪廓23移除後，一多晶砍層26、一金靥 矽化物層27以及一氮化矽層28係被沈積。多 晶矽層26係經由LPCVD製程而被沈積至大約 500至1500A的厚度，其係完全地塡充窗口 25 並完全地塡充窗口 24。多晶矽層26可在沈積 期間藉著將砷或磷添加於矽烷氣氛中而於原 位置被摻雜；或者多晶矽層26可被本質地沈 積，並經由砷或磷離子的離子植入而被摻雜。 其次，可爲一矽化鎢層或一矽化鈦層之金羼矽 化物層27係藉由LPCVD製程而被沈積至介於 大約500至1S00A的厚度；而一氮化矽層28係 經由LPCVD或PECVD製程而被沈積至大約 1000至2500A間的厚度。這些製程的結果係被 示意地表示於圖8中。光阻輪廓29係被使用爲 罩幕以刻割一連串的諸層，而產生一連接至 SAC結構20之爲氮化矽所覆羞的多晶矽化金 屬結構3lc，藉著爲多晶矽所塡充之窗口 25， 其可被使用爲後序位元線結構的一部份》藉由 在氮化矽層28時使用CF4作爲蝕刻物質，在金 屬矽化物層27與多晶矽層26使用Cl2作爲蝕 ________1_3_ 本紙張尺度適用中國国家榡率（CNS ) A4規格（21〇>< 297公釐） I I I —1 I I I I 訂 ~~ n I 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印裝 416140 A7 _B7__ 五、發明説明（^) 刻物質之非等向性RIE製程而完成之刻劃亦將 產生一經由多晶矽塡充窗口 24而連接至導電 插塞21之爲氮化矽所覆蓋的多晶矽化金颶結 構31a »此外，爲氮化矽所覆蓋之多晶矽化金 屬結構31b與Md係被形成於氧化矽層60上 方，且其係直接位於爲氮化矽所覆蓋之多晶矽 化金屬閘極結構8以及爲氮化矽所覆蓋之多晶 矽化金屬閘極結構11上方。這些製程的結果係 被示意地表示於圖9中。 其次*氮化矽間陳壁30係藉由使用一 LPCVD或一 PECVD製程之氮化矽層沈積至大 約200至ιοοοΑ的厚度，接著藉由執行一使用 CHF3爲蝕刻物質的非等向性RIE製程，而被 形成於爲氮化矽所覆蓋之多晶係閘極結構邊 緣上。這些製程的結果係示意地表示於圃10 中。一層氧化矽層32係經由LPCVD或PECVD 被沈積至大約4〇⑽至ιοοοοΑ間的厚度。在以 CMP製程產生一平順頂端表面形貌的氧化矽 層32後，圖11中所示意表示的一氮化矽層33 係使用LPCVD或PECVD製程而被沈積至大約 100至ΙΟΟΟΑ間的厚度。光阻輪廓34係於後序 被形成且被使用爲罩幕，而允許使用CHF3作 爲蝕刻物質的非等向性RIE製程形成一硬式罩 幕圖案於氮化矽層33中，如圖12中所示意表 ________1_4_ i~ I— n n I i i I n n ΙΊ u ^ I— I— J~ I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2】0X297公釐） 416140 A7 B7 經濟部中央揉準局員工消費合作杜印製 五、發明説明（If) 示。經由電漿氧氣灰化與仔細的濕式淸除而將 光阻輪麻34移除後，一氧化矽層35係使用 LPCVD或PECVD製程而被沈積至大約4000 至15000A的厚度》另外一個光阻圖案％係被 形成爲擁有對齊於下面氮化矽層33之硬式罩 幕圖案中之窗口的窗口 37a :並擁有位於在下 面氮化矽層33之硬式罩幕圖案中之窗口上的 窗口 38a，其中該氮化矽中的硬式罩幕圃案之 窗口係對齊於爲氮化矽所覆蓋之多晶矽化金 屬閘極結構7之氮化矽層6中的窗口》此係示 意地表示於圖13中》 一使用CHF3作爲蝕刻物質且使用光阻輪 廓Μ作爲罩幕之非等向性RIE製程係被使用 以在氧化矽靥35以及在爲氮化矽層33中之硬 式罩幕圖案所暴露之氧化矽層32中形成窗口 37b。窗口 37b係較爲氮化矽所覆蓋之多晶矽 化金雇結構31b、31<：與31<1間的間距寬度爲 大；而除了暴β出爲氮化矽所覆蓋之多晶矽化 金靥結構外，並暴露出覆蓋氮化矽層以及爲氮 化矽所覆蓋之多晶矽化金靥結構的氮化矽間 隙壁，因此可作爲第二層SAC窗口的功能。一 使用CHFjt爲蝕刻物質且使用光阻輪廓36以 及氮化矽層33中的硬式罩幕圖案作爲罩幕之 非等向性RIE製程，經移除氧化矽層35、氧 _ 15 (請先閲讀背面之注意事項再填寫本頁) J*s 丁 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） 416140 A7 B7 經濟部中央標攀局員工消費合作社印製 五、發明説明（//) 化矽層32、氧化矽層60與氧化矽層16後，將 形成窗口 38b »窗口 3Sb將暴露出爲氮化矽所 覆蓋之多晶矽化金屬閘極結構7中的金屬矽化 物層，並暴»出半導體基板1的一部份。此係 被示意地表示於圖14中。 經由電漿氧氣灰化與仔細的濕式淸除將光 阻輪廓36移除後，一鎢層係使用RF濺鍍或 LPCVD製程而被沈積至大約4000至12000A間 的厚度，以完全塡充窗口 37b與3Sb。其次， 一 CMP製程係被用以自氧化矽層S5的頂端表 面移除鎢，以在窗口 37b中產生包含有自行校 準儲存節點結構39之一連串的第一錶嵌式結 構。此外，銀嵌式下互連結構40係被形成於窗 口 38b中》此係示意地舉例於圖IS中。使用經 稀釋或經緩衝之氫氟酸溶液的濕式蝕刻製程 係被用以選擇性地移除氧化矽35，以產生由氮 化矽層33向上延伸之儲存節點結構39，而呈 現出額外的表面積，所以增加的電容量將可被 利用。此外，圖16所示意表示之下互連結構亦 由氮化矽層33向上延伸》 圖I7示意地舉例DRAM單元區域8〇中之 DRAM電容結構43的完成•首先，一若非由 Ta205層、一 ON (氧化氮）層' -BST (鋇 鋸鈦酸鹽）層則爲一 PZT (鉛銷鈦酸鹽）層所 1 6 (請先閎讀背面之注意事項再填寫本頁) -a5. Description of the invention) The isotropic RIE process is removed to expose a part of the top surface of the gold-silicide layer 5 in the polycrystalline silicon silicide metal gate structure 7 covered by silicon nitride. This system is shown schematically in FIG. 3. The photoresist profile I4 was removed using plasma oxygen ashing and careful wet ablation. Secondly, a silicon oxide layer 16 shown schematically in FIG. 4 is sunk to a thickness of about 5000 to 100 ΑΑ through a LPCVD or PECVD process. »The photoresist profile I7 is used in the subsequent sequence to form the DRAM cell plaque domain 80. The first layer of self-calibrating contact (SAC) window 18 generated in the first layer is schematically shown in FIG. 5 and the SAC window 18 produced by making the (111′3 is the anisotropic RIE process of the etching material has a The polysilicon gold gate structure 8-11 covered by silicon nitride has a larger gap. Therefore, the selective RIE process using CHF3 as an etching substance does not erode the silicon nitride layer during the SAC window process. 6 or silicon nitride spacers 12, so it not only exposes the source / drain region 13 between the polycrystalline silicon silicide gate structures covered by silicon nitride, but also exposes it as a polycrystalline silicon silicide gate. The capping layer of the electrode structure is nitrided a portion of the top surface of layer 6. A SAC window designed using a wide range of crystalline silicide metal gate structures with a wide width will allow these distances to be maintained at a minimum design criterion (Design rule) Narrow size * Because the subsequent SAC structure will self-calibrate to SAC ---- ^ ------ ^-^ ---- 1T ------ ^ (Please read the precautions on the back first (Fill in this page again) This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) 416140 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () The window a is completely located in Among them, the same anisotropic RIE process is also used to generate the window I9 in the silicon oxide layer 16 in the peripheral area 70. The photoresist profile 17 is shifted by plasma oxygen ashing and careful wet removal. After the removal, the SAC structure 20 is formed in the SAC window 1S in the DRAM cell region 80, and the conductive plug structure 21 is formed in the window I9 in the peripheral region 70. The SAC structure 20 and the contact plug 21 The formation is through the deposition of a polycrystalline silicon layer and arsenic or phosphorus is added to the silane atmosphere during the immersion process, and then the polycrystalline silicon is removed from the top surface of the silicon oxide layer 16 by a selective RIE process using <: 12 as an etching substance, and A SAC structure 20 and a conductive plug structure 21 are formed. A tungsten layer with a titanium nitride layer underneath It is used to replace polycrystalline silicon as a SAC and contact plug structure. In addition, a chemical mechanical honing (CMP) process can be used to replace the selective RIE process to remove unwanted polycrystalline silicon or tungsten from the top of the silicon oxide layer 16 The "surface removal" is schematically shown in Figure 6. A silicon oxide layer 60 is deposited by a LPCVD or PECVD process to a thickness of about 6000 A, and then a silicon oxide layer with a smooth top surface morphology is produced by a CMP process. 60. The photoresist profile 23 is used as a single screen in the subsequent sequence, and the anisotropic RIE process that allows the use of CHF3 as an etching substance produces a window 25 that exposes the top surface of the SAC structure 20 as the DRAM cell area 80 after -____ ± 2__ This paper size is applicable to Chinese national standard (CNS> / \ 4 is now (210X297 mm) --------- installation —, ---- order ------ Travel (please first (Please read the notes on the back and fill in this page.) Consumer Co-operation of the Central Bureau of Standards, Ministry of Economic Affairs, printed 416140 A7 B7 V. Description of the invention (/ >) Contact pads of sequential bit line structure; The peripheral area 70 produces a window 24 that bursts out the top surface of the conductive plug structure 21. This is schematically illustrated in FIG. 7 "The photoresist contour 23 is moved by plasma oxygen ashing and careful wet removal. After the removal, a polycrystalline silicon layer 26, a gold halide silicide layer 27, and a silicon nitride layer 28 are deposited. The polycrystalline silicon layer 26 is deposited to a thickness of about 500 to 1500 A through the LPCVD process, which is completely The window 25 is filled and the window 24 is completely filled. The polycrystalline silicon layer 26 may be deposited by arsenic or Added in a silane atmosphere and doped in situ; or the polycrystalline silicon layer 26 may be deposited in nature and doped by ion implantation of arsenic or phosphorus ions. Secondly, it may be a tungsten silicide layer or a titanium silicide. The gold silicide layer 27 is deposited by a LPCVD process to a thickness of about 500 to 1S00A; and a silicon nitride layer 28 is deposited by a LPCVD or PECVD process to a thickness of about 1000 to 2500A The results of these processes are shown schematically in Figure 8. The photoresist profile 29 is used as a mask to cut a series of layers, resulting in a silicon nitride overlaid connection to the SAC structure 20 The polycrystalline silicon silicide metal structure 3lc can be used as part of the post-sequence bit line structure through the window 25 filled by polycrystalline silicon. By using CF4 as an etching substance in the silicon nitride layer 28, the metal The silicide layer 27 and the polycrystalline silicon layer 26 use Cl2 as the etch. ________1_3_ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇 > < 297mm) III —1 IIII Order ~~ n I line (please Read the notes on the back before filling out this Page) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 416140 A7 _B7__ V. Description of the Invention (^) The engraving completed by the anisotropic RIE process of engraving the material will also generate a polycrystalline silicon filling window 24 connected to the conductive The polycrystalline silicon silicide structure 31a covered by the silicon nitride plug 31 is made of polysilicon. In addition, the polycrystalline silicon silicide metal structure 31b covered by the silicon nitride and the Md system are formed on the silicon oxide layer 60, and the system is directly located as Above the polycrystalline silicon silicide gate structure 8 covered by silicon nitride and the polycrystalline silicon silicide gate structure 11 covered by silicon nitride. The results of these processes are shown schematically in FIG. Secondly, the silicon nitride interlayer 30 is deposited by a silicon nitride layer using a LPCVD or a PECVD process to a thickness of about 200 to ιοοοΑ, and then an anisotropic RIE process using CHF3 as an etching substance is performed. And is formed on the edge of the polycrystalline gate structure covered by silicon nitride. The results of these processes are shown schematically in the nursery 10. A silicon oxide layer 32 is deposited by LPCVD or PECVD to a thickness of about 40 Å to ιοοοοΑ. After a silicon oxide layer 32 having a smooth top surface topography is produced by the CMP process, a silicon nitride layer 33 illustrated schematically in FIG. 11 is deposited to a thickness of about 100 to 100 Å using a LPCVD or PECVD process. The photoresist profile 34 is formed in the subsequent sequence and used as a mask, and an anisotropic RIE process using CHF3 as an etching substance is used to form a hard mask pattern in the silicon nitride layer 33, as shown in FIG. 12 Schematic table ________1_4_ i ~ I— nn I ii I nn ΙΊ u ^ I— I— J ~ I (Please read the precautions on the back before filling out this page) The paper size applies to the Chinese National Standard (CNS) Λ4 specification (2 ] 0X297 mm) 416140 A7 B7 Printed by the Central Government Bureau of the Ministry of Economic Affairs on the consumer cooperation of employees. After removing the photoresist rime 34 by plasma oxygen ashing and careful wet removal, the silicon oxide layer 35 is deposited to a thickness of about 4000 to 15000A using LPCVD or PECVD process. Another photoresist The pattern% is formed as a window 37a having a window aligned in the hard mask pattern of the silicon nitride layer 33 below: and a window 38a on the window in the hard mask pattern of the silicon nitride layer 33 below, The window of the hard mask curtain in the silicon nitride is aligned with the window in the silicon nitride layer 6 of the polycrystalline silicided metal gate structure 7 covered by the silicon nitride. This is schematically shown in FIG. 13 》 An anisotropic RIE process using CHF3 as the etching material and photoresist profile M as the mask is used to expose the oxide on the silicon oxide layer 35 and the hard mask pattern in the silicon nitride layer 33 A window 37b is formed in the silicon layer 32. Window 37b is a polycrystalline silicon silicide structure 31b, 31 < and 31 < 1 which is covered by silicon nitride. The width of the gap is large; The silicon nitride spacers covering the silicon nitride layer and the polycrystalline Au silicide structure covered by the silicon nitride are exposed, so they can function as the second SAC window. An anisotropic RIE process using CHFjt as the etching material and using the hard mask pattern in the photoresist contour 36 and the silicon nitride layer 33 as the mask, after removing the silicon oxide layer 35, oxygen _ 15 (please read first Note on the back, please fill in this page again) J * s The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 416140 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs //) After siliconizing layer 32, silicon oxide layer 60 and silicon oxide layer 16, window 38b will be formed »window 3Sb will expose the metal silicide layer in the polycrystalline silicon silicide metal gate structure 7 covered by silicon nitride, A part of the semiconductor substrate 1 is exposed. This system is schematically shown in FIG. 14. After removing the photoresist contour 36 by plasma oxygen ashing and careful wet ablation, a tungsten layer is deposited to a thickness of about 4000 to 12000A using RF sputtering or LPCVD process to completely fill the window 37b and 3Sb. Second, a CMP process is used to remove tungsten from the top surface of the silicon oxide layer S5 to generate a series of first table embedded structures including one of the self-calibrated storage node structures 39 in the window 37b. In addition, the silver embedded lower interconnect structure 40 is formed in the window 38b. This is schematically illustrated in FIG. A wet etch process using a diluted or buffered hydrofluoric acid solution is used to selectively remove silicon oxide 35 to produce a storage node structure 39 extending upward from the silicon nitride layer 33, presenting additional Surface area, so increased capacitance will be available. In addition, Figure 16 shows that the underlying interconnect structure also extends upwards from the silicon nitride layer 33. Figure I7 schematically illustrates the completion of the DRAM capacitor structure 43 in the DRAM cell area 80. First, if not by the Ta205 layer, a ON (nitrogen oxide) layer '-BST (barium saw titanate) layer is a PZT (lead pin titanate) layer 16 (Please read the precautions on the back before filling this page) -a
T 本纸張尺度適用中國國家榇準（CNS )八4規格（2丨OX2Q7公釐) 416140 A7 B7 經濟部中央標準局員工消費合作社印裝T This paper size is applicable to China National Standards (CNS) 8-4 specifications (2 丨 OX2Q7 mm) 416140 A7 B7 Printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs
五、發明説明（fp 組成的電容介電層41係使用LPCVD製程而被 沈積大約30至80人間的厚度於氧化矽上。其 次’一多晶矽層42係使用LPCVD製程而被沈 積至大約5〇〇至2〇0〇A間的厚度，並於沈積期 間使甩砷或磷在原位置摻雜或者本質地沈積 後再以離子植入製程摻雜。如果想要的話，鎢 層可被用以取代多晶矽層42。光學微影以及 RIE製程係被使用以產生DRAM電容結構43 之單元電極板結構，其中在RIE蝕刻製程中係 使用Cl2作爲多晶矽層42的蝕刻物質，並使用 CHF3作爲電容介電層41的蝕刻物質，如圖17 所示意表示。被使用爲單元電極板刻劃之蝕刻 罩幕的光阻輪廓係使用電漿氧氣灰化以及仔 細的濕式淸除而被移除。 其次，一氧化矽層44係經由LPCVD或 PECVD製程而被沈積至大約4000至12000入間 的厚度。一 CMP製程係再次被使用以平坦化 氧化矽層44的表面形貌。画18中所示意表示 的光阻輪廓45係被形成並被使用爲允許非等 向性RIE製程的罩幕，以產生連接至DRAM區 域80與周邊區域70中之特殊元件所欲的窗 口。使用CHF3作爲氧化矽層44之蝕刻物質的 非等向性RIE製程將產生暴露出下互連結構 40頂端表面的窗口 46，並產生暴露出DRAM (請先閲讀背面之注意事項再填离本頁) -裝· 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐〉 416140 經濟部中央標準局員工消費合作社印裝 五、發明説明（門） 電容結構43頂端表面的窗口 48。光阻輪廓45 亦被使用爲罩幕以產生窗口 47於氧化矽層 44、氮化矽層33、氧化矽層32以及爲氮化矽 所覆蓋之多晶矽化金靥結構31a的氮化矽層 中，以暴露出爲氮化矽所覆蓋之多晶矽化金屬 結構31a的金屬矽化物層。此係使用CHF3作 爲氧化矽層的蝕刻物質以及使用CHF3作爲氮 化矽層的蝕刻物質而完成。在經由電漿氧氣灰 化以及仔細的濕式淸除以將光阻輪廓45移除 後* 一第二鏤嵌製程係被使用以產生鎢插塞於 窗口 46,47與48中，如圖19所示意表示。此 項工作的完成係經由使用LPCVD或RF濺鍍製 程將鎢沈積4〇〇〇至ΐοοοοΑ間的厚度，接著經 由CMP或使用Cl2爲蝕刻物質之選擇性非等向 性RIE製程，以將所不欲的鎢由氧化矽層44 的頂端表面移除，而產生：連接至下互連結構 40之鎢插塞49於窗口 46中；連接至DRAM電 容結構43之鎢插塞49於窗口 48中：連接至爲 氮化矽所覆蓋之多晶矽化金靥結構3U之鎢插 塞49於窗口 47中。 最後，圖20中所示意表示之上互連結構的 產生係經由鋁基金屬層的沈積，接著施以包含 傳統光學微影以及使用Cl2作爲蝕刻物質之非 等向性RIE製程的刻劃製程。由包含大約1至 (請先閎讀背面之注意事項再填寫本頁) -裝- -va 線 本紙張尺度適用中國國家標準（CNS ) Λ4規格u m X 297公釐） 416140 A7 五、發明説明（（^ ) 3%重量百分比銅的鋁所組成的鋁基金靥層係 經由RF涵鍍製程而獲得大約3000至ιοοοοΑ 間的厚度。該刻割製程將產生下列物質的形 成：經由鎢插塞49連接至下互連結構4〇的上 互連結構54 ;經由鎢插塞49、爲氮化矽所覆 蓋之多晶矽化金靥結構31a與導電插塞結構21 連接至半導體基板區域1的上互連結構51;以 及被用以和位元線結構連通之上互連結構S3 (未表示於圖中）。被使用爲刻劃鋁基層之罩 幕的光阻輪廓係使用電漿氧氣灰化以及仔細 的濕式淸除而被移除。 裝i 訂 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裳 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）V. Description of the Invention (The capacitive dielectric layer 41 composed of fp is deposited on the silicon oxide using a LPCVD process to a thickness of about 30 to 80 people. Secondly, a polycrystalline silicon layer 42 is deposited to about 500 using the LPCVD process. Thickness to 2000A, and doped with arsenic or phosphorus in situ during deposition or essentially doped with an ion implantation process. If desired, a tungsten layer can be used instead of polycrystalline silicon Layer 42. Optical lithography and RIE processes are used to produce the unit electrode plate structure of the DRAM capacitor structure 43. In the RIE etching process, Cl2 is used as the etching material of the polycrystalline silicon layer 42 and CHF3 is used as the capacitor dielectric layer 41. The etching material is shown schematically in Fig. 17. The photoresist profile used as the etching mask scribed by the unit electrode plate is removed using plasma oxygen ashing and careful wet erasing. Second, the oxidation The silicon layer 44 is deposited by a LPCVD or PECVD process to a thickness of about 4000 to 12,000 Å. A CMP process is used again to planarize the surface topography of the silicon oxide layer 44. The schematic shown in Figure 18 The photoresist profile 45 is formed and used as a mask to allow an anisotropic RIE process to create a window that is connected to the special elements in the DRAM area 80 and the peripheral area 70. CHF3 is used as the silicon oxide layer 44 The anisotropic RIE process of the etched material will generate a window 46 exposing the top surface of the lower interconnect structure 40 and exposing DRAM (please read the precautions on the back before filling out this page)-bound and bound paper The dimensions are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm> 416140. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (door) The window 48 on the top surface of the capacitor structure 43. The photoresistance profile 45 is also used as The mask is used to create a window 47 in the silicon oxide layer 44, the silicon nitride layer 33, the silicon oxide layer 32, and the silicon nitride layer of the polycrystalline silicon silicide structure 31a covered by the silicon nitride to be exposed as silicon nitride. The metal silicide layer of the covered polycrystalline silicided metal structure 31a. This is done using CHF3 as the etching material of the silicon oxide layer and using CHF3 as the etching material of the silicon nitride layer. After plasma oxygen After ashing and careful wet slicing divided by removing the photoresist profile 45 * A second stenciling process is used to produce tungsten plugs in windows 46, 47 and 48, as shown schematically in Figure 19. This This work is completed by depositing tungsten to a thickness of 4,000 to ΐοοοοΑ using LPCVD or RF sputtering, and then by CMP or a selective anisotropic RIE process using Cl2 as an etching substance, in order to The tungsten is removed from the top surface of the silicon oxide layer 44 to produce: a tungsten plug 49 connected to the lower interconnect structure 40 in the window 46; a tungsten plug 49 connected to the DRAM capacitor structure 43 in the window 48: connection In the window 47, a tungsten plug 49 with a polycrystalline Au silicide structure 3U covered with silicon nitride is placed in the window 47. Finally, FIG. 20 schematically illustrates that the above-mentioned interconnection structure is produced by depositing an aluminum-based metal layer, followed by a scribe process including a conventional optical lithography and an anisotropic RIE process using Cl2 as an etching substance. Contains about 1 to (please read the precautions on the back before filling out this page) -installation--va wire paper size applicable to Chinese National Standard (CNS) Λ4 size um X 297 mm) 416140 A7 V. Description of the invention ( (^) The aluminum foundation layer composed of 3% by weight copper and aluminum is obtained by an RF culmination process to a thickness of about 3000 to ιοοοοΑ. This engraving process will result in the formation of the following materials: connected through a tungsten plug 49 Upper interconnect structure 54 to lower interconnect structure 40; upper interconnect structure connected to semiconductor substrate region 1 via tungsten plug 49, polycrystalline silicon silicide structure 31a covered with silicon nitride and conductive plug structure 21 51; and the interconnect structure S3 (not shown in the figure) which is used to communicate with the bit line structure. The photoresist profile used to mark the aluminum substrate mask is plasma ashing and careful Wet wiped and removed. Binding line (please read the notes on the back before filling this page) Printed on the paper of the China National Standards (CNS) A4 (210X297) Mm)