1433:2 1 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 1. 發明領域 本發明係有關半導體裝置之製程’特別是關於形成積體 電路之通孔(via)或接觸窗（contact opening)的方法。 2. 發明背景 積體電路使用絕緣層來隔離金屬層或電極，而電路元件 與金屬層之間的導電接觸（conductive contact)以及不同金 屬層之間的互連（interconnect)，係於絕緣層挖設通孔埋入 插才王(plug)來達成’此一技術稱為通孔接觸(via contact)。 積體電路的集積密度與通孔有關》當電路元件尺寸縮減 (scale down)時’通孔的尺寸亦須隨著縮減，因而造成後續 形成插栓時金屬沈積之步階覆:蓋(step coverage )不佳’在通孔内沈積金屬時會形成空隙，導致通孔接觸之 電性惡化。尤其在線寬（line width)達到次微米以下後，傳 統的通孔接觸製程已不能適用。 為改善上述缺失，習知技藝例如中華民國專利公告第 304282號及美國專利第5, 629, 237號，係利用等向性蝕刻 (i sotrop i c etch)例如濕钱刻（wet etch)先在絕緣層上形成 碗狀的輪廓(profile) ’再第二次蝕刻穿透絕緣層形成較小的 接觸孔(contact hole)。這類方法雖然能夠改善金屬之步階 覆蓋，但製程卻較為複雜或較為耗時，例如，使用一次濕蝕 刻及一次乾蝕刻，或是經過兩道不同的蝕刻配方(recipe)， 或是使用不同的|虫刻機台（etch machine)。因此，有必要謀 求較佳的方法進一步解決習知技藝的缺失。 3_發明目的與概述 3 本紙張尺度適用中國國家標準（CNS ) A4規格（2ί〇Χ297公釐） !·*. ·—1 b— - - I JAJ1 I I XT朱 (諳先閱讀背面之注意事項再填寫本頁) -訂 -1, -1, A7 B7 五、發明説明（ 接觸本ίΓ方Ϊ要目的即為揭露-種為積體 電路形成通孔或 成積提供，快速·，縮短形 一目的係為提高形成積體電路之通孔的產能 的明之又—目的係在形成—種具有改善金屬步階覆蓋 根據本發Μ ’ ±雜在形成通孔時料兩階段餘刻，第 -次僅侧絕緣層至-部份深度，織縮小（shHnk)飯刻 用的遮罩(mask)，第二次钕刻再完全穿透絕緣層形成接觸 孔。 在本發明的較佳實施例中，包括下列步驟：在介電層 (dielectric layer)上沈積氮化矽及塗佈光阻，利用光阻 定義圖案（pattern)蝕刻氮化矽形成開口（opening)，透過 開口蝕刻介電層至大於一半深度，經縮小光阻及氮化矽後， 再蝕刻穿透介電層形成接觸孔。 藉由底下的實施例說明並配合所附的圖式，當更容易明 暸本發明之内容及特點。 4·圖式簡單說明 ， 4-1 圖式說明 第一圖之(a)〜（e)圖係一較佳實施例的剖視圖’說明形 成通孔的過程。 4-2 圖號說明 10導電層 12介電層 4- ； ^------，玎------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） π Α7 Β7 五 、發明説明（ 14氮化矽 16光阻 5.洋細說明 根據本發明，主要係在形成通孔時分為兩階段钱 二次僅賴絕緣層至-部份深度，然後縮小侧用 弟二次蝕刻再完全穿透絕緣層形成接觸孔。 ”、 第一圖描述一較佳實施例之詳細步驟，其係在一介電層 上形成通孔，以便後續於通孔内沈積導電層形成插栓，盥& 電層下方之導電層形成接觸。 〃 如（a)圖中所示，首先在導電層1〇上已經形成有介電層 12。為形成通孔，先於介電層12上形成蝕刻用的遮罩，在此 ，使用沈積氮化矽14及塗佈光阻π組成之疊層。將光阻16曝 光及顯影，利用光阻16定義的圖案蝕刻氮化矽14，形成與& 阻16之圖案的輪廓一致的開口，暴露出下方之介電層12。 光阻16之作用係作為蝕刻通孔的遮罩，而氮化矽14則是 在光阻16遮罩縮小银刻時用來控制此縮小遮罩及介電層a之 通孔臨界尺寸(Critical Dimension;CD)’另外亦可當作後續 化學性機械研磨之停止層（St〇p layer)。 本實·^例係為形成多重導電層（肌c〇n_ducUve layer)結構當中連接二導電層之間的通孔β在其他實施例 中’本發明可以用來形成例如與被覆層（pa-SSjVati〇n layer) 上方電極連接的接觸窗，或是與基體(substrate)上方電路元 件的接觸區（contact area)例如電晶體的源極區（source area)和沒極區（drain area)連接的通孔。 一般而言’導電層10係金屬、合金或摻雜的多晶矽（ 本紙張尺度適用中國國家標準（CNS > A4规格（210X297公釐） (諸先閱讀背面之注意事項再填寫本頁) 經濟部令央操準局員工消費合作社印^. -坤衣 ^ '灯 --^--L----^---：______ 腿4392彳8 經濟部中央標準局員工消費合作社印製 Α7 Β7 五、發明説明（） doped polysilicon)。介於導電層之間的絕緣層通常稱為介 電層，其係諸如電聚二氧化砍(plasma oxide)、旋塗玻璃 (Spin-On-Glass;SOG)、硼碟玻璃（Boro—phosphoSilicate1433: 2 1 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (1) Field of the invention The present invention relates to the process of semiconductor devices, especially to the formation of vias or contacts of integrated circuits Window (contact opening) method. 2. BACKGROUND OF THE INVENTION Integrated circuits use insulating layers to isolate metal layers or electrodes, and conductive contacts between circuit elements and metal layers and interconnections between different metal layers are tied to the insulation layer. A via is embedded in a plug to achieve 'this technique is called via contact. The integrated density of integrated circuits is related to the vias. "When the circuit components are scaled down, the dimensions of the vias must also be reduced, resulting in step coverage of metal deposition during the subsequent formation of plugs: step coverage. Poor 'will form voids when depositing metal in the vias, resulting in deterioration of the electrical properties of the via contact. Especially after the line width reaches below the sub-micron, the traditional through-hole contact manufacturing process is no longer applicable. To improve the above-mentioned defects, conventional techniques such as the Republic of China Patent Publication No. 304282 and U.S. Patent No. 5,629,237 are made by using isotropic etch such as wet etch before the insulation A bowl-shaped profile is formed on the layer, and a second contact hole is formed through the insulating layer through a second etching. Although this method can improve the step coverage of the metal, the process is more complicated or time-consuming, for example, using one wet etching and one dry etching, or going through two different etching recipes, or using different | Etch machine. Therefore, it is necessary to find better methods to further solve the lack of know-how. 3_Objective and summary of the invention 3 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2ί〇 × 297mm)! · *. · —1 b—--I JAJ1 II XT Zhu (Read the notes on the back first Fill out this page again)-Order -1, -1, A7 B7 V. Description of the invention (The main purpose of contacting this square is to expose-a way to provide through-holes or integrated circuits for integrated circuits, fast, and shorten the shape The purpose is to improve the productivity of forming the through-holes of the integrated circuit—the purpose is to form—a type with improved metal step coverage. According to the present invention, M ′ ± hybrids are used in the formation of through-holes in the remaining two stages, the first time Only the side insulation layer is to a partial depth, a mask for shHnk rice carving is woven, and the second neodymium carving completely penetrates the insulation layer to form a contact hole. In a preferred embodiment of the present invention, The method comprises the following steps: depositing silicon nitride on a dielectric layer and coating a photoresist, etching the silicon nitride with a pattern defined by the photoresist to form an opening, and etching the dielectric layer through the opening to more than half Depth, after reducing the photoresist and silicon nitride, then etching through the dielectric layer A contact hole is formed. With the following embodiment description and the accompanying drawings, it will be easier to understand the content and features of the present invention. 4. Brief description of the drawings, 4-1 The first illustration of the drawings (a) ~ (E) The figure is a cross-sectional view of a preferred embodiment 'illustrating the process of forming a through hole. 4-2 Figure numbers illustrate 10 conductive layers 12 dielectric layers 4-; ^ ------, 玎 ---- -^ (Please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives This paper is printed in accordance with Chinese National Standard (CNS) A4 (210X297 mm) π Α7 Β7 V. Description of the invention (14 Silicon Nitride 16 Photoresistor 5. Detailed description According to the present invention, it is mainly divided into two stages when forming a through hole. The second time only depends on the insulation layer to a partial depth, and then the side is reduced by secondary etching The contact hole is completely penetrated to form a contact hole. "The first figure describes the detailed steps of a preferred embodiment, which is to form a through hole on a dielectric layer, so that a conductive layer is subsequently deposited in the through hole to form a plug. & The conductive layer under the electrical layer makes contact. 所示 As shown in (a), first A dielectric layer 12 has been formed on layer 10. In order to form a through hole, a mask for etching is formed on the dielectric layer 12. Here, a stack composed of deposited silicon nitride 14 and coated with photoresistance π is used. The photoresist 16 is exposed and developed, and the silicon nitride 14 is etched using the pattern defined by the photoresist 16 to form an opening consistent with the contour of the pattern of the resist 16 to expose the underlying dielectric layer 12. The role of the photoresist 16 It is used as a mask for etching through holes, and silicon nitride 14 is used to control the critical dimension of the through hole (Critical Dimension; CD) when the photoresist 16 mask shrinks the silver engraving. It can also be used as a stop layer for subsequent chemical mechanical polishing. This example is to form a through hole β connecting two conductive layers in a multi-conductor layer structure. In other embodiments, the present invention can be used to form, for example, a coating layer (pa-SSjVati 〇n layer) a contact window connected to an upper electrode, or a contact area connected to a contact area of a circuit element above a substrate, such as a source area and a drain area of a transistor. hole. Generally speaking, the 'conducting layer 10 series metal, alloy or doped polycrystalline silicon (this paper size applies to Chinese national standards (CNS > A4 size (210X297 mm) (please read the precautions on the back before filling this page)) Ministry of Economic Affairs Ordered by the Central Government Bureau of Staff Consumption Cooperative ^. -Kun Yi ^ 'Light-^-L ---- ^ ---: ______ Leg 4392 彳 8 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Α7 Β7 Five Description of the invention () doped polysilicon). The insulating layer between the conductive layers is usually called a dielectric layer, which is such as plasma-oxide, spin-on-glass (SOG) (Boro—phosphoSilicate
Glass;BPSG)、次大氣壓無摻雜旋塗玻璃（Sub-Atmospheric Undoped Spin-on- Glass;SAUSG)、電漿輔助二氧化石夕(peox) 及金屬氧化物(metal oxide)等等這類絕緣層或其組合之疊 層，厚度約為5000至10000埃(A)。 氮化矽14及光阻16的開口具有與接觸孔相同的寬度，透 過他們對介電層12進行部份蚀刻（partial etch)，如（b)圖中 所示，蝕刻孔道之寬度即接觸孔之寬度，但深度僅達一半左 右’並不完全穿透介電層12而到達導電層1〇。 此一蝕刻步驟利用乾蝕刻（dry etch)來達成，其係一非 等向性餘刻（anisotropic etch)。我們採用磁場辅助反應性 離子蝕刻（Magnetic Enhanced Reactive Ion Etch;MERIE)， 使用功率400〜1200瓦(w) ’壓力50〜250毫托(mTorr)，磁場強 度(B-field)10〜50南斯(G) ’晶片背面冷卻(Back SideGlass (BPSG), Sub-Atmospheric Undoped Spin-on-Glass (SAUSG), plasma-assisted peox, metal oxide, etc. A stack of layers or combinations thereof having a thickness of about 5000 to 10,000 Angstroms (A). The openings of the silicon nitride 14 and the photoresist 16 have the same width as the contact hole. Partial etch of the dielectric layer 12 is performed through them. As shown in (b), the width of the etching channel is the contact hole. Width, but the depth is only about half, 'does not completely penetrate the dielectric layer 12 and reach the conductive layer 10. This etching step is achieved using dry etch, which is an anisotropic etch. We use magnetic enhanced reactive ion etching (Magnetic Enhanced Reactive Ion Etch; MERIE), using a power of 400 ~ 1200 watts (w) 'pressure 50 ~ 250 millitorr (mTorr), magnetic field strength (B-field) 10 ~ 50 ns (G) 'Back Side Cooling
Cooling;BSC)lt氣(He)8〜20Torr，氮氣(N2)5〜lOOsccra，氧氣 (〇2)5〜50sccm ’ 氬氣(Ar)10〜200sccm，四氟化碳(CF4)氣體 5〜lOOsccm，CHF3氣體liMOOsccm。 接著，將光阻16及氮化矽14縮小，獲得較寬大的蝕刻圖 案，如（c)圖中所示。此一步驟亦使用MERie，功率 200〜800w，壓力35〜200roTorr，B-field 10~50G，BSCHe氣體 8〜20Torr ’ 〇2氣體5〜50sccm ’ Ar氣體 10〜200sccm，CF4氣體 5~100sccm，CHF3氣體 10〜lOOsccm β 6 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁} •裝· --訂· 14 3 9 2 1 8 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（ 然後，再針對介電層12進行第二次钮刻，使用盥第一次 的製程，不過，為獲得漏斗狀之通孔，^後續導 J層真充’此i刻製程的聚合物沈積率較第—次酬製程 ，旦亦不應太高，以免造成接觸孔内银刻停止。_。蝕刻 後如（d)圖中所示，這次蝕刻讓接觸孔穿透介電^，使 ^10,露出’㈣孔大致呈漏斗形，即通孔之下半部份為較 孔，上半部份為較寬的凹槽。此—結構的通孔在後 績沈積v體時，可以獲得良好的金屬步階覆蓋。 前述使用MERIE之步驟亦可採取其他乾蝕刻製程來完 成，例如電子迴旋共振(Electr〇n Cycl〇tiOn Re_ sonance;ECR)電漿蝕刻。 、對於介電層12的兩次侧皆採取乾糊製程，而不使用 濕餘刻’可以縮在丑製程時間，並且所有的敲刻步驟可以在相 同的韻刻室實施’前後兩次的⑽更可使用類似的配方。 最後再去除光阻16，成為（e)圖中所示狀態。 後續如一般熟知者，將導電層填入通孔内'此非屬本發 明之内容，不再詳述。 ^發明提_單、迅速且穩定的製程，可_短形成通 孔之^間’提高產能。惟’以上所述係藉由實施例說明本發 ^之=點’其目的在使熟f該技術者能瞭解本發明之内容並 ^以實施，而非限定本發明之專利範圍。對於瞭解積體電路 製程之人士而言，报輕易地能夠修改上述實施例，例如使用 不同的遮罩及引用合適_財法料，皆未麟本發明所 揭不之精神。故，本發明應根據以下所述之申請專利範圍而 --J----01¾ — (請先閩讀背面之注意事項再填寫本頁) ίτί-----·}^-----^-------- 本紙張尺度適用中國國家標準（CNS ) 公i~). A7 B7 經濟部中央標準局貝工消費合作杜印製 五、發明説明（ 限定。 8 (諳先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4规格（2I0X297公釐）Cooling; BSC) lt gas (He) 8 to 20 Torr, nitrogen (N2) 5 to 100 sccra, oxygen (〇2) 5 to 50 sccm 'argon (Ar) 10 to 200 sccm, carbon tetrafluoride (CF4) gas 5 to 100 sccm , CHF3 gas liMOOsccm. Next, the photoresist 16 and the silicon nitride 14 are reduced to obtain a wider etching pattern, as shown in (c). This step also uses MErie, power 200 ~ 800w, pressure 35 ~ 200roTorr, B-field 10 ~ 50G, BSCHe gas 8 ~ 20Torr '〇2 gas 5 ~ 50sccm' Ar gas 10 ~ 200sccm, CF4 gas 5 ~ 100sccm, CHF3 Gas 10 ~ lOOsccm β 6 This paper size is applicable to Chinese National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling in this page} • Installation ·-Order · 14 3 9 2 1 8 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (then, the second button engraving is performed on the dielectric layer 12 and the first process is used. However, in order to obtain a funnel-shaped through hole, ^ The subsequent guide layer J is really charged. The polymer deposition rate of this process is higher than that of the first-time process, and it should not be too high, so as not to stop the silver engraving in the contact hole. After etching, as shown in (d) As shown in the figure, the contact hole penetrates through the dielectric ^ this time, so that the exposed hole is roughly funnel-shaped, that is, the lower half of the through-hole is more porous and the upper half is a wider groove. — Structured through-holes can obtain good metal step coverage when depositing v-body later The aforementioned steps using MERIE can also be completed by other dry etching processes, such as electron cyclotron resonance (ECR) plasma etching. Dry paste processes are used for both sides of the dielectric layer 12. Instead of using wet engraving, it can be shortened in the ugly process time, and all the engraving steps can be implemented in the same rhyme chamber. The two times before and after can also use a similar formula. Finally, remove the photoresist 16 and become (E) The state shown in the figure. In the following, as is generally known, the conductive layer is filled into the via hole. This is not the content of the present invention, and will not be described in detail. ^ Invention, single, rapid and stable process, can be _Short time to form through-holes '' to increase production capacity. However, the above description is based on the embodiment to explain the point of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it. It does not limit the patent scope of the present invention. For those who understand the integrated circuit manufacturing process, the report can easily modify the above embodiments, such as using different masks and quoting appropriate_ financial law materials, which are not disclosed by the present invention No spirit. So, this Ming should be based on the scope of patent application described below --J ---- 01¾-(Please read the notes on the back before filling this page) ίτί ----- ·} ^ ----- ^- ------- This paper size applies to Chinese National Standards (CNS). I.). A7 B7 Printed by Shellfish Consumer Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (Limited. 8 (谙 Read the first Please fill in this page for the matters needing attention) This paper size is applicable to Chinese National Standard (CNS) A4 specification (2I0X297 mm)