TW400565B - The manufacturing processes of the shallow trench isolation - Google Patents

Abstract

This invention provides the manufacturing method of the shallow trench isolation to assure the formation more reliable gate oxide around the neighboring areas of the shallow trench isolation. This method includes: to grow a thermal oxide on the surface of the silicon substrate, then, deposit the first polycrystalline silicon layer on the surface of the thermal oxide. Since the thermal oxide will be used as the gate oxide subsequently, there must be enough thickness for protecting the thermal oxide on the first polycrystalline silicon layer; depositing a silicon nitride layer on the first polycrystalline silicon layer, then making a mask to expose the parts of forming the trench of the silicon nitride layer, and etching the above-mentioned silicon nitride layer, the first polycrystalline silicon layer, the thermal oxide, and one part of the silicon substrate for forming a trench. Then, use the chemical mechanical polishing procedure to remove the excess portion on the surface of the dielectrics and use the silicon nitride layer as the stop layer of the polishing procedure. After removing the silicon nitride layer, deposit the second polycrystalline silicon layer over the first polycrystalline silicon layer. Finally, proceed doping, photolithography, and etching toward the two above-mentioned polycrystalline silicon layers in order to define wiring lines.

Description

0339TWF.DOC A7 B7 V. Description of the Invention (t) The present invention relates to a method for manufacturing a cell isolation region on a semiconductor substrate. In many semiconductor circuits, an isolation region is formed between adjacent components to prevent carriers from flowing between adjacent components through the substrate. For example, it is known to form a device isolation region between adjacent field effect transistors (FETs) in a semiconductor volume circuit such as a dynamic random access memory (DRAMs) to reduce leakage current between the FETs. In general, the element isolation region forms a thick field oxide region, which extends below the surface of the semiconductor substrate. In the early days, the most common technique for forming a field oxide region was the local oxidation of silicon (LOCOS) method, as illustrated in Figure 1. Referring now to FIG. 1, a field oxide region 12 in a silicon substrate 10 is used to separate two FETs 14 and 16. Each FET contains a source, a drain, a channel, and a gate above the channel. The components exemplified above may be only a part of a memory circuit. Generally, the component will have external circuits, such as capacitors for storing electric charges, wires formed in the field oxidation region 12 and other areas, and various wires, Contact windows and circuits. The step of forming a field oxide region by the LOCOS method includes: forming a silicon nitride layer on a surface of a silicon substrate; and selectively etching the silicon nitride layer until the silicon substrate to form a silicon nitride mask. The opening of the silicon mask exposes the portion of the silicon substrate where the field oxide region is to be formed; the silicon substrate is placed in an oxidizing environment, and a thick silicon oxide layer is grown on the exposed portion of the opening of the silicon nitride mask. The silicon layer extends below the surface of the silicon substrate and also above the surface of the substrate. Because the silicon nitride mask is difficult to react in an oxidizing environment, the level of the thick silicon oxide layer mainly depends on the silicon nitride. The mask, the silicon oxide will horizontally extend above and below the surface of the silicon substrate along the edge of the silicon nitride mask. Therefore, as shown in the example in Figure 1, ‘the field (please read the notes on the back before filling this page), the words printed by the Central Labor Bureau of the Ministry of Economic Affairs

0339TWF.DOC A7 B7_ 5. Description of the invention (2) The oxidized region 12 includes a bird's beak (i > ird beak) region 18 along its edge, which is thinner than the main part of the field oxidation region. Because we want to develop memory cells with reduced size and space in the future, the beak area formed by the LOCOS method is not what we want, because the beak area is thin and has almost no isolation effect, and the beak area consumes the silicon substrate surface area ' When the desired flatness of the element isolation region is to be provided, the range in which the field oxidation region can be reduced is limited. To provide higher component density, different component isolation configurations are available. Another method for forming an element isolation region is a shallow trench isolation (STI) method. A shallow trench isolation method uses an anisotropic etching method to form a trench on a semiconductor substrate; an oxide is inserted into the trench. In order to provide an element isolation region, the advantages of the shallow trench isolation region formed by the STI method include: providing the element isolation effect over the entire horizontal range; and providing a flatter element structure 'but reducing the immediate isolation of the trench. Zone construction and component reliability. The purpose of the present invention is to provide a method for manufacturing a shallow trench isolation region, so that structures and components adjacent to the trench isolation region have higher reliability, and the isolation region has better flatness. The invention is a method for manufacturing a semiconductor device. The steps include: providing a sand substrate, the silicon substrate having a surface; forming an anode oxide layer on the surface of the silicon substrate; and forming a mask above the gate oxide layer, the The mask has an opening to define a trench uranium engraved area; the gate oxide layer and the surface of the silicon substrate are etched to form a trench in the silicon substrate; an insulating plunger is formed in the trench to make the insulating plunger The top surface of the paper is equal to or higher than the surface of the silicon substrate. This paper is made from the Chinese National Standard (CNS) (2 丨 〇χ297 公) in I I 'IIII-IIII Order — IIII line -. (Please read the note on the back before filling out this page)

0339TWF.DOC A7 B7 5. Description of the invention (3) Higher; forming a wire so that the wire extends above the gate oxide layer portion and above the upper surface of the insulating plunger. Another procedure of the present invention includes: providing a silicon substrate having a surface; forming a gate oxide layer on the surface of the sand substrate; depositing a first conductive material layer on the gate oxide layer; A cover is formed over a conductive material, the cover has an opening to define a trench etch area; the first conductive material layer, the ytterbium oxide layer, and the surface of the silicon substrate are etched to form a trench on the silicon substrate; An insulating plunger is formed in the groove so that the insulating plunger has a flat upper surface; a wire is formed so that the wire extends above the gate oxide layer portion and extends above the upper surface of the insulating plunger , So that at least a part of the wire includes at least a part of the first conductive material layer. Brief description of the figure: Figure 1 illustrates the field oxidation area formed by the LOCOS technology, including the bird's beak area formed around the LOCOS field oxidation area. Figures 2 to 12 show the process steps for forming a conventional trench isolation. 13 to 20 illustrate manufacturing steps for forming a trench isolation region according to a preferred embodiment of the present invention. The conventional method of forming a shallow trench isolation region often results in unsatisfactory coupling between a conductive line and a semiconductor substrate, even when the substrate directly generates a subcritical voltage, that is, conduction. The above-mentioned non-ideal coupling between the conductive line and the substrate and a subcritical voltage The conduction phenomenon is related to the poor gate oxide layer formed under the conductive material layer part, and the conductive material is used as the gate electrode and the first ytterbium wire. The inventor found that the poor gate oxide layer was generated because the oxide plunger that penetrated into the groove was over-etched, so that the surface of the oxide plunger 6 paper New Zealand ^ 1 standard (CNS (210X297) ) --------, ---- ^ ------ 1T ------ ^ (Please read the notes on the back before filling out this page) Central Bureau of Standards, Ministry of Economic Affairs Employee consumer cooperative printing

0339TWF.DOC A7 B7 V. Description of the Invention (4) Below the surface of the silicon substrate adjacent to the trench, an undesired amount of gate oxide is generated on the silicon substrate connected to the over-etched portion of the oxidation plunger. A preferred embodiment of the present invention provides a method for forming a shallow structure isolation region to provide a more reliable gate oxide layer. The feature of the present invention is that a thermal structure is formed before a shallow structure trench is formed on a silicon substrate. Oxide layer, and leave the thermal oxide layer as a gate oxide layer of the transistor; and an oxide plunger penetrating into the shallow trench must be higher than the surface of the silicon substrate to avoid the necessary etching process Thereafter, the upper surface of the oxidation plunger is lower than the surface of the silicon substrate. Another step of forming a shallow trench isolation region according to the present invention is as follows: providing a silicon substrate; forming a gate oxide layer on the surface of the silicon substrate; forming a first conductive layer on the surface of the gate oxide layer; Anisotropic etching etches the first conductive layer, the gate oxide layer, and the surface of the silicon substrate to form a trench on the silicon substrate; inserts an insulating plunger into the trench; and in the first A second conductive layer is formed on a conductive layer so that the second conductive layer also covers the surface of the insulating plunger. Using this embodiment, the step of generating the gate electrode with higher reliability can be selected. This gate oxide layer is formed. Figures 2 to 12 illustrate successive steps of a conventional method for forming a shallow trench isolation region, which is used to isolate a field effect transistor in a memory circuit. The inventor particularly pointed out where the conventional technology forms a poor gate oxide layer, the gate oxide layer is located under a conductive layer, and the poor gate oxide layer may cause part of the conductive layer and the silicon substrate Undesired coupling and conduction phenomenon at sub-critical voltages. After discussing the improperly known techniques in Figures 2 to 12, please refer to Figures 13 to 20, which describe the formation of trench isolation regions in the present invention. Method, this method can produce a more reliable 7 paper size, using China National Standard (CNS) A4 size (210X297 mm): ----, ---_----- pack --- --- Order -------- Line I < Please read note f on the back before filling out this page) Printed by the Central Bureau of the Ministry of Economic Affairs Cooperatives Benben 0339TWF.DOC A7 ________B7 5. Description of the invention (5) Thorium oxide. Figure 2 illustrates the first few steps of a conventional method for forming a shallow trench isolation region: a thermal oxide layer 22 is formed on a silicon substrate 10, and the thermal oxide layer 22 is used as a pad oxide layer for protection during the process On the surface of the silicon substrate 10, & the thermal oxide layer 22 is removed before the last gate oxide layer is formed; by chemical vapor deposition, a silicon nitride layer 24 is formed on the thermal oxide layer 22; A photoresist A is formed on the surface of the nitride layer 24, and the photoresist A is exposed and etched 1J to form an ion cloth mask 26; an ion implantation is applied into the silicon substrate @ 'to form an isolation element, For example, the isolation well is implanted, or the ion-implanted mask 26 is removed by anti-breakdown cloth. Then, referring to FIG. 3, a photoresist B is formed on the nitrided sandstone 24, and the photoresist B is exposed and etched. A trench defining mask 28 is formed later; the silicon nitride layer 24, the thermal oxidation layer 22, and the substrate 10 are continuously etched to form a trench 30, see FIG. 4; and then the trench etching mask 28 is removed. Next, silicon monoxide 32 is poured into the formation groove 30 to form the silicon oxide% method, such as atmospheric pressure chemical vapor deposition (APCVD), using tetraethylsilicon oxide (TEOS) as the gas, the silicon oxide 32 Excessive amounts must be introduced, see Figure 5 'because a TEOS oxide formed will shrink in the subsequent densification process; then at about 1000 ° C, processing for 10 to 30 minutes to densify the TEOS oxide; and then The chemical mechanical polishing method removes the excess TEOS oxide to achieve comprehensive planarization. The silicon nitride layer 24 is used as a polishing stop layer, leaving an oxide plunger 34 in the trench region (see FIG. 6). Figure 6 does not show that, because the oxidized plunger is “softer” than the silicon nitride layer 24, during the chemical mechanical process, the oxidized plunger is abraded more and its surface height is lower than the nitride 8 This paper size uses China National Kneading Rate (CNS) A4 specification (210X297 mm) --- J--; ---------------------- order line.-(Please first (Read the note on the back and fill in this page)

0339TWF.DOC A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (6) The surface of the silicon layer 24; removing the silicon nitride layer 24 to reveal the thermal oxide layer 22 will generally leave a part located in the The oxidation plunger 34 on the surface of the thermal oxidation layer 22; immersed in hydrofluoric acid (HF) to remove the thermal oxidation layer 22, (see FIG. 8), at this time, the oxidation plunger 34 is etched faster than the thermal The oxide layer 22 is etched at a high speed. A sacrificial oxide layer 36 is then grown on the silicon substrate 10 to protect the surface of the silicon substrate from damage in subsequent steps. One or more ion implants, such as a critical voltage adjustment implant (such as (Shown in Figure 9); immersion in hydrofluoric acid (HF) to remove the sacrificial oxide layer 36, the result is shown in Figure 10 ^ After the oxide layer etching steps as shown in Figure 8 and Figure 10, often a large number of The oxidized plunger 34 is also etched away, so that the surface of the oxidized plunger 34 is lower than the surface of the silicon substrate 10, and the above-mentioned over-etching phenomenon is mostly shown in the oxidation pillar adjacent to the surface of the silicon substrate 10. The edge of the plug 34 or the entire surface of the oxidation plunger is evenly lower than the surface of the silicon substrate 10. Another case is that over-etching may cause a part of the substrate 38 at the side wall of the trench to be exposed, or the silicon oxide layer on the silicon substrate adjacent to the side wall of the trench is too thin. Now referring to FIG. 11, in FIG. On the exposed surface of the silicon substrate 10, a gate oxide layer 40 grows at a high temperature. The gate oxide layer 40, which is usually located on the part of the silicon substrate 38 on the side wall of the trench, is of poor quality. A polycrystalline silicon layer 42 is deposited on the surface of the silicon substrate; an ion implantation and annealing process is performed on the polycrystalline silicon 42; and a pattern is transferred to form a conductive line 44, as shown in FIG. Since the wire 44 generally extends over the gate oxide layer 40 and the oxide plunger 34, it must extend above the portion of the silicon substrate 38 adjacent to the side wall of the trench, and therefore, it is located above the 38 with a poor quality. This paper size applies to Chinese National Standard (CNS) A4 specification (219X297 mm) ^ ---- packing— (Please read the precautions on the back before filling this page)

0339TWF.DOC Α7 B7 V. Description of the invention (7) The gate oxide layer and the protruding silicon substrate will cause the phenomenon of 'undesired coupling of the wire 44 and the silicon substrate 10 or conduction at a subcritical voltage'. Because the undesired coupling or conduction between the wire and the silicon substrate is not what we want, the inventor will modify the process of forming a shallow trench isolation region, see Figures I3 and 20 and the following The content of the description. / In order to avoid the poor quality and unreliable gate oxide layer adjacent to the shallow trench isolation region, a preferred embodiment of the present invention forms a gate oxide layer at an earlier step in the semiconductor circuit process, and the formed A shallow trench isolation region passes through the gate oxide layer. Another feature of the present invention is that a sufficient amount of oxidation pillars are inserted into the trench, so that the surface of the silicon substrate adjacent to the sidewall of the trench is not exposed as much as possible during the formation of the shallow trench isolation region. The preferred embodiment of the present invention provides a more reliable gate oxide layer and reduces the phenomenon of conduction between the wire and the silicon substrate at a subcritical voltage. The preferred embodiment of the present invention is as described now, and please refer to FIGS. 13 to 20. In order to make the above-mentioned and objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: For an embodiment, refer to FIG. 13. A thermal oxide layer 50 is formed on the surface of the silicon substrate 10, and the thermal oxide layer 50 must meet the requirements of the transistor in the semiconductor circuit, because the thermal oxide layer 50 is regarded as a gate oxide layer when the device is completed; A conductive material layer 52 is formed on the surface of the oxide layer 50. In this embodiment, the conductive material layer 52 will be left as a lower layer of the conductive material. The advantage of leaving the conductive material layer 52 is that in the subsequent steps Medium and insurable paper sizes are applicable to China National Standards (CNS) A4 specifications (21〇 × 25 > 7 mm) (锖 Please read the precautions on the back before filling out this page) Printed by a cooperative

0339TWF.DOC 0339TWF.DOC Printed by A7 __ B7 in the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) Protect the gate oxide layer that has been formed in the first step, so as to produce a higher quality gate An oxide layer is a lower layer wire in a semiconductor circuit, and is usually used to form a gate electrode. The conductive material layer is a low-voltage chemical vapor deposition method that deposits a polycrystalline silicon with a thickness of about 400 to 1000 A. The conductive material The layer preferably has a sufficient thickness to protect the gate oxide layer 50 in the subsequent steps, but it should not be too thick, so as not to hinder the subsequent steps such as ion implantation. In these implementations, “the conductive material layer 52 is usually polycrystalline silicon, and it is best not to implant it first” to wait until the later step to implant; a high temperature annealing step may be applied to make impurities (such as doped ions) ) Diffused from the polycrystalline silicon layer to the gate oxide layer 50. Then 'deposit a masking material layer 54 on the conductive material layer 52. The main purpose of the masking material layer 54 is to protect the conductive material layer in subsequent steps', for example, by chemical mechanical polishing (CMP) to remove the intrusion. When the excess portion of the insulating plunger of the trench is 'the mask material layer is used as a polishing stop layer, silicon nitride is particularly suitable as a mask material, because silicon nitride is durable and stable when used as a CMP stop layer' When silicon nitride is used as the mask material layer 54, a thickness of 1000 to 3000 A is deposited; then, a photoresist layer is formed on the surface of the mask material layer 54; and the photoresist layer is formed into a trench by a general method. The mask 56 is etched, so that the surface of the mask material 54 exposes the area 58 to be etched into a groove. The pattern of the groove etch mask has been completed, please refer to FIG. 14, and the mask 56 is etched with the groove. It is used to etch 54, 52, 50 layers and the silicon substrate 10 to form a trench. This is followed by a series of etching steps. A preferred etching method is anisotropic etching, such as reactive ion etching (RIE). The size of this paper etched with silicon nitride is applicable to China National Standard (CNS) A4 specification (210X297 mm) L- ---- Γ ---- ^-(Please read the note on the back before reading (Fill in this summer)

0339TWF.DOC A7 B7 Consumption cooperation between employees of the Central Bureau of quasi-government of the Ministry of Economic Affairs. Printing 5. Description of the invention (9) The mask material layer 54 is suitable for mixed gas, including SF6, He and 〇2; and the conductive material is etched Layer 52, suitable mixed gas, including Ci2, He, HBr, and 〇2; and etching the gate oxide layer 50, suitable mixed gas, including CHF3, 〇2, and Ar; and etching the silicon substrate 10, suitable The mixed gas, including Cl2, He, HBr, and O2, plus a very small amount of SF6, makes the bottom of the silicon substrate 10 form a rounded edge. Referring to FIG. 15, in order to complete the trench etching step, the depth of the trench is about 4,000 people. If necessary, a thermal oxidation thin layer may be formed on the sidewall and bottom of the trench to remove defects generated during the etching step, and the thermal oxidation thin layer may be left or removed. Next, a thick layer of insulating material 60 is deposited on the trench and the exposed surface. As shown in FIG. 16, the commonly used method is ozone TEOS or CVD TEOS procedure. The conventional CVD technology includes normal pressure CVD method, low pressure CVD method and plasma. Strengthen the CVD method. When TEOS oxide is used as the insulating material 60, its thickness is 6000A. It is necessary to charge an excessive amount of insulating material, because during the densification process, the deposited insulating material is reduced by about 4-10%, and the density is reduced. It is treated at a high temperature of about 1000 ° C for 10 to 30 minutes. Next, the excess insulating material 60 ′ is removed by common chemical mechanical polishing (CMP) and ground to the surface of the mask material 54. When using CMP, the mask material 54 layer (silicon nitride or other hard substances) is used. 'It is used as the CMP stop layer, and then the mask material layer 54 is removed, and if nitrided sand is used as the mask', it can be removed by wet etching such as h3po4 in aqueous solution at 150.8 ° C or plasma etching. The gases are SF6 'He and 〇2. For the figure after the mask material layer 54 is removed, please refer to FIG. 18, and then (please read the precautions on the back before filling this page) • ΙΊ · -binding · binding-thread paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm>

0339TWF.DOC A7 B7 V. Description of Invention (ίο), the implantation of ion implantation 'well implantation and channel-planting can pass through the conductive material layer 52 (polycrystalline silicon)' and the oxide layer 50 'well implantation is By implanting boron or phosphorus ions at an energy of about 300 to 100 OKeV, the conductive material layer 52 and the oxide layer 50 can be penetrated into the silicon substrate 10, and the channel is implanted and operated at a lower energy. The same is Doped with boron, phosphorus or arsenic ions. In the above-mentioned implantation step, rapid high temperature annealing (1000-1100 ° C, 10-60sec) can be used to activate the implanted impurities. After implantation and activation, a second conductive material layer 64 is deposited on the lower conductive material layer 52. As shown in FIG. 19, if a low pressure chemical vapor deposition method is used, it is deposited at about 620 ° C. A polycrystalline silicon layer with a thickness of about 400 to 2500 A; when the deposition is completed, it is necessary to implant the 52 and 64 rain layers, such as phosphorus ion or boron ion. After the implantation, it can be activated by high temperature annealing. Deposit a high temperature metal or high temperature metal silicon compound (such as tungsten silicide) on the second conductive material layer 64, or replace the second conductive material layer, so that the conductive material contains the metal silicon compound, and the thickness of the wire is about 2000 ~ 3000A. The conductive material layers 52 and 64 are also used as the gate of the transistor, such as the gate electrode, the special configuration of the conductive layer must be considered; then, pattern transfer and etching are performed to form a wire 66, as shown in FIG. 20, Then, the device is completed by the conventional semiconductor process. The dotted line in FIG. 20 shows two separated layers of conductive material (polycrystalline silicon). As described above, according to the method of manufacturing a shallow trench isolation region according to the present invention, a gate oxide layer is formed in an appropriate step of the process to maintain its high quality, and it also reduces the reduction in the height of the insulating plunger below the surface of the silicon substrate. opportunity. Although the present invention has been disclosed as above with a preferred embodiment, it is not applicable to the Chinese National Stick with 13 paper sizes ^ 21_7 / @ L-IJ --- Γ ---- ^ ------- 1T- ----- ^ *-{Please read the precautions on the back before filling out this page) Printed by Duongcheng

0339TWF.DOC A7 B7 V. Description of the invention (J p to limit the invention, anyone skilled in the art can make some changes and retouch without departing from the spirit and scope of the invention, so the scope of protection of the invention should be Subject to the scope of the attached patent application. (Please read the notes on the back before filling out this page.) The paper size of the printed paper is applicable to the Chinese National Standard (CNS) A4 specification. (210X297 mm)

Claims (1)

Printed by A8 0339TWF.DOC g D8, Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6. Application for a patent 1. A semiconductor manufacturing method comprising the steps of: providing a silicon substrate having a surface; on the surface of the silicon substrate, Forming a gate oxide layer; forming a mask on the gate oxide layer, the mask having an opening defining a trench etching area; etching the gate oxide layer and the surface of the silicon substrate to form a trench on the gate oxide layer A silicon substrate; an insulating plunger is formed in the groove, so that the upper surface of the insulating plunger is equal to or higher than the surface of the silicon substrate; and a wire is formed to extend the wire A portion above the gate oxide layer and extending above the upper surface of the insulating plunger. 2. A method for manufacturing a semiconductor device, comprising the steps of: providing a silicon substrate having a surface; forming a gate oxide layer on the surface of the silicon substrate; and depositing a first on the gate oxide layer A conductive material layer; forming a mask on the first conductive material layer, the mask having an opening defining a trench etching area; using the opening of the mask to etch the first conductive material layer, the gate oxide layer and the A surface of a silicon substrate to form a trench on the silicon substrate; forming an insulating plunger in the trench, the upper surface of the insulating plunger; and forming a conductive line extending above the gate oxide layer A portion of the conductive plunger extends on the upper surface of the insulating plunger such that at least a portion of the wire includes at least a portion of the first conductive material layer. 3. The method as described in item 2 of the scope of patent application, wherein the first conductive -----------------------------1T------.it «~ (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) ° 339TWF.D〇C B8 C8 D8 The material layer of the patent application scope includes polycrystalline silicon; 4. The method as described in item 3 of the patent application scope, further comprising applying a critical voltage adjustment implantation step, passing through the first conductive material layer and the gate electrode Thorium oxide enters the silicon substrate. 5. The method as described in item 4 of the scope of patent application, further comprising the step of applying a rapid annealing at high temperature to deal with the threshold voltage adjustment implantation. 6. The method according to item 3 of the scope of patent application, wherein the polycrystalline silicon is not grafted with impurities and has a thickness of about 400 to ΐοοοΑ. 7. The method according to item 2 of the scope of patent application, further comprising the step of depositing a first material layer on the first conductive material layer, wherein the second material layer has a surface and is etched to form a trench. In the step, the first conductive material layer is etched away first. 8, The method according to item 2 of the scope of patent application, wherein the method of forming the insulating plunger is to deposit a second oxide layer on the surface of the substrate and in the groove. 9. The method as described in item 8 of the scope of patent application, further comprising the step of removing a part of the first to the second oxide layer, so that the upper surface of the second oxide layer is equal to the second material layer. 10. The method according to item 8 of the scope of the patent application, wherein the insulating plunger includes inserting an excessive amount of the second oxide layer into the groove, preferably a portion of the second oxide layer is excessive, and chemical mechanical polishing is performed. Law removal. 11. The method of claim 10, wherein the second material layer is used as a stop layer for chemical mechanical polishing of the second hafnium oxide. The method described in item 10 of the scope of patent application, wherein the paper size of the second material is applicable to the Chinese National Standard (CNS) A4 (210X297 mm)! Ur— | ~ 装 —— Ί. I ϋ nn 线 ( Please read the note on the back before filling in this page) ABCD 0339TWF.DOC 6. The scope of patent application is expected to include silicon nitride. 13. The method according to item 3 of the scope of patent application, further comprising two steps of depositing a second conductive material layer on the first conductive material layer; and implanting on the second conductive material layer. 14. The method according to item 2 of the scope of patent application, further comprising the step of growing a thin layer of thermal oxidation in the trench. 15. The method according to item 2 of the scope of patent application, wherein the upper surface of the insulating plug is equal to or higher than the surface of the silicon substrate. (Please read the note $ on the back before filling out this page)-Binding and Binding Line Printed by the Employees' Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs This paper uses the Chinese National Standard (CNS) A4 size (210X297 mm)