492142 Α7 Β7 五、發明説明（ 發明領域 經濟部智慧財產局員工消費合作社印製 本發明係有關於一種利用新式製程改良半導體內隔離 的方法。更仔細來說，本發明使用新的製程形成之隔離，達 到減小積體電路的體積，及避免自行對準製程矽化鈦短路的 目的。 發明背景： 非揮發性記憶體（nonvolatile memory)包含罩幕式唯 讀記憶體（Mask ROM)、可程式唯讀記憶體（PROM)、可抹除 且可程式唯讀記憶體（EPROM )、可電除且可程式唯讀記憶體 (EEPR0M 〇 r E2PR0M )、以及快閃記憶體（f 1 a s h memo ry )等， 其特性在可於電源移除後，仍保留住所儲存的資料。非揮 發性記憶體在電子及計算機工業中應用非常廣泛。參考A . Bergemont 等人之論文：“Low Voltage NVGTM: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Application” （in IEEE Trans. Electron Devices Vo 1 . 43，p . 1510，1 9 9 6 ) 中陳述，近幾年來，由於市場的發展快速，可攜式電腦與 電信工業已成爲半導體積體電路設計技術的主要驅動力， 因此對於低功率、高密度且可重複讀寫的非揮發性記憶體 請v 先、 閱 背 之 注 意 事 項 再 填 本 頁 訂 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 492142 A7 _____B7_ 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 產生了大量的需求。這些可程式且可抹除的記憶體可以儲 存上述系統中的作業系統以及應用軟體，是不可或缺的基 本元件之一。 當隨著對記憶體之功能需求更多，積集度的要求也就更 高了’更高積集度之發展意謂著更大容量之記憶體的產生。 快閃記憶體當基於其資料可以多次存入，讀出與淸除之優 點，成爲發展最快速的新一代記憶體之一。 經濟部智慧財產局員工消費合作社印製 請參閱第一圖，圖中顯示出記憶體的佈局。在第一圖中 所顯示的爲雙晶記憶晶胞（Twin Cell)的架構，以目前一般 所使用的設計法則中，爲了防止接觸窗有對準失當 (πη sal lgn)的情況出現，在設計階段將接觸窗5預定置入位 置的周圍都會預先留下一些邊界（margin)6。邊界6的功能 是用以防止一但有對準失當發生時，接觸窗5的位置變得有 所偏移，而沒有落在預設正確的位置上，接觸窗5的偏移使 得其位置插入至原本設置周圍遇留的邊界6安全區內。因爲 邊界有隔離功能的關係，與其它的元件亦達成了良好的阻 隔，所以落在邊界6中的接觸窗5不會與其周圍其他不應該 連結的部分接觸，如此即減少了形成短路的可能性。因爲其 避免了電路發生短路的特性，使得整體電路有良好的表現’ 然而因爲邊界所需要佔用的空間位置，使得半導體的積集度 無法更佳的提昇。 在製造多層積體電路的製程上，爲了半導體元件有更佳 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 492142 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 的表現，當元件的積集度增加，使得半導體元件之汲極與源 極的電阻逐漸上升，到與半導體元件之通道（channel)的電 阻相當時，爲了調降汲極與源極的片電阻（sheet resistance)，並確保金屬與金屬氧化物半導體（MOS)之間 '的”淺接面（shallow I unction)”的完整，需要進行應用自行 對準金屬矽化物（self-aligned si licide)的製程。簡單來 說在此製程內將鈦濺鍍於表面後，藉由快速加熱製程，鈦與 矽化物反應形成良導體，但是鈦並而不會與氧化物反應，便 將所剩餘的鈦以濕蝕刻的方法加以去除，在理想的情況下矽 化鈦會在汲極、源極與閘極的表面上留下來。但是第一圖之 雙晶記憶晶胞架構中，前後或左右相鄰的記憶晶胞7上方所 形成之矽化鈦，因爲沒有明顯的隔離所以有發生短路，而會 影響其性能表現的情況。 因此需要一種新的製程方法，以避免半導體內矽化鈦的 短路問題，並且可在相同或更高的積集度下，增強元件的效 能。 發明目的及槪沭： 經濟部智慧財產局員工消費合作社印製 本發明的主要目的爲提供非揮發性記億體一種改良設 計設計法則的製作方法，改善了當接觸窗的位置有對準失當 的情況發生時，會發生短路的缺點。 492142 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 本發明的另一目的在於提供非揮發性記憶體一種節省 傳統設計設計法則之空間的製作方法，因爲當對準失當發生 不會對電路有發生短路的影響，所以使得接觸窗周圍不需要 預留邊界。而藉由減少邊界所佔用的空間’以增加積體電路 之積集度。 本發明的再一目的在於提供非揮發性記憶體一種改良 在多層積體電路應用缺點的製作方法。用以防止自行對準製 程中矽化鈦在閘極、汲極與源極之間或不同的電晶體間的短 路。 本發明的更一目的在於利用本發明並不需要額外的光 罩。因此應用本發明的架構亦不需要額外的製程，更不會以 此而增加成本。 本發明提供一種節省傳統設計法則空間並防止後 續無邊界製程中自行對準矽化鈦短路之半導體元件的製作 方法，該方法至少包含：形成淺溝渠隔離區域（STI)於一半 導體晶圓基材之上，摻雜穿隧氧化層於該基材上，再分別沈 積多晶矽層及氮化矽層，在製作出金氧半導體（MOS)主動區 域之位置後，以離子佈植製程分別植入及埋入式汲極（BD) 及大角度斜向汲極（LATID)，然後再沈積高密度電漿氧化層 (HDP)。隨後移除部份HDP氧化層，接著再加上另一層氮化 矽。移除部份之該HDP氧化層後，使得氮化矽上側的邊緣外 露’再以蝕刻移除氮化矽，同時也移除了在氮化矽上方的 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） — 一- — ^----噃----^-Iβ------#. (請先閱讀背面之注意事項再填寫本頁) 492142 A7 B7__ 五、發明説明（） HDP氧化層。接下來形成第二多晶矽層於前一多晶矽層及 HDP氧化層上之後微影蝕刻。之後再分別生成ΟΝΟ層、另一 多晶矽層及外罩幕層。在圖案化硬罩幕層及分別完成多晶矽 層、0Ν0層及第一、第二多晶矽層的蝕刻之後，以HDP氧化 ‘層做爲硬罩幕，移除半導體晶圓之矽，以定義出凹陷區域。 然後再移除遺留下來的HDP氧化層。最後再沈積一保護層於 該凹陷區域中及該半導體矽基材之上，接著鈾刻最後沈積之 保護層，且因此得到一位置在凹陷上緣延伸至硬罩幕層的間 隙壁，之後可以銜接傳統上一般多層積體電路應用的製程， 例如無邊界（boarderless)接觸窗製程或自行對準砂化物製 程。 圖式簡單說明= 由以下本發明中較佳具體實施例之細節描狀，可以 對本發明之目的、觀點及優點有更佳的了解。本發明之參考 圖形如下： 第一圖 爲一半導體晶片剖底面圖，說明先前技術中接觸窗 之位置； 第二圖 爲一半導體晶片剖底面圖，說明本發明於基材上形 成溝渠結構之步驟；492142 Α7 Β7 V. Description of the Invention (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Invention Field of the Invention The present invention relates to a method for improving the isolation within a semiconductor using a new process. More specifically, the present invention uses the isolation formed by a new process To achieve the purpose of reducing the volume of the integrated circuit and avoiding the short circuit of the self-aligned titanium silicide process. BACKGROUND OF THE INVENTION Nonvolatile memory (nonvolatile memory) includes a mask ROM and a programmable ROM. Read Memory (PROM), Erasable and Programmable Read Only Memory (EPROM), Erasable and Programmable Read Only Memory (EEPR0M 〇r E2PR0M), and Flash Memory (f 1 ash memo ry) Etc., its characteristics can retain the stored data after the power is removed. Non-volatile memory is widely used in the electronics and computer industry. Refer to the paper by A. Bergemont et al: "Low Voltage NVGTM: A New High Performance 3 V / 5 V Flash Technology for Portable Computing and Telecommunications Application "(in IEEE Trans. Electron Devices Vo 1.43, p. 1510, 1 9 9)), in recent years, due to the rapid development of the market, the portable computer and telecommunications industry has become the main driving force of semiconductor integrated circuit design technology, so for low power, high density and Non-volatile memory that can be read and written repeatedly, please v, read the notes before refilling this page, the paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 492142 A7 _____B7_ V. Description of the invention () (Please read the precautions on the back before filling out this page.) There is a lot of demand. These programmable and erasable memory can store the operating system and application software in the above systems, which is one of the essential basic components. As more functions are required for memory, the requirement for accumulation is higher. The development of higher accumulation means the generation of larger memory. Flash memory should be based on it Data can be stored multiple times, read and erased, and has become one of the fastest-growing next-generation memories. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics A picture showing the layout of the memory. The first picture shows the structure of the twin-crystal memory cell (Twin Cell). In order to prevent the contact window from being aligned, according to the design rules currently used in general In the case of misalignment (πη sal lgn), some margins 6 are left in advance around the predetermined placement position of the contact window 5 in the design stage. The function of the boundary 6 is to prevent the position of the contact window 5 from shifting when there is a misalignment without falling on the preset correct position. The offset of the contact window 5 causes its position to be inserted. Go to the security zone of border 6 that was originally set around. Because the boundary has the function of isolation and achieves good barriers with other components, the contact window 5 falling in the boundary 6 will not contact with other parts around it that should not be connected, which reduces the possibility of forming a short circuit. . Because it avoids the short circuit characteristic of the circuit, it makes the overall circuit perform well. However, because of the space position occupied by the boundary, the semiconductor accumulation cannot be improved. In the process of manufacturing multilayer integrated circuits, in order to have better semiconductor components 3 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 492142 A7 B7 V. Description of the invention () (Please read the note on the back first (Please fill in this page again), when the accumulation degree of the device increases, the resistance of the drain and source of the semiconductor device gradually rises to reach the resistance of the channel of the semiconductor device, in order to lower the drain Sheet resistance to the source, and to ensure the integrity of the "shallow I unction" between the metal and the metal oxide semiconductor (MOS), the application needs to self-align the metal silicide (self -aligned si licide). In short, after sputtering titanium on the surface in this process, through rapid heating process, titanium reacts with silicide to form a good conductor, but titanium does not react with the oxide, and the remaining titanium is wet-etched. Method to remove, in the ideal case, titanium silicide will remain on the surface of the drain, source and gate. However, in the dual-crystal memory cell structure of the first figure, the titanium silicide formed on the front and back or left and right adjacent memory cells 7, because there is no obvious isolation, there is a short circuit, which will affect its performance. Therefore, a new process method is needed to avoid the short circuit problem of titanium silicide in the semiconductor, and to enhance the performance of the device at the same or higher integration level. Purpose of the invention and the following: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics The main purpose of the present invention is to provide a non-volatile memory device with an improved design and design method, which improves the misalignment of the contact window. The shortcoming of a short circuit occurs when the situation occurs. 492142 Printed by A7 B7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the invention () Another object of the present invention is to provide a non-volatile memory, a manufacturing method that saves space in traditional design rules, because misalignment occurs There will be no short circuit effect on the circuit, so there is no need to reserve a boundary around the contact window. And by reducing the space occupied by the boundary 'to increase the integration degree of the integrated circuit. It is still another object of the present invention to provide a method for manufacturing a non-volatile memory which improves the disadvantages of the application in a multilayer integrated circuit. It is used to prevent short circuit of titanium silicide between gate, drain and source or different transistors during self-alignment process. A further object of the present invention is that no additional photomask is required to use the present invention. Therefore, no additional process is required to apply the structure of the present invention, nor will it increase costs. The invention provides a method for manufacturing a semiconductor device that saves space of a conventional design rule and prevents self-alignment of titanium silicide short circuits in a subsequent borderless process. The method at least includes forming a shallow trench isolation region (STI) on a semiconductor wafer substrate. On the substrate, a doped tunneling oxide layer is doped on the substrate, and then a polycrystalline silicon layer and a silicon nitride layer are respectively deposited. After the position of the active region of the metal-oxide-semiconductor (MOS) is fabricated, they are implanted and buried by ion implantation. BD and LATID, and then deposit high-density plasma oxide (HDP). Then remove part of the HDP oxide layer, and then add another layer of silicon nitride. After removing part of the HDP oxide layer, the upper edge of the silicon nitride is exposed, and then the silicon nitride is removed by etching. At the same time, the 5 paper sizes above the silicon nitride are applied to the Chinese national standard (CNS ) A4 specification (210X297 mm) — 1 — — ^ ---- 噃 ---- ^-Iβ ------ #. (Please read the notes on the back before filling this page) 492142 A7 B7__ 5 2. Description of the invention () HDP oxide layer. Next, a second polycrystalline silicon layer is formed on the previous polycrystalline silicon layer and the HDP oxide layer, and then lithographically etched. After that, an ONO layer, another polycrystalline silicon layer, and a cover curtain layer were generated. After patterning the hard mask layer and completing the etching of the polycrystalline silicon layer, ON0 layer, and the first and second polycrystalline silicon layers, the HDP oxide 'layer is used as the hard mask, and the silicon of the semiconductor wafer is removed to define Out of the recessed area. Then remove the remaining HDP oxide layer. Finally, a protective layer is deposited in the recessed area and on the semiconductor silicon substrate, and then the last deposited protective layer is etched by uranium, and a gap wall extending from the upper edge of the recess to the hard mask layer is obtained. It is a process that connects to traditional multi-layer integrated circuit applications, such as a boarderless contact window process or a self-aligned sand process. Brief description of the drawings = The following detailed description of the preferred embodiments of the present invention can better understand the purpose, viewpoints and advantages of the present invention. The reference figure of the present invention is as follows: The first figure is a bottom view of a semiconductor wafer, illustrating the position of a contact window in the prior art; the second figure is the bottom view of a semiconductor wafer, illustrating the steps of forming a trench structure on a substrate according to the present invention ;
第三圖 爲一半導體晶片剖底面圖，說明本發明於基材上以 化學機械式硏磨去除部份第二氮化矽層及部份HDP 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) -- L.... I IT I n I i^_^.-- (請七閱讀背面之注意事項再填寫本頁) 、?τ 經濟部智慧財產局員工消費合作社印製 492142 A7 B7 五、發明説明（） 氧化層之步驟； 第四圖 爲一半導體晶片剖底面圖，說明本發明於移除氮化 矽層後，將第二多晶矽層沈積、微影及蝕刻之後的步 驟； •第五A圖爲一半導體晶片剖底面圖，說明本發明在SAM0S製 程中圖案化硬罩幕層後，蝕刻第三多晶矽、0N0層、 第二多晶矽層及第一多晶矽層之步驟； 第五Β圖爲一半導體晶片剖底面圖，說明本發明於以HDP氧 化層爲罩幕飽刻砂基材形成凹陷之步驟； 第六圖爲一半導體晶片俯視圖，說明本發明於沈積第三多 晶矽層及沈積硬罩幕層之步驟，並顯示本發明之方法 所形成的槪略結構； 第七圖爲一半導體晶片底剖面圖，說明第六圖中ΒΒ截面之 結構； 第八圖 爲一半導體晶片剖面示意立體圖，說明本發明之將 保護層以非等向性蝕刻後，形成間隙壁之結構； 桌九Α圖爲同第六圖結構之ββ截面圖之對照，即第六圖中 X軸的結構；及 第九B圖爲同第六圖結構之dd截面圖之對照，即第六圖中 Y軸的結構。 號對照說明： 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） --1----續—— (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 492142 A7 _ B7_^__ 五、發明説明（） 5 接觸窗 6 邊界（margin) 7 晶胞 10 基材 (請先閲讀背面之注意事項再填寫本頁)The third figure is a bottom view of a semiconductor wafer, illustrating that the present invention removes part of the second silicon nitride layer and part of HDP by chemical mechanical honing on the substrate. The paper size is applicable to the Chinese National Standard (CNS) A4 specification. (210X297mm)-L .... I IT I n I i ^ _ ^ .-- (Please read the precautions on the back before filling out this page),? Τ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 492142 A7 B7 V. Description of the invention () Oxidation step; The fourth figure is a bottom view of a semiconductor wafer, illustrating that the present invention deposits, lithographs, and etches the second polycrystalline silicon layer after removing the silicon nitride layer. The subsequent steps; Figure 5A is a bottom view of a semiconductor wafer, illustrating that the present invention etches the third polycrystalline silicon, the 0N0 layer, the second polycrystalline silicon layer and the first polycrystalline silicon layer after patterning the hard mask layer in the SAM0S process. A step of a polycrystalline silicon layer; FIG. 5B is a bottom view of a semiconductor wafer, illustrating the steps of the present invention for forming a depression on a sand-saturated substrate using an HDP oxide layer as a mask; and FIG. 6 is a top view of a semiconductor wafer. Explain that the present invention is used for depositing a third polycrystalline silicon layer and a deposited hard mask layer Steps, and shows the rough structure formed by the method of the present invention; the seventh figure is a bottom cross-sectional view of a semiconductor wafer, illustrating the structure of the BB cross-section in the sixth figure; the eighth figure is a schematic perspective view of a semiconductor wafer, illustrating the present invention. Invented, the protective layer is anisotropically etched to form the structure of the partition wall. Table 9A is a comparison with the ββ cross-sectional view of the structure in FIG. 6, that is, the structure of the X axis in the sixth figure; and ninth B The figure is in contrast to the dd cross-sectional view of the structure of the sixth figure, that is, the structure of the Y axis in the sixth figure. No. comparison description: This paper size is applicable to China National Standard (CNS) A4 specification (21 × 297 mm) --1 ---- continued-- (Please read the precautions on the back before filling this page) Order the wisdom of the Ministry of Economic Affairs Printed by the Consumer Affairs Cooperative of the Property Bureau 492142 A7 _ B7 _ ^ __ 5. Description of the invention () 5 Contact window 6 Margin 7 Cell 10 Substrate (Please read the precautions on the back before filling this page)
11 淺溝渠隔離區域/STI 12 第一氧化層/穿隧氧化層（Tox) 13 第一多晶矽層 14 第一氮化矽層 15 埋入式汲極（BD) 16 大角度斜向汲極（LATID) 17 第二氧化層/高密度電漿氧化層（HDP ) 18 第二氮化矽層覆蓋 19 第二多晶矽層 20 介電材料層/0N0 21 第三多晶矽層 22 罩幕層（矽化鎢/二氧化矽） 23 保護層（TE0S) 24 凹陷 25 間隙壁 26 介電材料層 27 接觸窗 28 氮化矽層 發明詳細說明= 經濟部智慧財產局員工消費合作社印製 本發明係揭露一種新型隔離之製程方式。於本發明 中，藉由新的製程方法形成隔離，該隔離可以取代接觸窗的 周圍的絕緣區，用以預防當接觸窗位置的對準失當發生時所 產生之短路，而節省了傳統上設計法則中使用較大邊界 (margin)的設計，使電晶體得到更緊密的設計。並且在後續 的無邊（boarderless)接觸窗製程中，本發明所形成的隔離 8 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 492142 A7 ___ B7 _ 五、發明説明（） 亦可以避免新生成之自行對準矽化鈦短路的情況。 (請先閱讀背面之注意事項再填寫本頁) 自第二圖至第九B圖表示爲本發明使用於非揮發 性快閃記億體上，雙電晶體（twm-cell)架構的具體實施 例。請參考第二圖所述，首先提供一具有<100>結晶面之單 .晶半導體基材1 0，然後利用傳統製程方法形成隔離，以較 佳實施例來說，形成淺溝渠隔離區域11 (Shallow Trench Isolation，STI)於該半導體基材中，溝渠之深度大約爲 3 500 - 4000埃，在此做爲主動區域之間的隔離。以避免操作 時彼此之間的干擾。此STI製程可利用氮化矽層/墊氧化層 爲罩幕，非等向性蝕刻基材以形成溝渠，並沉積二氧化矽層 於溝渠中，最後再移除氮化矽層以形成電晶體之間的隔離功 會b 。 經濟部智慧財產局員工消費合作社印製 在這基本的隔離完成後，先製作第一氧化層12於 基材10上，舉例來說，形成一穿隧二氧化矽層（Tox)12，其 厚度非常薄，僅有約50 - 300埃之間，並可在含氧的環境下 以熱氧化法於750°C至1000°C中形成。此穿隧氧化層12亦 可以利用傳統之化學氣相沈積法（CVD)形成。接著在穿隧氧 化層1 2上覆蓋第一多晶矽層1 3，舉例來說，可以利用傳統 之化學氣相沈積法形成，同時亦可利用其他已知方法，例如 摻雜多晶矽，此第一多晶矽層13的厚度大約只有500- 1000 埃。多晶矽層在快閃記憶體之中的一個重要功用是儲存電 荷，一般來說儲存的電荷越多，快閃記憶體的表現越好。而 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) 492142 , 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 此一多晶砂層因爲未與其他的導體連接，而稱爲懸浮聞極 (FloatingGate)。在第一多晶矽層13的上面再沈積上第一 氮化砂層1 4，因爲氮化矽有不容易被氧滲透的優點，可以 做爲保護層用。例如，上述之第一^氮化砂層1 4可以化學氣 相沈積法形成，其厚度約爲1000 -2000埃。隨後將該第一氮 化石夕層1 4、第一多晶砂層1 3及第一氧化層1 2，以傳統的微 影與非等向性蝕刻技術定義出數個快閃記憶體的主動區 域，留下如第一圖上方部份的情況。 完成後，再以剛剛完成的閘極區爲罩幕，植入汲極 /源極，在較佳實施例中，於基材丨0上分別以離子植入摻雜 離子進入基板之中，以形成埋入式汲極（Buried Drain) 15 及大角度斜向汲極（LATID) 16，用以防止短通道效應，同時 也是做爲汲極/源極之所在，如第二圖中的斜線部份。其中 埋入式汲極之植入能量範圍可以約爲40至80Kev，植入劑 量可以約爲lx 1015至5x 1015lons/cm2;而大角度斜向汲極 之植入能量範圍可以約爲40至lOOKev ，植入劑量可以約 爲 5x 1012 至 lx 1014i〇ns/cm2。 本發明之第三圖表示了延續第二圖的製程，在完成了植 入汲極/源極的程序之後，再覆蓋上第二氧化層1 7，舉例來 說，該第二氧化層17可以爲高密度電漿化學氣相沈積法形 成（HDPCVD)，其形成之氧化層厚度約爲1 500 - 3500埃。然後 需要移除一部份剛剛覆蓋上去的氧化層1 7，例如使用傳統 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公s ) ftp r kp J— MM MB MMV I MM I · ϋ ·1 ϋ I ϋ-」a n ϋ I. n n ϋ n I ^ -tp (請先閱讀背面之注意事項再填寫本頁) 492142 A7 B7 五、發明説明（） 濕式蝕刻的方法移除約300 - 1 550埃的HDP氧化層17，其目 的是使得第一氮化矽層1 4上側的邊緣部位暴露在外。 (請先閲讀背面之注意事項再填寫本頁) 移除的程序完成之後，繼續在上方又沈積另一層第二氮 化政遮蓋層18(Cap Layer)，例如厚度約爲150至600埃， 新沈積上的第二氮化矽遮蓋層18可以與暴露出角落的第一 氮化矽層1 4互相接觸，藉由第一層氮化矽層1 4與第二氮化 矽覆蓋層18之間的接觸以保護埋入之汲極與源極上之氧化 物1 7 A。接下來移除在結構中最頂層、最突出的一部份，例 如以化學機械硏磨的方式稍加硏磨，移除之厚度約爲300至 1 500埃，且移除的部份包括在最頂層的氮化矽及部份的HDP 氧化層。所完成後的示意圖請參考第三圖，在移除了部份第 二氮化矽遮蓋層1 8之後，同時也暴露出了部份的HDP氧化 層17,而埋入之汲極與源極上之氧化物17A此時被第一及 第二氮化矽層保護住。 經濟部智慧財產局員工消費合作社印製 在第四圖中所顯示的結構爲移除所有的氮化矽極其上 之硏磨殘留之氧化層後，並且繼續分別沈積、圖案化及蝕刻 第二多晶矽層19的結果，該第二多晶矽層19之形成厚度約 爲3 00至1000埃。第三圖結構中將第一氮化矽層上方的HDP 氧化物首先被移除後，第一氮化矽層14及第二氮化矽層18 亦可以被同時蝕刻，例如以濕式蝕刻的方式，同時亦將使第 一氮化矽層上方的HDP氧化物也會隨著一起被移除。隨後， 在餘留下之第一多晶矽層13及欲留下的HDP氧化層17上再 11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 492142 A7 ______B7__ 五、發明説明（） 次沈積第二多晶矽層1 9，以本實施例中沈積的方式爲利用 傳統的化學氣相沈積法，第二多晶矽層1 9係用以增加原有 多晶矽層厚度及電容面積，以容納更多電荷並增加積體電路 的表現。在此提出說明的是第二多晶矽層1 9並非絕對需 要，而其應用係因爲此一具體實施例爲針對於製作快閃記憶 體，所以需要擁有較好表現的電性表現。 在第二多晶矽層19沈積之後會與原有的第一多晶矽層 13結合，形成共同的多晶矽層，而此時兩層之間的介面不 復存在。之後新形成的多晶矽層也還要藉由經過微影及鈾刻 的步驟，以移除在STI11上方及HDP氧化層17上方的多晶 矽層材料，以食義出達成如第四圖所表示的結構。在微影過 程之圖案化的要求中，在此階段即已經定義了各部位的大小 尺寸。 在完成第四圖的結構之後’再分別沈積上一介電材料層 20，例如二氧化矽/氮化矽/二氧化矽（ΟΝΟ)、一第三多晶矽 層21及一硬罩幕層（Hard Mask) 22 ’例如矽化鎢或氧化層。 0N0層20在此爲做爲絕緣層，亦可以其他材料取代’例如 氮化矽/二氧化矽（NO)。二氧化矽/氧化氮/二氧化矽（0Ν0) 的生成可以利用氮離子植入到前述之多晶矽層上。在一較佳 實施例中，可利用氮氣或氧化氮加以處理以生長氧化物，進 而控制二氧化矽/氧化氮/二氧化矽（0Ν0)之底層氧化物厚 度。而第三多晶砂層21及硬罩幕層22的生成依然可以使用 12 本紙張尺度適用中國國家標準（CNS ) Α4規格(210X297公釐） - - Γ - :·1· :rI 111 - - --- -= --- ! , (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 492142 A7 _____B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 化學氣相沈積法來沈積，而兩者之厚度分別約爲700至2000 埃及約爲1 000至30000埃。亦可以在硬罩幕層22之上方更 覆蓋其他層的罩幕，例如介電抗反射覆蓋（DARC )或其他材 料，其目的是使以下的步驟中微影及蝕刻的效果達到更好。 將硬罩幕層22圖案化，以定義出記憶體的區域結構 後，進行在較佳實施例中自行對準金屬氧化半導體（SAMOS) 的蝕刻。參考第五A圖，利用已經圖案化的硬罩幕層22， 使用乾式蝕刻方式依序移除了第三多晶矽層21罩幕及、介 電材料0N0層20、第二多晶矽層19及第一多晶矽層Π。蝕 刻的製程一直至HDP氧化層1 7及基材1 0表面的穿隧氧化層 1 2爲止。 繼續請參考第五Α圖，接下來再次以HDP氧化層1 7Α及 硬罩幕層22作爲罩幕，定義出雙晶結構之間的凹陷區域。 在使用針對矽化物材料的配方做蝕刻，在本發明之較佳實施 例中以CF4做乾式飩刻，使得蝕刻的部位穿透了穿隧氧化層 12,而在半導體矽基材10上部份區域，形成了深度約爲500 埃- 1 500埃的凹陷24，該凹陷24即爲本發明之主要特徵之 一，做爲隔離的功用。 經濟部智慧財產局員工消費合作社印製 在本發明中可以於SAMOS蝕刻之後，再次更換另一種 針對氧化層蝕刻的配方，以乾式飩刻爲主，在有硬罩幕層 22的情況下做非等向性蝕刻，蝕刻移除剩餘HDP氧化層1 7 的部份，完成後的結構即類似於第五B圖所表現之示意圖。 13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 492142 A7 B7 五、發明説明（） (秦先閱讀背面之注意事項再填寫本頁) 在第五A、B圖之立體圖結構可以比照第六圖中之俯視圖， 依照AA截面及BB截面之結構，在第五A、B圖及第六圖中 的AA截面因爲有硬罩幕層22，所以沒有蝕刻到硬罩幕層2211 Shallow trench isolation area / STI 12 First oxide layer / tunneling oxide layer (Tox) 13 First polycrystalline silicon layer 14 First silicon nitride layer 15 Buried drain (BD) 16 Wide-angle oblique drain (LATID) 17 Second oxide layer / high-density plasma oxide layer (HDP) 18 Second silicon nitride layer covering 19 Second polycrystalline silicon layer 20 Dielectric material layer / ON0 21 Third polycrystalline silicon layer 22 Mask Layer (tungsten silicide / silicon dioxide) 23 protective layer (TE0S) 24 depression 25 gap wall 26 dielectric material layer 27 contact window 28 silicon nitride layer Detailed description of the invention = Printed by the Department of Economic Affairs Reveal a new type of isolation process. In the present invention, the isolation is formed by a new manufacturing method. The isolation can replace the surrounding insulating area of the contact window to prevent a short circuit generated when the misalignment of the position of the contact window occurs, thereby saving the traditional design. A larger margin design is used in the rule, so that the transistor can be more compactly designed. And in the subsequent boarderless contact window manufacturing process, the isolation formed by the present invention 8 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 492142 A7 ___ B7 _ 5. The invention description () can also be Avoid newly generated self-aligned titanium silicide short circuits. (Please read the precautions on the back before filling in this page) Figures 2 to 9B show specific examples of the twm-cell architecture of the present invention used on non-volatile flash memory billion . Please refer to the second figure, first provide a single crystal semiconductor substrate 10 with a <100> crystal plane, and then use conventional manufacturing methods to form the isolation. In a preferred embodiment, a shallow trench isolation region 11 is formed. (Shallow Trench Isolation, STI) In the semiconductor substrate, the depth of the trench is about 3 500-4000 Angstroms, which is used as the isolation between the active regions. To avoid interference with each other during operation. This STI process can use a silicon nitride layer / pad oxide layer as a mask, anisotropically etch the substrate to form a trench, and deposit a silicon dioxide layer in the trench. Finally, the silicon nitride layer is removed to form a transistor. The isolation function will be b. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs After this basic isolation is completed, a first oxide layer 12 is first formed on the substrate 10, for example, a tunneling silicon dioxide layer (Tox) 12 is formed, and its thickness is Very thin, only between about 50-300 Angstroms, and can be formed at 750 ° C to 1000 ° C by thermal oxidation in an oxygen-containing environment. The tunnel oxide layer 12 can also be formed by a conventional chemical vapor deposition (CVD) method. Then, a first polycrystalline silicon layer 13 is covered on the tunneling oxide layer 12. For example, the first polycrystalline silicon layer 13 can be formed by using a conventional chemical vapor deposition method, and other known methods such as doped polycrystalline silicon can also be used. The thickness of a polycrystalline silicon layer 13 is only about 500-1000 Angstroms. An important function of the polycrystalline silicon layer in flash memory is to store charge. Generally speaking, the more charge stored, the better the performance of the flash memory. 9 paper sizes are in accordance with Chinese National Standard (CNS) A4 specifications (210X297 mm) 492142, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () This polycrystalline sand layer is not connected with other conductors The connection is called a floating gate (FloatingGate). A first nitrided sand layer 14 is deposited on top of the first polycrystalline silicon layer 13, because silicon nitride has the advantage of not being easily penetrated by oxygen, and can be used as a protective layer. For example, the above-mentioned first nitrided sand layer 14 can be formed by a chemical vapor deposition method and has a thickness of about 1000 to 2000 angstroms. Subsequently, the first nitrided stone layer 14, the first polycrystalline sand layer 13 and the first oxidized layer 12 are used to define the active areas of several flash memories by conventional lithography and anisotropic etching techniques. , Leaving the situation as in the upper part of the first picture. After the completion, the drain / source is implanted with the gate area just completed. In a preferred embodiment, the substrate ions are implanted with ions and doped ions into the substrate. Buried Drain 15 and LATID 16 are used to prevent short-channel effects and also serve as the drain / source, as shown in the diagonal line in the second figure Serving. The implantation energy range of the buried drain can be about 40 to 80 Kev, and the implantation dose can be about 1x 1015 to 5x 1015lons / cm2; and the implantation energy range of the large-angle oblique drain can be about 40 to 10OKev The implantation dose can be about 5x 1012 to 1x 1014 ions / cm2. The third diagram of the present invention shows the process of continuing the second diagram. After completing the process of implanting the drain / source, the second oxide layer 17 is covered. For example, the second oxide layer 17 may It is formed by high-density plasma chemical vapor deposition (HDPCVD), and the thickness of the formed oxide layer is about 1 500-3500 angstroms. Then you need to remove a part of the oxide layer 1 7 that has just been covered. For example, the traditional 10 paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public s). Ftp r kp J— MM MB MMV I MM I · Ϋ · 1 ϋ I ϋ- 」an ϋ I. nn ϋ n I ^ -tp (Please read the precautions on the back before filling out this page) 492142 A7 B7 5. Description of the invention () Wet etching method removes about The HDP oxide layer 17 of 300-1 550 angstroms is intended to expose the edge portion of the upper side of the first silicon nitride layer 14 to the outside. (Please read the precautions on the back before filling this page) After the removal process is completed, continue to deposit another layer of second nitride capping layer 18 (Cap Layer) on the top, for example, the thickness is about 150 to 600 Angstroms, new The deposited second silicon nitride masking layer 18 may be in contact with the first silicon nitride layer 14 with the corners exposed, and between the first silicon nitride layer 14 and the second silicon nitride cover layer 18 Contact to protect the buried drain and source oxide 17 A. Next, remove the topmost and most prominent part of the structure, for example, by honing it by chemical mechanical honing. The thickness of the removal is about 300 to 1500 angstroms, and the removed part is included in The top silicon nitride and part of the HDP oxide layer. Please refer to the third diagram for the completed diagram. After removing part of the second silicon nitride masking layer 18, part of the HDP oxide layer 17 is also exposed, and the buried drain and source are exposed. The oxide 17A is now protected by the first and second silicon nitride layers. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the structure shown in the fourth figure after removing all the oxide residues of the silicon nitride and the honing residue, and then continued to deposit, pattern and etch the second most. As a result of the crystalline silicon layer 19, the second polycrystalline silicon layer 19 is formed to a thickness of about 300 to 1000 angstroms. In the structure of the third figure, after the HDP oxide above the first silicon nitride layer is first removed, the first silicon nitride layer 14 and the second silicon nitride layer 18 can also be etched simultaneously, for example, by wet etching. At the same time, the HDP oxide above the first silicon nitride layer will also be removed along with it. Subsequently, on the remaining first polycrystalline silicon layer 13 and the HDP oxide layer 17 to be left, the paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) 492142 A7 ______B7__ 5. Description of the invention () Second deposition of the second polycrystalline silicon layer 19, using the traditional chemical vapor deposition method for the deposition method in this embodiment, the second polycrystalline silicon layer 19 is used to increase the thickness and capacitance of the original polycrystalline silicon layer Area to hold more charge and increase the performance of the integrated circuit. It is proposed here that the second polycrystalline silicon layer 19 is not absolutely necessary, and its application is because the specific embodiment is directed to making flash memory, so it needs to have a good electrical performance. After the second polycrystalline silicon layer 19 is deposited, it will be combined with the original first polycrystalline silicon layer 13 to form a common polycrystalline silicon layer. At this time, the interface between the two layers no longer exists. Afterwards, the newly formed polycrystalline silicon layer also needs to pass through the steps of lithography and uranium etching to remove the polycrystalline silicon layer material above the STI11 and the HDP oxide layer 17 to achieve the structure shown in the fourth figure. . In the patterning requirements of the lithography process, the size of each part has been defined at this stage. After completing the structure of the fourth figure, a layer of dielectric material 20 is deposited, such as silicon dioxide / silicon nitride / silicon dioxide (ONO), a third polycrystalline silicon layer 21, and a hard mask layer. (Hard Mask) 22 'such as tungsten silicide or oxide layer. The 0N0 layer 20 is used as an insulating layer, and may be replaced with other materials, such as silicon nitride / silicon dioxide (NO). The formation of silicon dioxide / nitrogen oxide / silicon dioxide (ON0) can be implanted on the aforementioned polycrystalline silicon layer using nitrogen ions. In a preferred embodiment, nitrogen or nitrogen oxide can be used to grow oxides to control the thickness of the underlying oxide of silicon dioxide / nitrogen oxide / silicon dioxide (ON0). The third polycrystalline sand layer 21 and the hard cover curtain layer 22 can still be used for the production of 12 paper standards applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm)--Γ-: · 1 ·: rI 111--- --= ---!, (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives printed 492142 A7 _____B7 V. Description of the invention () (Please read the precautions on the back first Fill in this page again) Chemical vapor deposition method, and the thickness of the two is about 700 to 2000, respectively, Egypt is about 1,000 to 30,000 Angstroms. It is also possible to cover other layers of masks, such as dielectric anti-reflection cover (DARC) or other materials, on top of the hard mask layer 22, the purpose of which is to make the effect of lithography and etching better in the following steps. After patterning the hard mask layer 22 to define the area structure of the memory, the self-aligned metal oxide semiconductor (SAMOS) etching is performed in a preferred embodiment. Referring to FIG. 5A, using the patterned hard mask layer 22, the third polycrystalline silicon layer 21 mask, the dielectric material ON0 layer 20, and the second polycrystalline silicon layer were sequentially removed by dry etching. 19 and the first polycrystalline silicon layer Π. The etching process continues until the HDP oxide layer 17 and the tunneling oxide layer 12 on the surface of the substrate 10 are formed. Continue to refer to the fifth A figure, and then use the HDP oxide layer 17A and the hard mask layer 22 as masks again to define the recessed areas between the dual crystal structures. In the use of a silicide-based formulation for etching, in the preferred embodiment of the present invention, CF4 is used for dry etching so that the etched portion penetrates the tunneling oxide layer 12 and a portion on the semiconductor silicon substrate 10 In the area, a depression 24 having a depth of about 500 Angstroms to about 1,500 Angstroms is formed. The depression 24 is one of the main features of the present invention and serves as an isolation function. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the present invention, another formula for etching the oxide layer can be replaced again after SAMOS etching, mainly dry-etching, and it can be done with a hard cover layer 22 Isotropic etching removes the remaining HDP oxide layer 17 by etching, and the structure after completion is similar to the schematic diagram shown in Figure 5B. 13 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 492142 A7 B7 V. Description of the invention () (Qin Xian read the notes on the back before filling this page) The three-dimensional structure of the fifth A and B It can be compared with the top view in the sixth figure, and according to the structure of the AA section and the BB section, the AA section in the fifth A, B, and the sixth figure is not etched to the hard mask layer 22 because it has the hard mask layer 22
下方的結構，因此形成如第七圖的電晶體結構；在第五AB % 圖及第六圖中之BB截面因爲沒有硬罩幕層22的保護，所以 第三多晶矽層21、ΟΝΟ層20及第二多晶矽層19與第一多晶 矽層13的組合多晶矽層相繼被蝕刻，跟著矽基材10又以 HDP氧化層17爲罩幕被鈾刻成凹陷之結構，在本發明之一 實施例中，接下來可以將HDP氧化層1 7蝕刻移除。 在形成自行對準之凹陷24,下一個部分應該就要進行 形成間隙壁25的製程。先沉積一第二介電材料層28，例如 以傳統低壓化學氣相沉積法沈積。沈積的部份不僅只有在自 行對準之凹陷24之中，並且也包括在半導體基材.10及記憶 體晶胞隔離11與硬罩幕層22之上。隨後對TE0S保護層23 進行非等向性蝕刻，回鈾後產生了間隙壁25，而凹陷區域 24仍被介電材料28塡滿，參考第八圖。 經濟部智慧財產局員工消費合作社印製 在本發明中之另一實施例亦包含在凹陷24形成後，暫 不立即的移除HDP層1 7。如同上述形成間隙壁的製程，先 沈積一層第二介電材料層28,再施予回鈾作業。在回蝕作 業進行的同時，上述殘留之HDP亦會被同時的移除。 參考第六圖爲依照本發明之一實施例的俯視圖。於此圖 中，標號11爲淺溝渠隔離，硬罩幕層22則形成主動區的雙 14 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇Χ297公釐） 492142 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 晶結構。於此例中可以了解爲適應快閃記憶體的功能，設計 隔離可以存在的區域。在沒有罩幕層22的部份中，傳統上 並無隔離區的設計，但於本發明中，即可利用凹陷區域24 的部分形成隔離區。 於本發明之一具體實施例中，可在之後進行自行對準矽 化物（Se 1 f _ A1 i gned S i 1 i c i de )製程。舉例來說，使用傳統 的方式分別形成一金屬層（未以圖面表示），例如鈦金屬，再 加以熱處理之後與電晶體晶胞上的矽反應形成矽化鈦。晶胞 之間所形成的結構即爲第九A圖與第九B圖的表示。在第九 A圖所代表的相當於第六圖中X軸沿BB截面的剖面圖，第 九B圖所代表的相當於第六圖中Y軸沿DD截面的剖面圖， 兩圖之間箭頭的部份表示對稱的部位。因爲有罩幕的阻隔， 箭頭所指的是由不同方向觀察的同一個區域。本發明其中之 一優點爲，在自行對準製程中，形成導體的矽化鈦因爲有凹 陷區域24作爲隔離，所以不會造成晶胞之間的短路。 經濟部智慧財產局員工消費合作社印製 在本發明之另一具體實施例中，MOS電晶體完成之後可 以接著進行無邊（Broader less)接觸窗的製程。例如，先形 成一薄氮化砍層後在氮化砂層28上’再加上一層氧化砂介 電層，隨後蝕刻欲開接接觸窗處之介電層，以做爲接觸窗之 用，在鈾刻過程中，因氮化矽與氧化矽具有高選擇性比，所 以可以停留再氧化矽上之後再轉換蝕刻氣體，將氮化矽移除 而形成接觸窗。本發明之另一優點如前所述，以本發明所生 15 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 492142 A7 B7 五、發明説明（） 成的隔離亦可做爲取代傳統設計法則中接觸窗旁預留邊界 (margin)的功能。例如參考第六圖之BB截面與DD截面及其 相對之第九A圖與第九B圖，接觸窗27即使有對準失當的 情況，但是仍不會有短路的缺陷。藉由在晶胞中加入隔離以 減小邊界所占的面積，可以達到增加積體電路積集度的效 果。 本發明以較佳之具體實施例敘述如上，僅用於藉以幫助 了解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，凡其它未脫離本發明所 揭示之精神下，所完成之些許更動潤飾及等效之改變或 修飾，例如再第五A圖中，在硬罩幕層22上更可加上光阻 罩幕層以避免過度蝕刻的情形發生。其專利保護範圍當視 包含在下述之申請專利範圍及其等同領域而定。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）The lower structure thus forms the transistor structure as shown in the seventh figure; the cross section BB in the fifth AB% figure and the sixth figure is not protected by the hard cover curtain layer 22, so the third polycrystalline silicon layer 21, ONO layer 20 and the second polycrystalline silicon layer 19 and the combination of the first polycrystalline silicon layer 13 and the polycrystalline silicon layer are successively etched, followed by the silicon substrate 10 and the HDP oxide layer 17 is used as a mask to be carved into a recessed structure by uranium. In one embodiment, the HDP oxide layer 17 can be removed by etching. After forming the self-aligned depression 24, the next part should be subjected to the process of forming the partition wall 25. A second dielectric material layer 28 is deposited first, such as by conventional low pressure chemical vapor deposition. The deposited part is not only in the self-aligned recess 24, but also in the semiconductor substrate. 10 and the memory cell isolation 11 and the hard mask layer 22. Subsequently, the TEOS protective layer 23 is anisotropically etched, and a spacer 25 is generated after the uranium is returned, and the recessed area 24 is still filled with the dielectric material 28, refer to the eighth figure. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Another embodiment of the present invention also includes that the HDP layer 17 is not removed immediately after the depression 24 is formed. As in the process for forming a spacer, as described above, a second layer of dielectric material 28 is deposited and then applied to the uranium return operation. At the same time as the etch-back operation is performed, the above-mentioned residual HDP will also be removed at the same time. Reference to the sixth figure is a top view according to an embodiment of the present invention. In this figure, the reference number 11 is shallow trench isolation, and the hard cover curtain layer 22 forms the double 14 of the active area. The paper size applies to the Chinese National Standard (CNS) A4 specification (21〇 × 297 mm) 492142 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page). In this example, you can understand that in order to adapt to the function of the flash memory, the design can isolate the area that can exist. In the part without the cover layer 22, there is no conventional design of the isolation region, but in the present invention, the isolation region can be formed by using the recessed region 24 portion. In a specific embodiment of the present invention, a self-aligned silicide (Se 1 f _ A1 i gned S i 1 i c i de) process may be performed later. For example, a traditional method is used to form a metal layer (not shown in the figure), such as titanium, and then heat treatment with silicon on the unit cell to form titanium silicide. The structure formed between the unit cells is the representation of Figures 9A and 9B. A cross-sectional view corresponding to the X-axis along the BB cross section represented by the ninth graph in FIG. The part indicates the symmetrical part. Because of the barrier, the arrows point to the same area viewed from different directions. One of the advantages of the present invention is that in the self-alignment process, the titanium silicide forming the conductor does not cause a short circuit between the cells because the recessed area 24 is used as an isolation. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In another specific embodiment of the present invention, after the MOS transistor is completed, the process of a Broader less contact window can be performed. For example, first form a thin nitride cut layer and then add a sand oxide dielectric layer on the nitrided sand layer 28, and then etch the dielectric layer at the contact window to be used as the contact window. During the uranium etching process, because silicon nitride and silicon oxide have a high selectivity ratio, it is possible to stay on the silicon oxide and then switch the etching gas to remove the silicon nitride to form a contact window. Another advantage of the present invention is as described above. The 15 paper sizes produced by the present invention are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 492142 A7 B7. 5. The isolation of the invention () can also be used as It replaces the function of reserving a margin by the contact window in the traditional design rules. For example, referring to the BB cross section and the DD cross section of the sixth diagram and the ninth diagrams A and N of the opposite diagrams, even if the contact window 27 is misaligned, there is still no short circuit defect. By adding isolation to the unit cell to reduce the area occupied by the boundary, the effect of increasing the integration degree of the integrated circuit can be achieved. The present invention is described in the above specific embodiments. It is only used to help understand the implementation of the present invention, and is not intended to limit the spirit of the present invention. After a person skilled in the art understands the spirit of the present invention, others who have not departed from it Under the spirit disclosed by the invention, a few changes and retouching and equivalent changes or modifications are completed. For example, as shown in Figure 5A, a photoresist mask layer can be added to the hard mask layer 22 to avoid excessive etching. The situation happened. The scope of patent protection shall depend on the scope of patent applications covered below and the equivalent fields. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm)