JPH0774274A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the voltage of gate insulation film and to stabilize the characteristics of an element being formed using the gate insulation film by preventing the gate insulation film from thinning at the edge part of an isolation region when the gate insulation films for the isolation region and a MOS transistor are formed sequentially. CONSTITUTION:The method for fabricating a semiconductor device comprises a step for forming a first insulation film 22 and a deposition film 23 for mask sequentially on a semiconductor substrate 21, a step for anisotropically etching the deposition film, the first insulation film, and the semiconductor substrate sequentially to make a groove in the semiconductor substrate, a step for filling the groove with a second insulation film 27 up to the upper face of the semiconductor substrate, a step for subjecting the surface of the semiconductor substrate to thermal oxidation using the deposition film as a mask thus partially forming a reoxidation film 28 below the second insulation film and the deposition film, a step for removing the deposition film and the first insulation film to form a gate insulation film 30 on the element forming region of the semiconductor substrate, and a step for forming a gate electrode 31 on the gate insulation film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a region element isolation region for electrically isolating elements from each other, for example, an array of nonvolatile memory cells having a stacked gate electrode structure. Applied to the manufacture of non-volatile memory having.

[0002]

2. Description of the Related Art An example of a conventional semiconductor device structure and a method of manufacturing the same will be described with reference to FIGS. First, as shown in FIG. 3A, the insulating film 12 is formed on the surface of the semiconductor substrate 11, and the nitride film 13 is further deposited. After that, a predetermined resist pattern 14 is formed by a photolithography process, and the nitride film 13 is etched using the resist pattern 14 as a mask.

Next, after removing the resist pattern 14, as shown in FIG. 3B, thermal oxidation is performed to form an element isolation oxide film 15, and then the nitride film 13 is formed.
By removing the insulating film 12 and the insulating film 12, an element isolation region and an element formation planned region are obtained as shown in FIG.

Thereafter, as shown in FIG. 3D, a gate oxide film 16 for a MOS transistor is formed on the surface of the substrate in a region where elements are to be formed. By the way, the element isolation oxide film 15 has a thickness of 700 to 800 nm in order to secure its withstand voltage.
Therefore, it is necessary to oxidize for a long time when forming the oxide film 15.

However, at this time, as shown in FIG. 3B, lateral oxidation under the nitride film 13 also occurs, the element isolation region expands, and miniaturization becomes difficult. At this time, the edge portion of the nitride film 13 rises and the oxide film 15 for element isolation is formed.
As shown in FIG. 3 (b), the edge portion has a sharp edge portion.

As a result, as shown in FIG. 3 (d),
When the gate oxide film 16 for the MOS transistor is formed on the substrate surface in the device formation region, the supply of the oxidizing agent is reduced at the edge portion of the oxide film 15, and the gate oxide film 16 is thinned at the edge portion of the oxide film 15. Will turn into.

When the gate oxide film 16 is thinned in this way, the breakdown voltage of the gate oxide film 16 deteriorates, and
When an EEPROM (electrically erasable / rewritable memory) cell having a laminated gate electrode structure is formed on the gate oxide film 16 later, there arises a problem that the write / erase characteristics of the memory cell deteriorate.

[0008]

As described above, according to the conventional method of manufacturing a semiconductor device, when the element isolation region is formed,
The gate oxide film becomes thinner at the edge of the element isolation region, the breakdown voltage of the gate oxide film deteriorates, and the write / erase characteristics of the cell are improved when an EEPROM cell having a stacked gate electrode structure is formed on the gate oxide film. There was a problem of deterioration.

The present invention has been made to solve the above-mentioned problems, and when the element isolation region and the gate insulating film for the MOS transistor are sequentially formed, the gate insulating film at the edge portion of the element isolation region is thinned. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent the breakdown voltage, improve the breakdown voltage of the gate insulating film, and stabilize the characteristics of an element in which a gate electrode is formed on the gate insulating film.

[0010]

A method of manufacturing a semiconductor device according to the present invention comprises a step of sequentially forming a first insulating film and a deposited film for a mask on a semiconductor substrate, the deposited film and the first insulating film. And a semiconductor substrate are sequentially processed by anisotropic etching to form a groove in the semiconductor substrate, and a step of embedding a second insulating film in the groove up to the upper surface of the semiconductor substrate.
Thermally oxidizing the surface of the semiconductor substrate by using the deposited film as a mask to form a re-oxidized film on the second insulating film and a part of the lower portion of the deposited film; and the deposited film and the first insulating film. Are removed, and the surface of the semiconductor substrate is thermally oxidized to form a gate insulating film on the device formation planned region; and a step of forming a gate electrode on the gate insulating film. .

[0011]

Since the element isolation region is formed by embedding the insulating film in the groove formed in the predetermined region of the semiconductor substrate and then performing thermal oxidation, the amount of thermal oxidation is ensured while ensuring the film thickness of the element isolation region. It becomes possible to reduce. As a result, the shape of the edge portion of the element isolation oxide film becomes gentle, and it is possible to suppress the thinning of the gate insulating film for the MOS transistor formed on the substrate surface in the element formation planned region in a later step. Therefore, it becomes possible to improve the breakdown voltage of the gate insulating film and stabilize the characteristics of the element in which the gate electrode is formed on the gate insulating film.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 (a)-(d) and 2 (a)-
FIG. 3D is a sectional view showing a substrate structure in a process of forming an element isolation region when the present invention is applied to an EEPROM manufacturing method.

First, as shown in FIG. 1A, a thermal oxide film 22 having a thickness of 30 nm is formed on a silicon substrate 21, and a mask deposition film, such as a nitride film, is formed by a low pressure CVD (chemical vapor deposition) method. The film 23 is deposited to a thickness of about 150 nm.

Next, as shown in FIG. 1B, a predetermined resist pattern 24 is formed on the nitride film 23 by a photolithography process. Next, as shown in FIG. 1C, the nitride film 23, the thermal oxide film 22, and the silicon substrate 21 are sequentially etched by anisotropic etching using the resist pattern 24 as a mask, so that the silicon substrate 21 has a depth of 0. A groove 25 of about 0.5 μm is formed.

Next, after removing the resist pattern 24, as shown in FIG. 1D, field ion implantation is performed using the nitride film 23 as a mask to form an inversion prevention layer 26 just below the bottom surface of the groove 25. To do.

Next, as shown in FIG. 2A, the reduced pressure CV
An insulating film is formed on the entire surface of the substrate to a thickness of, for example, about 500 nm by the D method, and then the insulating film is etched to the upper surface of the silicon substrate 21 by anisotropic etching. As a result, the inside of the groove 25 is filled with the insulating film 27.

Next, as shown in FIG. 2B, the upper surface of the insulating film 27 is re-oxidized by thermal oxidation to form a re-oxidized film 28 of about 200 nm. At this time, although oxidation also progresses under the nitride film 23, since the thickness of the oxide film 27 is about 200 nm, the amount of oxidation under the nitride film 23 is small, and the shape of the edge portion of the oxide film 27 becomes gentle.

Next, after the nitride film 23 and the thermal oxide film 22 are removed, as shown in FIG. 2 (c), channel ion implantation is performed in the element formation planned region as needed. That is, an ion implantation layer for controlling the threshold value is formed in the channel region 29 of the transistor that will be formed in a later step.

After that, as shown in FIG. 2D, an EEPROM cell having a laminated gate electrode structure is formed by a normal process. That is, in FIG. 2D, 30 is the first gate oxide film formed on the surface of the substrate in the device formation planned region, 3
Reference numeral 1 is a first gate electrode (floating gate electrode of an EEPROM cell) made of polysilicon formed on the first gate oxide film 30, and 32 is a second gate insulating film formed on the first gate electrode 31. 33 is a second gate electrode (E) made of polysilicon formed on the second gate insulating film 32.
Control gate electrode of the EPROM cell), and EEPRO
Part of a word line commonly connected to cells in the same row of the M cell array is formed.

The word line 33 may have a refractory metal or its silicide layer formed on polysilicon in order to reduce the resistance. Similarly, in the floating gate electrode 31, a refractory metal or a silicide layer thereof may be formed on polysilicon.

That is, in the method of forming the EEPROM cell of the above embodiment, the first insulating film (thermal oxide film) 22 and the nitride film 23 are formed on the silicon substrate 21, and the resist pattern 24 is formed.
Using the mask as a mask, the nitride film 23, the thermal oxide film 22, and the silicon substrate 21 are sequentially etched to form a groove 25 in a predetermined region of the silicon substrate 21. Then, after removing the resist pattern 24, the second insulating film 2 is formed on the entire surface.
7 is deposited and the second insulating film 27 is formed by anisotropic etching.
The insulating film 27 is embedded in the groove by etching until the upper surface of the above becomes the upper surface of the semiconductor substrate. Next, thermal oxidation is performed using the nitride film 23 as a mask to form a re-oxidized film 28 on the surface of the second insulating film 27 to form an element isolation region.

According to such a method, it is possible to reduce the amount of thermal oxidation while securing the film thickness of the oxide film for element isolation (27, 28), and therefore, as shown in FIG. 2 (b). To
The edge portion of the element isolation oxide film (27, 28) has a gradual shape to prevent the gate oxide film 30 for the MOS transistor formed on the substrate surface in the element formation planned region from being thinned in a later step. You can Therefore, it becomes possible to improve the breakdown voltage of the gate oxide film 30.
Stable write / erase characteristics of the M cell can be obtained.

[0023]

As described above, according to the method of manufacturing a semiconductor device of the present invention, when the gate insulating film for the MOS transistor is sequentially formed on the substrate surface of the element isolation region and the element formation planned region, the element isolation region is formed. Prevents thinning of the gate insulating film at the edge of the gate, improving the breakdown voltage of the gate insulating film,
The characteristics of the element formed using the gate insulating film can be stabilized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a substrate structure in a part of an element isolation region forming step when the present invention is applied to an EEPROM manufacturing method.

FIG. 2 is a cross-sectional view showing a substrate structure in a step that follows the step of FIG.

FIG. 3 is a sectional view showing a substrate structure in a conventional element isolation region forming step.

[Explanation of reference numerals] 21 ... Silicon substrate, 22 ... Thermal oxide film, 23 ... Nitride film,
24 ... Resist pattern, 25 ... Grooves dug in semiconductor substrate, 26 ... Element isolation region inversion prevention layer, 27 ... Buried insulating film, 28 ... Reoxidation film, 29 ... Channel region, 30 ... First gate oxide film, 31 ... first gate electrode (floating gate electrode), 32 ... second gate insulating film, 33 ... second gate electrode (control gate electrode).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/76

Claims (2)

[Claims] 1. A step of sequentially forming a first insulating film and a deposited film for a mask on a semiconductor substrate; and a step of sequentially processing the deposited film, the first insulating film and the semiconductor substrate by anisotropic etching, Forming a groove in the semiconductor substrate; embedding a second insulating film in the groove up to the upper surface of the semiconductor substrate; and thermally oxidizing the surface of the semiconductor substrate using the deposited film as a mask to form the second insulating film. Forming a re-oxidized film on the film and a part below the deposited film, removing the deposited film and the first insulating film, and thermally oxidizing the surface of the semiconductor substrate to form an element formation region A method of manufacturing a semiconductor device, comprising: a step of forming a gate insulating film; and a step of forming a gate electrode on the gate insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode has a laminated polysilicon gate structure.