KR100324339B1 - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR100324339B1 KR100324339B1 KR1020000010066A KR20000010066A KR100324339B1 KR 100324339 B1 KR100324339 B1 KR 100324339B1 KR 1020000010066 A KR1020000010066 A KR 1020000010066A KR 20000010066 A KR20000010066 A KR 20000010066A KR 100324339 B1 KR100324339 B1 KR 100324339B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상부에 버퍼산화막을 형성한 다음 문턱전압조절을 위한 불순물이온을 주입하는 공정과; 상기 버퍼산화막을 제거한 다음 게이트산화막과 폴리실리콘을 순차적으로 형성하고, 폴리실리콘 상부에 제1감광막을 도포, 노광 및 현상하여 소자간 격리영역이 형성될 영역의 폴리실리콘이 노출되도록 제1감광막 패턴을 형성하는 공정과; 상기 제1감광막 패턴을 적용하여 폴리실리콘과 게이트산화막을 식각하고, 계속해서 노출되는 반도체기판을 소정의 깊이로 식각되도록 과도식각하여 얕은 트렌치를 형성한 다음 제1감광막 패턴을 제거하는 공정과; 상기 얕은 트렌치가 형성된 반도체기판의 노출된 영역에 고전압 소스/드레인 이온주입을 실시한 다음 필드산화를 실시하여 필드산화막을 형성하는 공정과; 상기 결과물 상에 제2감광막을 도포하고, 노광 및 현상하여 게이트 형성영역을 제외한 폴리실리콘이 노출되도록 제2감광막 패턴을 형성한 다음 노출된 폴리실리콘을 식각하여 게이트를 형성하고, 제2감광막 패턴을 제거하는 공정으로 이루어지는 반도체소자의 제조방법을 통해 게이트형성을 위한 사진식각을 통해 소자간 격리영역을 동시에 정의하여 공정단순화 및 소자의 특성변화요인을 최소화함으로써, 안정적인 소자의 특성을 확보할 수 있는 효과가 있다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a buffer oxide film on an upper surface of a semiconductor substrate, and then implanting impurity ions for adjusting a threshold voltage; After removing the buffer oxide layer, the gate oxide layer and the polysilicon are sequentially formed, and the first photoresist pattern is formed to expose the polysilicon of the region where the isolation region is to be formed by applying, exposing and developing the first photoresist layer on the polysilicon. Forming step; Etching the polysilicon and the gate oxide layer by applying the first photoresist pattern, overetching the semiconductor substrate to be subsequently etched to a predetermined depth to form a shallow trench, and then removing the first photoresist pattern; Forming a field oxide film by subjecting the exposed region of the semiconductor substrate on which the shallow trench is formed to a high voltage source / drain ion implantation followed by field oxidation; The second photoresist film is coated on the resultant, exposed and developed to form a second photoresist pattern to expose polysilicon except for the gate formation region, and then the exposed polysilicon is etched to form a gate, and the second photoresist pattern is formed. It is effective to secure stable device characteristics by minimizing process simplification and device characteristic change factors by simultaneously defining isolation regions between devices through photolithography for gate formation through a method of manufacturing a semiconductor device. There is.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 절연 게이트(gate isolation) 고전압 트랜지스터(high voltage transistor)의 형성을 단순화함과 아울러 특성을 안정시키기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, which is suitable for simplifying the formation of a gate isolation high voltage transistor and for stabilizing characteristics thereof.
종래 절연 게이트 고전압 트랜지스터의 제조방법을 첨부한 도1a 내지 도1f의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.The detailed description will now be made with reference to the procedure cross-sectional view of FIGS. 1A to 1F attached to a method of manufacturing a conventional insulated gate high voltage transistor.
먼저, 도1a에 도시한 바와같이 통상적인 공정을 통해 엔웰/피웰(미도시)이 형성된 반도체기판(1) 상에 산화막(2)과 질화막(3)을 순차적으로 형성한 다음 질화막(3) 상부에 감광막(PR1)을 도포하고, 노광 및 현상하여 소자간 격리영역이 노출되도록 감광막(PR1) 패턴을 형성한다.First, as shown in FIG. 1A, an oxide film 2 and a nitride film 3 are sequentially formed on a semiconductor substrate 1 on which an Enwell / Pwell (not shown) is formed, and then the upper portion of the nitride film 3. The photoresist film PR1 is coated on the photoresist film, and the photoresist film PR1 pattern is formed so as to expose the isolation region between the devices by exposing and developing the photoresist film PR1.
그리고, 도1b에 도시한 바와같이 상기 감광막(PR1) 패턴에 의해 선택적으로 노출된 질화막(3)을 식각한 다음 고전압 소스/드레인(high voltage source drain : HSD) 이온주입을 실시한다.As shown in FIG. 1B, the nitride film 3 selectively exposed by the photoresist film PR1 pattern is etched, and then a high voltage source drain (HSD) ion implantation is performed.
그리고, 도1c에 도시한 바와같이 상기 감광막(PR1) 패턴을 제거한 다음 필드산화를 실시하여 상기 고전압 소스/드레인 이온주입이 실시된 영역 상에 필드산화막(4)을 형성한다.Then, as shown in FIG. 1C, the photoresist film PR1 pattern is removed, followed by field oxidation to form a field oxide film 4 on the region where the high voltage source / drain ion implantation is performed.
그리고, 도1d에 도시한 바와같이 상기 질화막(3)을 제거한 다음 산화를 실시하여 상부전면에 버퍼산화막(5)을 형성한 다음 필드산화막(4)이 형성되지 않은 반도체기판(1) 상에 문턱전압 조절을 위한 불순물이온을 주입한다.Then, as shown in FIG. 1D, the nitride film 3 is removed and then oxidized to form a buffer oxide film 5 on the upper surface, and then a threshold on the semiconductor substrate 1 on which the field oxide film 4 is not formed. Inject impurity ions for voltage regulation.
그리고, 도1e에 도시한 바와같이 상기 결과물 상에 폴리실리콘(6)을 증착한 다음 폴리실리콘(6) 상부에 감광막(PR2)을 도포하고, 노광 및 현상하여 게이트 형성영역을 제외한 폴리실리콘(6)이 노출되도록 감광막(PR2) 패턴을 형성한다.In addition, as shown in FIG. 1E, polysilicon 6 is deposited on the resultant, and then a photoresist film PR2 is coated on the polysilicon 6, and exposed and developed to expose polysilicon 6 excluding the gate forming region. ) Is formed so that the photosensitive film PR2 pattern is exposed.
그리고, 도1f에 도시한 바와같이 상기 감광막(PR2) 패턴에 의해 선택적으로 노출된 폴리실리콘(6)을 식각하여 게이트를 형성한 다음 감광막(PR2) 패턴을 제거한다.As shown in FIG. 1F, the polysilicon 6 selectively exposed by the photoresist film PR2 pattern is etched to form a gate, and then the photoresist film PR2 pattern is removed.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 필드산화막의 형성을 위한 사진식각이 별도로 진행됨에 따라 버드-빅(bird's beak) 길이의 제어가 어려워 액티브영역의 크기를 제어하기 어렵고, 필드산화막의 형성을 위한 장시간의 산화공정이 요구됨에 따라 제조비용 및 시간의 손실이 발생하는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above, as the photolithography for forming the field oxide film is separately performed, it is difficult to control the length of the bird's beak, so that it is difficult to control the size of the active region. As a long time oxidation process is required for formation, there is a problem in that a loss of manufacturing cost and time occurs.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 게이트형성을 위한 사진식각을 통해 소자간 격리영역을 동시에 정의하여 공정단순화 및 소자의 특성변화요인을 최소화함으로써, 안정적인 소자의 특성을 확보할 수 있는 반도체소자의 제조방법을 제공하는데 있다.The present invention was devised to solve the above-mentioned problems, and an object of the present invention is to simultaneously define isolation regions between devices through photolithography for gate formation to minimize process simplification and characteristics change factors of devices. In addition, the present invention provides a method for manufacturing a semiconductor device capable of securing stable device characteristics.
도1a 내지 도1f는 종래 반도체소자의 제조방법을 보인 수순단면도.1A to 1F are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
도2a 내지 도2f는 본 발명의 일 실시예를 보인 수순단면도.2a to 2f are cross-sectional views showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판 12:버퍼산화막11: semiconductor substrate 12: buffer oxide film
13:게이트산화막 14:폴리실리콘13: gate oxide film 14: polysilicon
15:필드산화막 PR11,PR12:감광막15: Field oxide film PR11, PR12: Photosensitive film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판 상부에 버퍼산화막을 형성한 다음 문턱전압조절을 위한 불순물이온을 주입하는 공정과; 상기 버퍼산화막을 제거한 다음 게이트산화막과 폴리실리콘을 순차적으로 형성하고, 폴리실리콘 상부에 제1감광막을 도포, 노광 및 현상하여 소자간 격리영역이 형성될 영역의 폴리실리콘이 노출되도록 제1감광막 패턴을 형성하는 공정과; 상기 제1감광막 패턴을 적용하여 폴리실리콘과 게이트산화막을 식각하고, 계속해서 노출되는 반도체기판을 소정의 깊이로 식각되도록 과도식각하여 얕은 트렌치를 형성한 다음 제1감광막 패턴을 제거하는 공정과; 상기 얕은 트렌치가 형성된 반도체기판의 노출된 영역에 고전압 소스/드레인 이온주입을 실시한 다음 필드산화를 실시하여 필드산화막을 형성하는 공정과; 상기 결과물 상에 제2감광막을 도포하고, 노광 및 현상하여 게이트 형성영역을 제외한 폴리실리콘이 노출되도록 제2감광막 패턴을 형성한 다음 노출된 폴리실리콘을 식각하여 게이트를 형성하고, 제2감광막 패턴을 제거하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A method of manufacturing a semiconductor device for achieving the object of the present invention as described above comprises the steps of forming a buffer oxide film on the semiconductor substrate and then implanting impurity ions for adjusting the threshold voltage; After removing the buffer oxide layer, the gate oxide layer and the polysilicon are sequentially formed, and the first photoresist pattern is formed to expose the polysilicon of the region where the isolation region is to be formed by applying, exposing and developing the first photoresist layer on the polysilicon. Forming step; Etching the polysilicon and the gate oxide layer by applying the first photoresist pattern, overetching the semiconductor substrate to be subsequently etched to a predetermined depth to form a shallow trench, and then removing the first photoresist pattern; Forming a field oxide film by subjecting the exposed region of the semiconductor substrate on which the shallow trench is formed to a high voltage source / drain ion implantation followed by field oxidation; The second photoresist film is coated on the resultant, exposed and developed to form a second photoresist pattern to expose polysilicon except for the gate formation region, and then the exposed polysilicon is etched to form a gate, and the second photoresist pattern is formed. It is characterized by comprising a step of removing.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법을 첨부한 도2a 내지 도2f의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 2a to 2f attached to the manufacturing method of the semiconductor device according to the present invention as described above in detail as an embodiment as follows.
먼저, 도2a에 도시한 바와같이 통상적인 공정을 통해 엔웰/피웰(미도시)이 형성된 반도체기판(11) 상부에 버퍼산화막(12)을 형성한 다음 문턱전압 조절을 위한 불순물이온을 주입한다.First, as shown in FIG. 2A, a buffer oxide layer 12 is formed on a semiconductor substrate 11 on which an enwell / pewell (not shown) is formed, and then impurity ions are implanted to control a threshold voltage.
그리고, 도2b에 도시한 바와같이 상기 버퍼산화막(12)을 제거하고, 반도체기판(11) 상부에 순차적으로 게이트산화막(13)과 폴리실리콘(14)을 형성한 다음 폴리실리콘(14) 상부에 감광막(PR11)을 도포, 노광 및 현상하여 소자간 격리영역이 형성될 영역의 폴리실리콘(14)이 노출되도록 감광막(PR11) 패턴을 형성한다.As shown in FIG. 2B, the buffer oxide film 12 is removed, and the gate oxide film 13 and the polysilicon 14 are sequentially formed on the semiconductor substrate 11, and then, on the polysilicon 14. The photosensitive film PR11 is coated, exposed and developed to form the photosensitive film PR11 pattern so that the polysilicon 14 in the region where the isolation region between the elements is to be formed is exposed.
그리고, 도2c에 도시한 바와같이 상기 감광막(PR11) 패턴에 의해 노출된 폴리실리콘(14)과 게이트산화막(13)을 순차적으로 식각하고, 계속해서 노출되는 반도체기판(11)을 500Å 정도의 깊이로 식각되도록 과도식각하여 얕은 트렌치를 형성한 다음 감광막(PR11) 패턴을 제거하고, 고전압 소스/드레인 이온주입을 실시한다.As shown in FIG. 2C, the polysilicon 14 and the gate oxide film 13 which are exposed by the photoresist film PR11 pattern are sequentially etched, and the semiconductor substrate 11 that is continuously exposed is about 500Å deep. To form a shallow trench by over-etching so as to be etched into a trench, the photoresist layer PR11 pattern is removed, and a high voltage source / drain ion implantation is performed.
그리고, 도2d에 도시한 바와같이 상기 결과물 상에 필드산화를 실시하여 고전압 소스/드레인 이온주입이 실시된 영역에 필드산화막(15)을 형성한다. 이때, 상기 폴리실리콘(14) 상에도 필드산화로 인해 산화막(미도시)이 성장되지만, 상기 고전압 소스/드레인 이온주입으로 인해 반도체기판(11)이 손상된 영역에서 성장되는 필드산화막(15)에 비해 미세하며, 작은 양의 폴리실리콘(14) 손실을 감안하고도 반도체기판(11)의 손상된 영역을 통해 필드산화 시간을 단축하면서 충분한 격리특성을 갖는 필드산화막(15)을 형성할 수 있게 되고, 또한 얕은 트렌치를 이용함에 따라 필드산화막(15)의 버드-빅 길이를 최소화할 수 있게 된다.As shown in FIG. 2D, field oxidation is performed on the resultant to form the field oxide film 15 in the region where the high voltage source / drain ion implantation is performed. At this time, an oxide film (not shown) is grown on the polysilicon 14 due to field oxidation, but compared to the field oxide film 15 grown in a region where the semiconductor substrate 11 is damaged due to the high voltage source / drain ion implantation. It is possible to form the field oxide film 15 having sufficient isolation characteristics while shortening the field oxidation time through the damaged region of the semiconductor substrate 11 even in view of the fine and small amount of polysilicon 14 loss. By using a shallow trench, it is possible to minimize the bud-big length of the field oxide layer 15.
그리고, 도2e에 도시한 바와같이 상기 결과물 상에 감광막(PR12)을 도포하고, 노광 및 현상하여 게이트 형성영역을 제외한 폴리실리콘(14)이 노출되도록 감광막(PR12) 패턴을 형성한 다음 노출된 폴리실리콘(14)을 습식 식각한다.As shown in FIG. 2E, the photoresist film PR12 is coated on the resultant, exposed and developed to form a photoresist film PR12 pattern to expose the polysilicon 14 except for the gate formation region, and then the exposed poly The silicon 14 is wet etched.
그리고, 도2f에 도시한 바와같이 상기 감광막(PR12) 패턴을 제거한다.Then, as shown in Fig. 2F, the photosensitive film PR12 pattern is removed.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 게이트형성을 위한 사진식각을 통해 얕은 트렌치를 형성하여 소자간 격리영역을 동시에 정의함에 따라 공정단순화를 통해 제조비용 및 시간의 손실을 최소화할 수 있으며, 버드-빅 길이를 최소화하여 액티브영역의 크기 및 공정 마진을 확보함으로써, 소자의 특성변화요인을 최소화하여 안정적인 소자특성을 확보할 수 있는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention as described above, a shallow trench is formed through photolithography for gate formation to define isolation regions between devices at the same time, thereby minimizing manufacturing cost and time loss through process simplicity. In addition, by securing the size of the active region and the process margin by minimizing the bird-big length, there is an effect that can secure the stable device characteristics by minimizing the factors that change the characteristics of the device.
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| JPH06163684A (en) * | 1992-11-26 | 1994-06-10 | Nec Corp | Manufacture of semiconductor device |
| JPH0774274A (en) * | 1993-09-02 | 1995-03-17 | Toshiba Corp | Fabrication of semiconductor device |
| JPH07263433A (en) * | 1994-03-25 | 1995-10-13 | Sharp Corp | Manufacture of semiconductor device |
| JPH0982794A (en) * | 1995-09-20 | 1997-03-28 | Matsushita Electric Ind Co Ltd | Trench isolation formation method |
| KR19990033160A (en) * | 1997-10-23 | 1999-05-15 | 김영환 | Method of manufacturing transistor of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163684A (en) * | 1992-11-26 | 1994-06-10 | Nec Corp | Manufacture of semiconductor device |
| JPH0774274A (en) * | 1993-09-02 | 1995-03-17 | Toshiba Corp | Fabrication of semiconductor device |
| JPH07263433A (en) * | 1994-03-25 | 1995-10-13 | Sharp Corp | Manufacture of semiconductor device |
| JPH0982794A (en) * | 1995-09-20 | 1997-03-28 | Matsushita Electric Ind Co Ltd | Trench isolation formation method |
| KR19990033160A (en) * | 1997-10-23 | 1999-05-15 | 김영환 | Method of manufacturing transistor of semiconductor device |
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