495928 A7 B7 五、發明說明（） 發明頜域： 本發明與一種半導體元件製程有關，特別是關於一 種製造唯讀記憶體（read only memory ; R〇M)之方法。 發明背景= 隨著筆記型電腦 '行動電話及手提式CD等產品輕薄 短小之設計趨勢，促使半導體元件的技術與設計朝著高密 度且高操作速度之要求持續發展。其中唯讀記憶體⑺^^ only memones, ROMs)由於其爲非揮發性記憶體’並可於電 源關閉後保存所儲存之資料’故廣泛的運用於電腦元^件及 電子工業上，用來儲存需永久保存之資料’諸如操作系統、 應用軟體等等…。 一般而言，唯讀記憶體（R〇M)元件包括用以儲存資料 的單元胞陣列以及用來控制該單元胞陣列工作之週圍控制 元件。其中每一位元的資料被儲存於一單元胞中，且該單 元胞一般爲一個η-型通道電晶體或是唯讀記憶體單元胞。 如同熟悉該項技術者所熟知的，藉著對構成記憶體單π胞 之金屬氧化半場效電晶體（MOS transistors)進行離子植 入，可控制其啓始電壓（threshold voltage)，並進而對該唯 讀記憶體進行編程化（Programming) ° 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂---------線丨 經濟部智慧財產局員工消費合作社印製 495928 Α7 ------ Β7 五、發明說明（) 此外藉著使唯讀記憶體（R〇M)之MOS元件具有不同 的啓始電壓，可以對該唯讀記憶體進行編程化。例如，構 成記憶胞之MOS電晶體往往被設計爲具有相同的啓始電壓 以呈現“ Ο N ”或是邏輯“丨”之狀態。至於其中部份單元 胞電晶體則藉著提高其啓始電壓而被編程爲“OFF”或是 邏輯“ 0 ”之狀態。是以根據所設計的儲存電路，可對該唯 讀記憶體中要形成“ OFF”狀態之單元胞其通道，進行一 高劑量且與該通道摻質電性相反之離子植入，來提高其啓 始電壓，並改變其邏輯狀態由“ 1 ”變爲“ 0” ，其中進行 離子植入之區域，一般被稱爲編程區域（c 〇 d i n g r e g i ο η)。此 外，選擇性的增厚閘極氧化層，或是經由形成接觸孔之方 法亦可吊來替換離子植入，對記憶體單元胞進行編程。更 者，亦可藉著改變電晶體之增強模式爲空乏模式而進行資 料寫入。 其中値得注意的是藉著延後進行編程化離子植入程 序，往往可在獲得客戶的訂單後，立即進行編程化程序與 相關後續製程，以有效減少接獲訂單至出貨所需時間（請參 見美國專利案U S 5 , 5 14,6 1 0)。亦即藉著先形成所需之場氧 化隔離區、閘極結構、摻雜區域.等等’並利用高能量之離 子植入進行編程化程序，將可有效提昇交貨效率。然而’ 隨著半導體元件尺寸的日益縮小’形成於半導體底材上之 各式膜層厚度亦大幅降低，是以在進行上述之高能量離子 編程化程序時，往往會對場氧化隔離區等等先形成之元件 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --訂---------線I -- 經濟部智慧財產局員工消費合作社印製 495928495928 A7 B7 5. Description of the invention () Inventive jaw area: The present invention relates to a semiconductor device manufacturing process, and particularly relates to a method for manufacturing a read only memory (ROM). Background of the Invention = With the thin and short design trends of notebook computers, mobile phones and portable CDs, the technology and design of semiconductor components have been continuously developed towards the requirements of high density and high operating speed. Read-only memory (^^ only memones, ROMs) is widely used in computer components and the electronics industry because it is non-volatile memory and can store stored data after the power is turned off. Store the data that needs to be permanently stored, such as operating system, application software, etc ... Generally speaking, read-only memory (ROM) components include a cell array for storing data and surrounding control elements for controlling the operation of the cell array. The data of each bit is stored in a unit cell, and the unit cell is generally an n-type channel transistor or a read-only memory unit cell. As is familiar to those skilled in the art, by implanting metal oxide half field effect transistors (MOS transistors) that make up a single π cell of a memory, the threshold voltage can be controlled, and further Programming of read-only memory ° This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ------ --Order --------- Line 丨 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 495928 Α7 ------ Β7 V. Description of the invention () In addition, by using read-only memory (R〇 M) The MOS devices have different starting voltages, and the read-only memory can be programmed. For example, the MOS transistors that make up the memory cell are often designed to have the same starting voltage to show a state of "0 N" or logic "丨". As for some of them, the cell transistor is programmed to be “OFF” or logic “0” by increasing its starting voltage. According to the design of the storage circuit, the channel of the read-only memory to form an "OFF" state cell can be implanted with a high dose of ion implantation opposite to the dopant of the channel to improve its electrical conductivity. Starting voltage and changing its logic state from "1" to "0", in which the area where the ion implantation is performed is generally referred to as the programming area (c odingregi ο η). In addition, the gate oxide layer can be selectively thickened, or the method of forming contact holes can be used to replace the ion implantation to program the memory cell. Furthermore, data can be written by changing the enhancement mode of the transistor to the empty mode. It is worth noting that by delaying the programmed ion implantation procedure, often after the customer's order is obtained, the programmed procedure and related subsequent processes can be performed immediately to effectively reduce the time required to receive the order and ship it ( (See U.S. Patent No. 5,5 14,6 1 0). That is, by first forming the required field oxidation isolation region, gate structure, doped region, etc., and using high-energy ion implantation to perform the programming process, the delivery efficiency can be effectively improved. However, as the size of semiconductor elements is shrinking, the thickness of various film layers formed on semiconductor substrates has also been greatly reduced. Therefore, during the above-mentioned high-energy ion programming process, the isolation region is often oxidized to the field, etc. The components that are formed first apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling this page) --Order --------- Line I -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 495928
五、發明說明（） 造成損害，並由此產生諸如漏電流等問題。 發明目的及槪沭： 本發明之目的在提供一種可降低漏電流之唯讀記 憶體之製造方法。 本發明之再一目的在提供一種使用自對準光罩來 進行編程化程序之唯讀記憶體製造方法。 本發明之又一目的在提供一種可有效縮短接獲客 戶訂單至出貨所需製程時間之唯讀記憶體製造方法。 本發明提供了 一種製造唯讀記憶體的方法，該方法 包括了下列步驟。首先，形成閘極氧化層於半導體底材 上，其中該半導體·底材上具有場氧化隔離區。接著，形成 多晶矽層於該閘極氧化層上，用來定義閘極結構。再形成 邊牆側壁於該閘極結構之邊牆上’並形成遮蔽層於半導體 底材上以覆蓋該閘極結構。 隨後，使用閘極結構與邊牆側壁作爲罩冪’進行第 一次離子植入程序，以便在半導體底材中，形成源極與汲 極。然後，藉著利用自對準光罩來移除位於所選定欲進行 編程化之閘極結構上表面的遮蔽層，並對所選定之閘極結 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^ ----I I I I I I --II--— — — — — —---------- 495928V. Description of the invention () Causes damage and causes problems such as leakage current. OBJECTS AND PROBLEMS OF THE INVENTION: An object of the present invention is to provide a method for manufacturing a read-only memory that can reduce leakage current. It is still another object of the present invention to provide a read-only memory manufacturing method using a self-aligned mask for programming. Yet another object of the present invention is to provide a read-only memory manufacturing method which can effectively shorten the processing time required to receive a customer's order and ship. The present invention provides a method for manufacturing a read-only memory. The method includes the following steps. First, a gate oxide layer is formed on a semiconductor substrate, wherein the semiconductor substrate has a field oxide isolation region. Next, a polycrystalline silicon layer is formed on the gate oxide layer to define the gate structure. A side wall of the side wall is formed on the side wall of the gate structure, and a shielding layer is formed on the semiconductor substrate to cover the gate structure. Subsequently, the first ion implantation process is performed using the gate structure and the sidewall of the side wall as the mask power 'to form a source and a drain in the semiconductor substrate. Then, by using a self-aligned photomask, the shielding layer on the upper surface of the selected gate structure to be programmed is removed, and the selected gate junction paper size is subject to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ ---- IIIIII --II------- -------- 495928
經濟部智慧財產局員工消費合作社印製 構進行編程化離子植入程序。接著，形成介電層於半導體 底材上表面’以覆蓋該閘極結構，並形成導電插塞於第二 介電層中’其中導電插塞電性連結至閘極結構。 圖式簡單說明 藉由以下詳細之描述結合所附圖示，將可輕易的了 解上述內容及此項發明之諸多優點，其中： ^ 圖爲半導體晶片之截面圖，顯不根據本發明形 成閘極氧化層，多晶矽層及氮化矽層於半導體底材上之步 驟； 第二圖爲半導體晶片之截面圖，顯示根據本發明在 閘極結構上形成邊牆側壁及汲極/源極結構之步驟； 第三圖爲半導體晶片之截面圖，顯示根據本發明在 閘極結構上形成罩冪層以定義欲進行編程化之閘極結構； 第四圖爲半導體晶片之截面圖，顯示根據本發明對 所選定之閘極結構進行編程化離子植入之步驟；且 第五圖爲半導體晶片之截面圖，顯示根據本發明形 成導電插塞之步驟。 發明詳細說明： 本發明提供一個新方法用以製造唯讀記憶體°除了 可延後進行編程化離子植入程序，而大幅減少由接獲客戶 本紙張尺度適用中國g家標準（CNS)A4規格（210 X 297公t ) --------^---------^ ---------------------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 495928 A7 ________ B7 五、發明說明（） 訂單至出貨之製程時間外；更藉著運用自對準光罩來移除 位於閘極結構上之遮蔽氧化層，以提高後續進行編程化離 子植入之效果，此外更避免FOX區在上述移除程序中受到 損壞。有關本發明之詳細說明如下所述。 請參照第一圖，在一較佳之具體實施例中，可提 供一具<1〇〇〉晶向之P型單晶矽底材2，並在底材2上形 成厚場氧化（FOX)隔離區4，以提供元件間之隔離效用。 一般而言，該FOX區4可藉著微影及蝕刻程序蝕刻一氮 化矽-氧化矽複合層而形成，在移除光阻及進行濕式淸洗 後，於蒸氣環境中進行熱氧化以形成厚度約3000至8000 埃的FOX區4。此外，亦可以複數個淺溝隔離（shallow trench isolations)來取代 FOX 區 4。 接著，在該矽底材2上形成一氧化層6以作爲閘極 氧化層之用。在一較佳之具體實施例中，該閘極氧化層6 是由在溫度約800至1100°C之氧蒸氣環境中形成的氧化 矽所構成。同理，該閘極氧化層6亦可以合適的氧化物之 化學組合及程序來形成。例如，該閘極氧化層6可以是使 用化學氣相沈積法所形成之二氧化矽，該化學氣相沈積法 是以正矽酸乙酯（TE0S)在溫度600至800°C間且壓力約 0.1至lOtorr時形成。在一較佳之具體實施例中，該閘極 氧化層6之厚度大約是100-250埃。 ^ ---------^---------^ 1 ----- (請先閱讀背面之注意事項再填寫本頁) 6Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a programmed ion implantation program. Next, a dielectric layer is formed on the upper surface of the semiconductor substrate 'to cover the gate structure, and a conductive plug is formed in the second dielectric layer', wherein the conductive plug is electrically connected to the gate structure. Brief description of the drawing The above-mentioned content and many advantages of this invention can be easily understood through the following detailed description combined with the accompanying drawings, where: ^ The figure is a cross-sectional view of a semiconductor wafer, showing that the gate is not formed according to the present invention Steps of oxidizing layer, polycrystalline silicon layer and silicon nitride layer on semiconductor substrate; The second figure is a cross-sectional view of a semiconductor wafer, showing the steps of forming a sidewall of a sidewall and a drain / source structure on a gate structure according to the present invention The third figure is a cross-sectional view of a semiconductor wafer, showing the formation of a gate layer on the gate structure according to the present invention to define the gate structure to be programmed; the fourth figure is a cross-sectional view of the semiconductor wafer, showing The selected gate structure is subjected to a step of programming ion implantation; and the fifth figure is a cross-sectional view of a semiconductor wafer, showing a step of forming a conductive plug according to the present invention. Detailed description of the invention: The present invention provides a new method for manufacturing read-only memory. In addition to postponing the programmed ion implantation procedure, it greatly reduces the number of papers received by customers. The Chinese standard (CNS) A4 specification is applicable. (210 X 297 male t) -------- ^ --------- ^ ---------------------- (Please Read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 495928 A7 ________ B7 V. Description of the invention () Outside the processing time from order to shipment; moreover, by using a self-aligning mask The shielding oxide layer on the gate structure is removed to improve the effect of subsequent programmed ion implantation, and furthermore, to prevent the FOX region from being damaged during the above removal process. A detailed description of the present invention is as follows. Referring to the first figure, in a preferred embodiment, a P-type single crystal silicon substrate 2 with a <100%> crystal orientation can be provided, and a thick field oxidation (FOX) is formed on the substrate 2 Isolation area 4 to provide isolation between components. Generally speaking, the FOX region 4 can be formed by etching a silicon nitride-silicon oxide composite layer through a lithography and etching process. After removing the photoresist and performing wet cleaning, thermal oxidation is performed in a steam environment to A FOX region 4 is formed having a thickness of about 3000 to 8000 angstroms. In addition, a plurality of shallow trench isolations may be used to replace the FOX region 4. Next, an oxide layer 6 is formed on the silicon substrate 2 as a gate oxide layer. In a preferred embodiment, the gate oxide layer 6 is composed of silicon oxide formed in an oxygen vapor environment at a temperature of about 800 to 1100 ° C. In the same way, the gate oxide layer 6 can also be formed by a suitable chemical combination of oxides and procedures. For example, the gate oxide layer 6 may be silicon dioxide formed using a chemical vapor deposition method. The chemical vapor deposition method is based on ethyl Formed at 0.1 to 10 Torr. In a preferred embodiment, the thickness of the gate oxide layer 6 is about 100-250 angstroms. ^ --------- ^ --------- ^ 1 ----- (Please read the notes on the back before filling this page) 6
經濟部智慧財產局員工消費合作社印製 495928 A7 __ B7 五、發明說明（） 接著，形成一多晶矽層於該閘極氧化層6上，以作 爲後續製造閘極結構之用。一般而言，該多晶矽層可選擇 已摻雜之多晶矽或是採用同步摻雜多晶矽。對一較佳實施 例而言，該摻雜多晶矽層可藉著使用PH;將磷植入加以形 成。隨後，藉著使用傳統微影製程或反應離子蝕刻術（RIE) 對該多晶矽層進行蝕刻，以定義出閘極結構8。値得注意 的是該反應離子蝕刻程序是在充滿SF6與Ch之環境中進 行，並且在鈾刻程序完成後，可藉著使用HF溶液、BOE(阻 障氧化層蝕亥Π溶液或其他類似的溶液將未被閘極結構8 所覆蓋之閘極氧化層6移除。 請參照第二圖，在定義出閘極結構8之後，形成一 厚介電層於該矽底材2上，以覆蓋閘極結構8。在一較佳 實施例中，該介電層可爲氧化層，且該厚氧化層可藉著使 用低壓化學氣相沉積法（LPCVD)，在溫度大約600至800 °C之環境中加以形成。接著對該厚氧化矽層進行蝕刻程 序，可在上述之閘極結構8及閘極氧化層6的邊牆上形成 氧化矽邊牆側壁1 0。其中値得注意的是，該氧化矽邊牆 側壁1 0是以非均向性蝕刻形成的。 隨後，再形成一氧化層1 2於該閘極結構8與矽底材 2之上表面，以作爲遮蔽層（screen layer)。其中該氧化層 12在一較佳實施例中，可在900至1100°C的環境中形成， 且具有厚度約350至500埃。接著，進行一離子植入程序， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 495928 A7 __ B7 V. Description of the invention () Next, a polycrystalline silicon layer is formed on the gate oxide layer 6 for subsequent fabrication of the gate structure. Generally speaking, the polycrystalline silicon layer may be doped polycrystalline silicon or synchronously doped polycrystalline silicon. For a preferred embodiment, the doped polycrystalline silicon layer can be formed by implanting phosphorus using PH; Subsequently, the polycrystalline silicon layer is etched by using a conventional lithography process or reactive ion etching (RIE) to define a gate structure 8. It should be noted that the reactive ion etching process is performed in an environment full of SF6 and Ch, and after the uranium etching process is completed, the HF solution, BOE (Barrier Oxide Etching Solution or other similar) can be used. The solution removes the gate oxide layer 6 that is not covered by the gate structure 8. Referring to the second figure, after the gate structure 8 is defined, a thick dielectric layer is formed on the silicon substrate 2 to cover Gate structure 8. In a preferred embodiment, the dielectric layer may be an oxide layer, and the thick oxide layer may be formed by using a low pressure chemical vapor deposition (LPCVD) method at a temperature of about 600 to 800 ° C. It is formed in the environment. Then, the thick silicon oxide layer is subjected to an etching process to form silicon oxide sidewall walls 10 on the sidewalls of the gate structure 8 and the gate oxide layer 6 described above. It should be noted that The side wall 10 of the silicon oxide sidewall is formed by anisotropic etching. Subsequently, an oxide layer 12 is formed on the upper surface of the gate structure 8 and the silicon substrate 2 as a screen layer. The oxide layer 12 can be used at a temperature of 900 to 1100 ° C in a preferred embodiment. Forming environments, and has a thickness of about 350 to 500 Å. Then, an ion implantation procedure, applicable to the present paper China National Standard Scale (CNS) A4 size (210 X 297 mm)
495928 A7 ______ B7 五、發明說明（） 藉著使用該閘極結構8、該邊牆側壁1 0作爲罩冪將離子 植入矽底材2中，以便形成源極與汲極（S/D) 14。在一較 佳實施例中，進行該離子植入程序之能量及劑量分別爲 0.5 至 100 KeV、1E14 至 5E16 atoms/cm2。 接著，請參照第三圖，形成一光阻層1 6，覆蓋於該 矽底材2之上，以曝露出欲進行編程化之唯讀記憶體單元 胞其閘極結構8，並作爲後續移除遮蔽層1 2之罩冪層。 然後，爲了提昇進行編程化離子植入之效果，使用自對準 光罩進行光阻層1 6塗佈，使該光阻層僅曝露出位於閘極 結構上表面之遮蔽層1 2。接著移除位於該閘極結構8上 表面之遮蔽層1 2。其中在一較佳實施例中，可使用HF溶 液、B0E(阻障氧化層蝕刻）溶液或其他類似的溶液將氧化 層12加以移除，以曝露該閘極結構8。 請參照第四圖，接著對所曝露之閘極結構8進行編 程化之離子植入1 8。値得注意的是由於在進行此離子植 入程序1 8時，所使用之摻質需穿透該閘極結構8與閘極 氧化層6，以便進入位於閘極結構8底下之通道（channel) 中，是以在進行離子植入程序中所使用之摻質，可使用具 有較多電荷之離子物質，且進行植入之能量亦較高。在一 較佳實施例中，可採用N型的摻質P + +，在能量約120至 400 KeV之條件下進行離子植入。 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂-----I——線- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 495928 Α7 Β7 五、發明說明（) 在完成編程化程序後，移除光阻層16，並將遮蔽層 1 2移除，如同第五圖所示。接著，在該閘極結構8、遮蔽層 12與氧化矽側壁10上形成一金屬間介電層20。在一較佳實 施例中，該金屬間介電層20可爲一厚度約爲4000至8000埃 之厚硼磷矽玻璃（BPSG)，且可藉著低壓化學氣相沈積法 (Low Pressure CVD)或是室壓化學氣相沈積法（Air Pressure CVD)在溫度約300至500°C的環境中形成。然後，在溫度約 800至1 100°C，進行高溫熱回火程序以便對該BPSG層20之表 面進行平坦化。隨後，對該金屬間介電層20進行蝕刻程序， 以形成接觸孔（via holes)22，並曝露出該鬧極結構8之上表 面。接著，形成一導電層於該介電層20上’並塡充於該接 觸孔22中，以作爲導電之用。在一較佳實施例中，該導電 層之材料可選擇摻雜多晶矽（doped poly silicon)或是同步摻 雜多晶砂（i η - s i t u d 〇 p e d ρ ο 1 y s i 1 i c ο η)，此外如錦、銅、鶴、 白金或鈦等金屬亦可做爲該導電層之材料。然後，對該導 電層進行蝕刻程序，以形成導電插塞24。 本發明具有諸多之優點。例如，相較於傳統的唯讀 記憶體製程，根據本發明所提供之方法，進行編程化離子 植入的程序，可延後至整個製程之後段再加以進行（請參 見第三圖）。如此，可以在接獲客戶訂單後，立即按照客 戶之需求，進行後續編程化離子植入程序，而大幅降低出 貨所需之製程時間。另外，在進行編程化離子植入時，藉 著利用自對準光罩，將欲進行編程之唯讀記憶體單元胞其 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） * —~ --------^--------- (請先閱讀背面之注意事項再填寫本頁) 495928 A7 B7 五、發明說明（） 閘極結構上的遮蔽層移除，再進行編程化離子植入程序， 可以有效的提昇進行離子植入之效果。特別是藉著運用具 有高能量與高電荷之摻質來進行植入，可以使編程化之效 果獲得顯注的提昇。並且藉著使用自對準光罩來形成光阻 層，以移除位於閘極結構上之遮蔽層，不但可以避免FOX 區域受到損壞，更可避免漏電流的產生。 本發明雖以一較佳實例闡明如上，然其並非用以限 定本發明精神與發明實體，僅止於此一實施例爾。對熟悉 此領域技藝者，在不脫離本發明之精神與範圍內所作之修 改，均應包含在下述之申請專利範圍內。 (請先閱讀背面之注意事項再填寫本頁) 訂----------率 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）495928 A7 ______ B7 V. Description of the invention () By using the gate structure 8 and the side wall side 10 as a mask, ions are implanted into the silicon substrate 2 so as to form a source and a drain (S / D) 14. In a preferred embodiment, the energy and dose for performing the ion implantation procedure are 0.5 to 100 KeV, 1E14 to 5E16 atoms / cm2, respectively. Next, referring to the third figure, a photoresist layer 16 is formed and covered on the silicon substrate 2 to expose the gate structure 8 of the read-only memory cell to be programmed and used as a subsequent shift. Remove the masking layer 12 and cover the power layer. Then, in order to improve the effect of the programmed ion implantation, a photoresist layer 16 is coated using a self-aligned mask, so that the photoresist layer only exposes the shielding layer 12 on the upper surface of the gate structure. Then, the shielding layer 12 on the upper surface of the gate structure 8 is removed. In a preferred embodiment, the oxide layer 12 can be removed by using an HF solution, a BOE (Barrier Oxide Layer Etching) solution, or other similar solution to expose the gate structure 8. Please refer to the fourth figure, and then program the ion implantation 18 of the exposed gate structure 8. It should be noted that when performing the ion implantation procedure 18, the dopants used need to penetrate the gate structure 8 and the gate oxide layer 6 in order to enter the channel under the gate structure 8. Medium is based on the dopants used in the ion implantation procedure, which can use ionic substances with more charge, and the energy for implantation is also higher. In a preferred embodiment, N-type dopant P + + can be used for ion implantation at an energy of about 120 to 400 KeV. This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) (Please read the precautions on the back before filling out this page) Order ----- I——Line-Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumption Cooperative printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative, 495928 Α7 Β7 V. Description of the invention () After completing the programming process, remove the photoresist layer 16 and remove the shielding layer 12 as shown in the fifth figure Show. Next, an intermetal dielectric layer 20 is formed on the gate structure 8, the shielding layer 12 and the silicon oxide sidewall 10. In a preferred embodiment, the intermetal dielectric layer 20 may be a thick borophosphosilicate glass (BPSG) with a thickness of about 4000 to 8000 angstroms, and may be formed by Low Pressure CVD. Or Air Pressure CVD is performed in an environment with a temperature of about 300 to 500 ° C. Then, at a temperature of about 800 to 1100 ° C, a high-temperature thermal tempering process is performed to planarize the surface of the BPSG layer 20. Subsequently, an etching process is performed on the intermetal dielectric layer 20 to form via holes 22 and expose the upper surface of the alarm structure 8. Next, a conductive layer is formed on the dielectric layer 20 'and filled in the contact hole 22 for conductive purpose. In a preferred embodiment, the material of the conductive layer may be doped poly silicon or synchronously doped polycrystalline sand (i η-situd 〇ped ρ ο 1 ysi 1 ic η). Metals such as brocade, copper, crane, platinum or titanium can also be used as the material of the conductive layer. Then, the conductive layer is subjected to an etching process to form a conductive plug 24. The invention has many advantages. For example, compared to the traditional read-only memory system, the method of programming ion implantation according to the method provided by the present invention can be postponed to the later stage of the entire process (see Figure 3). In this way, after receiving the customer's order, the subsequent programmed ion implantation procedure can be performed immediately according to the customer's needs, which greatly reduces the process time required for shipment. In addition, when programming ion implantation, by using a self-aligned photomask, the read-only memory cell to be programmed has a paper size that conforms to the Chinese National Standard (CNS) A4 (210 X 297) %) * — ~ -------- ^ --------- (Please read the notes on the back before filling this page) 495928 A7 B7 V. Description of the invention () on the gate structure The removal of the shielding layer and the programmed ion implantation procedure can effectively improve the effect of ion implantation. In particular, the use of dopants with high energy and high charge for implantation can significantly improve the effect of programming. And by using a self-aligned photomask to form a photoresist layer to remove the shielding layer located on the gate structure, not only can the FOX area be damaged, but also the leakage current can be avoided. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive entity of the present invention, but only to this embodiment. Modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be included in the scope of patent application described below. (Please read the notes on the back before filling this page) Order ---------- Rate printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employees' Cooperatives This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)