5242twf.d〇c/006 t 437006 A7 5242twf.d〇c/006 t 437006 A7 經濟部智慧財產局員工消費合作社印製 ___B7__ 五、發明說明（/) 本發明是有關於一種快閃記憶體（F1 a s h Me mo r y )之 製造方法及其結構，且特別是有關於一種垂直型的快閃記 憶體結構之製造方法，可提高快閃記憶體之集積度。 一般的快閃記憶體結構，包括用來儲存電荷 (Charge)的浮置閘（Floating Gate)和用來控制資料 存取的控制閘（Control Gate)。其中#置閘位於捽制閘 和基底之間丄且氣於浮厚狀態’沒有和任何電路相連接； 而控制閘貝@字元線（Word Line)相接。其中，快閃記 憶體的控制閘連接到字元線，而每個快閃記憶胞的汲極 (Dram)則連接到位孟線，藉以控制每個^^15¥1^ 然而，傳統的快閃記億體製程係以場氧化層（Field 〇X1de; Fox)做爲相鄰之快閃記憶胞的電性隔離結構，以 場氧化層做電性隔離結構會占據矽基底太多面積；再者， 快閃記億體的每一記憶胞之源極/汲極和浮置閘，在配置 上，均需占據矽基底的平面面積，若在既有的快閃記憶體 之結構下縮小源極/汲極和浮置閘的平面佈局面積，會影 響元件的操作效能。 此外，即使使用淺溝渠隔離結構（Shallow Trench5242twf.d〇c / 006 t 437006 A7 5242twf.d〇c / 006 t 437006 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ___B7__ V. Description of the invention (/) The present invention relates to a flash memory ( F1 ash Memory) manufacturing method and structure thereof, and in particular, it relates to a manufacturing method of a vertical type flash memory structure, which can improve the accumulation degree of the flash memory. The general flash memory structure includes a floating gate for storing charges and a control gate for controlling data access. Among them, the #Set gate is located between the control gate and the base, and it is in a state of floating thickness. It is not connected to any circuit; and the control gate is connected to @ 字元 线 (Word Line). Among them, the control gate of the flash memory is connected to the word line, and the drain of each flash memory cell is connected to the bit line to control each ^^ 15 ¥ 1 ^ However, the traditional flash memory The billion system uses the field oxide layer (Field OX1de; Fox) as the electrical isolation structure of adjacent flash memory cells, and the field oxide layer as the electrical isolation structure will occupy too much area of the silicon substrate; furthermore, The source / drain and floating gate of each memory cell of the flash memory need to occupy the planar area of the silicon substrate in the configuration. If the source / drain is reduced under the existing flash memory structure, The planar layout area of the electrodes and floating gates will affect the operation efficiency of the components. In addition, even using shallow trench isolation structures (Shallow Trench
Isolanon; STI)取代以往的場氧化層做爲相鄰的快閃記 憶J包之間的電性隔離，來提高元件的積集度，但由於目前 的製程技術受限於光阻的解析度無法可靠地再提高，因此 使得淺溝渠隔離結構仍佔據基底相當多的平面空間，使快 閃記憶胞的尺寸亦難再縮減。 因此，本發明提供一種可以提高快閃記憶體的集積度 3 ^----Γ I ----'----裝！ 1 訂---------線 - . (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5242t\vf.doc/〇〇6 厶37 0 0 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（L) 之製造方法.---- 本發明提供一種快閃記憶體的製造方法，可以應用目 前的製程技術，將隔離結構及憶體的尺寸再縮小。 本發明提供一種垂直型的快閃記憶體結構，以減少每 一快閃記憶胞占據基底的面積。 鑑於此，本發明提供一種快閔記憶體的製造方法，包 括：提供已形成有一罩幕圖案層的基底，並以罩幕圖案層 爲蝕刻罩幕，將其圖案轉移至基底中，以於基底中形成開 口，再於開口的基底表面形成第一襯氧化層，之後於開口 的側壁形成間隙壁，此間隙壁具有第一底部寬度，接著以 罩幕層和間隙壁爲蝕刻罩幕，以繼續於開口的基底中形成 溝渠，再於溝渠中形成絕緣層，以做爲淺溝渠隔離結構之 用，之後將間隙壁的第一底部寬度縮減至第二底部寬度， 並剝除罩幕圖案層，接著於絕緣層的頂邊轉角處之基底中 和對應於罩幕圖案層下方的基底中，分別形成第一摻雜區 和第二摻雜區，以分別做爲源極和汲極之用，之後剝除間 隙壁*並選擇性地於第二摻雜區的上方形成終止層，接著 於第一摻雜區和第二摻雜區之間的基底表面形成穿遂氧 化層，並於第一摻雜區和第二摻雜區之間的基底側壁，形 成導電間隙壁，再於導電間隙壁上形成第一介電層，之後 將開口塡入導電層，最後定義此導電層、第一介電層和導 電間隙壁，以分別形成複數個控制閘、複數個第二介電層 和複數個浮置閘。 如上所述，其中於形成第一摻雜區和第二摻雜區之後 4 本紙張尺度適用中囷國家標準（CNS)A4規格（210 X 297公釐） I-------------^-------一訂！ I-線 (請先閱讀背面之注項再填寫本頁) 5242twt'.d〇c/0G6 Λ37 Ο ◦ 6 Α7 Β7 經濟部智慧財產局員工消f合作社印製 五、發明說明（幺） 或者之前，更包括於第二摻雜區下方第一摻雜區之側邊的 基底中，形成第三摻雜區，且於淺溝渠隔離結構下方的基 底中形成第四摻雜區，以分別做爲抗擊穿植入和場植入。 而第一摻雜區和第二摻雜區所摻雜之離子的電性與第三 摻雜區和第四摻雜區的電性相反。 再者，本發明提供一種快閃記憶體的結構，包括：一 基底，具有凸出部份和凹陷部份，而凸出部份具有一側 壁，凸出部份和凹陷部份之間之基底具有一表面；一穿遂 氧化層，位於凸出部份之側壁以及凸出部份和凹陷部份之 間之表面；一共用汲極，位於凸出部份的頂端；一源極， 位於凸出部份和凹陷部份之間之基底中；一浮置閘，位於 穿遂氧化層上方，以及源極和汲極之間；一介電層，位於 浮置閘上方；一淺溝渠隔離結構，位於凹陷部份；以及一 控制閘，位於介電層和淺溝渠隔離結構之間。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下= 圖式之簡單說明： 第1Α圖至第1G圖係繪示根據本發明較佳實施例之一 種快閃記憶體的製造流程剖面圖； 、 第2圖係繪τκ第1F圖之上視圖； 第3圖係繪示第1G圖之字元線著陸墊部份的上視 圖； 第4圖係繪示第1G圖之上視圖；以及 I----:1"-------裝---！！1 訂-! —----線 Ψ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 經濟部智慧財產局員工消費合作社印製 524：nvfdot/006 4-3^0^^ A7 _^_B7 五、發明說明（y) 第5圖係繪示本發明之快閃記憶體的等效電路圖。 其中，各圖標號與構件名稱之關係如下： 100 :基底 102、102a :墊氧化層 104、104a :罩幕層 106 :開口 108、U4:襯氧化層 110、110a :間隙壁 150、150a :間隙壁的底部寬度 11 2 :溝渠 116、116a:絕緣層 118 :摻雜區（汲極） 120 :摻雜區（源極） 122 :摻雜區（抗擊穿植入） 124 :摻雜區（場植入） 12 8 :終止層 Π0 :穿遂氧化層 132、132a :導電間隙壁 I 34 :介電層 136、1 36a :導電層 138 :絕緣層 14 0 :接觸窗開口 142、WL!、WU ' WL·、WL4 :字元線 S:、S:、S:、S4、Si、S& :源極線 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------'----^--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 5242twf.doc/006 437006 A7 B7 五、發明說明（孓） CDi、CD::共用汲極線 A :快閃記憶胞 實施例 第1A圖至第1G圖所示，爲根據本發明一較佳實施例 之一種快閃記憶體的製造流程剖面圖。 首先請參照第1A圖，提供一基底100，比如是半導體 矽基底，並於基底100上形成墊氧化層102和罩幕層104。 其中墊氧化層102的形成方法比如是熱氧化法；罩幕層1〇4 的材質比如是氮化矽，其形成方法比如是化學氣相沈積 法。 接著請參照第1B圖，將罩幕層104圖案化成罩幕圖 案層丨04a，並以此罩幕圖案層104a爲蝕刻罩幕，依序蝕 刻墊氧化層102和基底100，使墊氧化層102轉爲墊氧化 層102a，以於基底100中形成開口 106，藉以定義出欲形 成垂直型快閃記憶體的區域，而相鄰開口 106間係定義爲 基底100的凸出部份，此凸出部份係將用於形成汲極和通 道區之用。其中，開G 106面^度端視通SS%長度和廢 極的接合深度而定。 接著請參照第1C圖，於開口 106中的基底100表面 形成一層襯氧化層108，再於開口 106的側壁形成間隙壁 110,其中間隙壁110較佳的材質是氮化矽，此間隙壁110 具有一底部寬度150。 之後進行淺溝渠隔離結構的形成。以罩幕圖案層l〇4a 和間隙壁110爲蝕刻罩幕，繼續往開口 106中的基底100 諳 先 閲 讀 背 意 事 項 4 填 > ί装 頁 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5242twf.doc/006 437〇〇β A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6) 蝕刻，以於基底100中形成溝渠112，此溝渠112係定義 爲基底100的凹陷部份，此溝渠1丄2_Β做爲淺溝凓關結 構之用。而吐溝渠112的形成10ή 壁制其尺寸，故可突破微影製程上的限制，以在 ------- --- — - - —1 - 不影響電性隔離的效果下，有效縮小欲形成於溝渠112中 之淺溝渠隔離結構占據基底100的平面面積。續於溝渠112 的基底100表面形成襯氧化層114，並與襯氧化層108於 溝渠112的頂端相連，襯氧化層114的形成方法比如是熱 氧化法。之後覆蓋一層絕緣層116，用以塡滿開口 106和 溝渠112，絕緣層116的材質較佳的是氧化矽，其形成方 法比如是化學氣相沈積法。 接著請參照第1D圖，將絕緣層116回蝕刻至僅塡滿 溝渠Π2，使其轉爲絕緣層116a，之後將絕緣層116a進 行緻密化，以提高絕緣層116a電性阻隔的能力，而經緻 密化的絕緣層116a和介於基底100之間的襯氧化層114 則做爲淺溝渠隔離結構之用。之後，將間隙壁110的尺寸 縮小成如圖所示之間隙壁110a，以使其底部寬度150縮減 爲如圖所示之底部寬度150a，其縮短的方法比如利用回蝕 刻法，在此並同時將墊氧化層102a上方的罩幕圖案層104a 予以剝除。 續進行兩階段的離子植入步驟。首先進行第一階段的 離子植入步驟，以間隙壁110a和絕緣層116a做爲離子植 入罩幕，以於墊氧化層102a下方的基底100中（即凸出 部份的頂端），以及絕緣層116a頂端的基底100中（即Isolanon; STI) replaces the previous field oxide layer as the electrical isolation between adjacent flash memory J packages to improve the component accumulation, but the current process technology is limited by the resolution of the photoresist. Reliably improve, so that the shallow trench isolation structure still occupies a considerable amount of planar space on the substrate, making it difficult to reduce the size of the flash memory cell. Therefore, the present invention provides a method for improving the accumulation degree of the flash memory. 3 ^ ---- Γ I ----'---- load! 1 Order --------- Line-. (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 5242t \ vf .doc / 〇〇6 厶 37 0 0 6 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Manufacturing method of invention description (L). The present invention provides a method for manufacturing flash memory. The current process technology can be used to reduce the size of the isolation structure and memory. The invention provides a vertical flash memory structure to reduce the area occupied by each flash memory cell on the substrate. In view of this, the present invention provides a method for manufacturing a flash memory, which includes: providing a substrate having a mask pattern layer formed thereon, and using the mask pattern layer as an etching mask, transferring its pattern to the substrate so that the substrate An opening is formed in the middle, and a first lining oxide layer is formed on the base surface of the opening, and then a gap wall is formed on the side wall of the opening. The gap wall has a first bottom width, and then the mask layer and the gap wall are used as the etching mask to continue. A trench is formed in the opening base, and an insulating layer is formed in the trench to serve as a shallow trench isolation structure. Then, the first bottom width of the partition wall is reduced to the second bottom width, and the mask pattern layer is stripped. Then, a first doped region and a second doped region are formed in the substrate at the corner of the top edge of the insulating layer and in the substrate corresponding to the mask pattern layer, respectively, for use as a source and a drain, respectively. The spacers are then stripped off and a stop layer is selectively formed over the second doped region, and then a tunneling oxide layer is formed on the substrate surface between the first doped region and the second doped region, and is formed on the first doped region. The sidewall of the substrate between the impurity region and the second doped region forms a conductive spacer, and then a first dielectric layer is formed on the conductive spacer, and then an opening is inserted into the conductive layer. Finally, the conductive layer and the first dielectric are defined. Layer and conductive gap wall to form a plurality of control gates, a plurality of second dielectric layers and a plurality of floating gates, respectively. As mentioned above, after forming the first doped region and the second doped region, 4 paper sizes are applicable to the China National Standard (CNS) A4 specification (210 X 297 mm) I --------- ---- ^ ------- Order! I-line (please read the note on the back before filling this page) 5242twt'.d〇c / 0G6 Λ37 Ο ◦ 6 Α7 Β7 Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative, V. Invention Description (幺) or before It further includes forming a third doped region in the substrate on the side of the first doped region below the second doped region, and forming a fourth doped region in the substrate below the shallow trench isolation structure, respectively, as Anti-breakdown implantation and field implantation. The electrical properties of the ions doped in the first and second doped regions are opposite to those of the third and fourth doped regions. Furthermore, the present invention provides a structure of a flash memory, including: a substrate having a protruding portion and a recessed portion, and the protruding portion has a sidewall, a substrate between the protruding portion and the recessed portion It has a surface; a tunneling oxide layer located on the side wall of the protruding portion and the surface between the protruding portion and the recessed portion; a common drain electrode located on the top of the protruding portion; a source electrode located on the convex portion In the substrate between the exit and recess; a floating gate above the tunneling oxide layer and between the source and drain; a dielectric layer above the floating gate; a shallow trench isolation structure , Located in the depression; and a control gate, located between the dielectric layer and the shallow trench isolation structure. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: = Brief description of the drawings: Figure 1A to FIG. 1G is a cross-sectional view of a flash memory manufacturing process according to a preferred embodiment of the present invention; FIG. 2 is a top view of τκ and FIG. 1F; and FIG. 3 is a drawing of FIG. 1G Top view of the yuan line landing pad; Figure 4 shows the top view of Figure 1G; and I ----: 1 " ----------------! !! 1 Order-! —---- Line Card (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210x297 mm) Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System 524: nvfdot / 006 4-3 ^ 0 ^^ A7 _ ^ _ B7 V. Description of the invention (y) Figure 5 is an equivalent circuit diagram of the flash memory of the present invention. Among them, the relationship between each icon number and the component name is as follows: 100: substrate 102, 102a: pad oxide layer 104, 104a: cover layer 106: opening 108, U4: lining oxide layer 110, 110a: spacer 150, 150a: gap Width of bottom of wall 11 2: trench 116, 116a: insulating layer 118: doped region (drain) 120: doped region (source) 122: doped region (anti-breakdown implantation) 124: doped region (field Implantation) 12 8: Termination layer Π0: Passive oxide layers 132, 132a: Conductive spacers I 34: Dielectric layers 136, 136a: Conductive layer 138: Insulating layer 14 0: Contact window openings 142, WL !, WU 'WL ·, WL4: Character line S :, S :, S :, S4, Si, S &: Source line 6 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm)- -------'---- ^ -------- Order --------- line (Please read the precautions on the back before filling this page) 5242twf.doc / 006 437006 A7 B7 V. Description of the invention (i) CDi, CD :: shared drain line A: flash memory cell, as shown in FIGS. 1A to 1G, which is a flash memory according to a preferred embodiment of the present invention A cross-sectional view of the memory manufacturing process. First, referring to FIG. 1A, a substrate 100 is provided, such as a semiconductor silicon substrate, and a pad oxide layer 102 and a mask layer 104 are formed on the substrate 100. The method for forming the pad oxide layer 102 is, for example, a thermal oxidation method; the material of the mask layer 104 is, for example, silicon nitride, and the method for forming the mask layer 102 is, for example, a chemical vapor deposition method. Next, referring to FIG. 1B, the mask layer 104 is patterned into a mask pattern layer 04a, and the mask pattern layer 104a is used as an etching mask to sequentially etch the pad oxide layer 102 and the substrate 100 to make the pad oxide layer 102 It is converted to a pad oxide layer 102a to form an opening 106 in the substrate 100, thereby defining a region where a vertical flash memory is to be formed, and the adjacent opening 106 is defined as a protruding portion of the substrate 100, and this protrusion Some will be used to form the drain and channel regions. Among them, the open end of the G 106 surface depends on the length of the SS% and the bonding depth of the waste electrode. Next, referring to FIG. 1C, a lining oxide layer 108 is formed on the surface of the substrate 100 in the opening 106, and a spacer 110 is formed on the side wall of the opening 106. The preferred material of the spacer 110 is silicon nitride. This spacer 110 Has a bottom width of 150. The formation of a shallow trench isolation structure is then performed. Using the mask pattern layer 104a and the partition wall 110 as the etching mask, continue to the substrate 100 in the opening 106. Read the notes first 4 Fill in the booklet and print the printed copy of the staff ’s consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 5242twf.doc / 006 437〇〇β A7 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (6) Etching A trench 112 is formed in the substrate 100. The trench 112 is defined as a recessed portion of the substrate 100. The trench 1 丄 2_B is used as a shallow trench structure. The formation of the ditch 112 can be made by its size, so it can break through the limitations of the lithography process in order to be effective without affecting the effect of electrical isolation -----------1- Shallow trench isolation structures to be formed in the trenches 112 reduce the planar area of the substrate 100. A liner oxide layer 114 is formed on the surface of the substrate 100 that continues from the trench 112 and is connected to the top of the trench 112 with the liner oxide layer 108. A method for forming the liner oxide layer 114 is, for example, a thermal oxidation method. Then, an insulating layer 116 is covered to fill the openings 106 and the trenches 112. The material of the insulating layer 116 is preferably silicon oxide, and the formation method thereof is, for example, chemical vapor deposition. Next, referring to FIG. 1D, the insulating layer 116 is etched back to only the full trench Π2 to turn it into an insulating layer 116a. Then, the insulating layer 116a is densified to improve the ability of the insulating layer 116a to electrically block. The densified insulating layer 116a and the lining oxide layer 114 interposed between the substrate 100 are used as a shallow trench isolation structure. After that, the size of the gap wall 110 is reduced to the gap wall 110a as shown in the figure, so that the bottom width 150 thereof is reduced to the bottom width 150a as shown in the figure. The mask pattern layer 104a above the pad oxide layer 102a is stripped. Continue with a two-stage ion implantation step. The first stage of the ion implantation step is performed. The spacer 110a and the insulating layer 116a are used as the ion implantation mask to pad the substrate 100 (that is, the top of the protruding portion) under the oxide layer 102a, and the insulation In the substrate 100 on top of the layer 116a (i.e.
S 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^---------1---I-^--------訂---------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 _〇〇,· 4370 υ 6 Α7 _Β7__ 五、發明說明（^]) 凸出部份和凹陷部份之間）分別形成摻雜區118和120, 以分別做爲汲極和源極1用，此源極和汲極係爲埋入式的 源極線和埋入式的共用汲極（Common Drain)線，其中摻 雜區118和120所摻雜的離子比如是N型的離子或P型的 離子，端視所欲形成的快閃記憶體是爲N型或P型而定， 摻雜的劑量比如約爲1015原子/平方公分左右，能量約爲 40-60keV。接著進行第二階段的離子植入步驟，所植入的 離子之導電性與第一階段的離子是相反的，用以於絕緣層 116a底部的基底100中，以及墊氧化層102a下方之相鄰 的摻雜區120間分別形成摻雜區122和124，以分別做爲 淺溝渠隔離結構之場植入（Field Implant)和相鄰源極 之間的抗擊笔植入(An t i - punch through Imp 1 an t )之用， 其中摻雜的劑量比如約爲1012原子/平方公分左右。其中 第一階段的離子植入步驟和第二階段的離子植入步驟可 互換。 接著請參照第1E圖，剝除間隙壁110a後，將開口 106 塡滿塡充物質層126 (爲方便圖示，在此將襯氧化層108 納入於塡充物質層126中的一部份），此塡充物質層126 係利於後續選擇性的氮化反應之進行。其中塡充物質層 126的材質較佳的是氧化矽，其形成方法比如是利用化學 氣相沈積法於基底100上覆蓋一層氧化層，之後進行回蝕 刻製程，至剝除墊氧化層102a以暴露出做爲汲極之用的 摻雜區118之基底100表面止。續於做爲汲極的摻雜區118 上方形成一層終止層128，其材質較佳的是氮氧化矽，其 9 -------------^—i^i-------線 <請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 1 437 0 U6 A7 5242lwt'doc/006 __B7_ 五、發明說明（> ) 方法比如藉由在通入少量氧的環境中進行氮化反應 (Nitradauon)，而氮化反應僅發生於摻雜區118的基 底100表面，其中塡充物質層126在此係用於保護做爲汲 極的摻雜區118及其下方的基底100側壁。 接著請參照第1F圖，剝除塡充物質層126，至裸露出 做爲汲極的摻雜區118及其下方的基底100側壁，之後於 所裸露出的基底100表面形成一層穿遂氧化層130，並延 伸至與襯氧化層114於絕緣層116a的頂端處接觸，其中 穿遂氧化層Π0的形成方法比如是熱氧化法。 續於做爲源極的摻雜區120和做爲汲極的摻雜區118 之間的基底100側壁形成導電間隙壁Π2，其材質比如是 摻雜的複晶矽，導電間隙壁132的形成方法比如是於基底 100上形成一層共形的摻雜的複晶矽，之後進行非等向性 蝕刻製程，並以終止層128做爲鈾刻終止層_，藉以成此 導電間隙壁132。此導電間隙壁132將於後續做爲快閃記 憶體的浮置|之用。 ~ ' 之後於導電間隙壁132的表面形成介電層134，此介 電層134比如是利用熱氧化法而形成的氧化層，亦或是氧 化矽-氮化矽-氧化矽的結構。最後於開口 106中塡入導電 材質，其材質比如是摻雜的複晶矽，其方法比如是於基底 100上覆蓋一層導電層，再進行回蝕刻製程，以形成導電 層136,使得相鄰開口 106間之導電層136呈不連續狀態， 請參照第2圖，其係爲第1F圖的上視圖，此導電層136 將於後續做爲快閃記憶體的控制閘之用。 10 I-------------- 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5242twf,doc/006 437006 B7 五、發明說明（7) 接著請參照第1G圖，將導電層136圖案化成導電層 1 36a (請同時參照第3圖），同時介電層134和導電間隙 壁132亦圖案化成介電層134a和導電間隙壁132,其中導 電層136a係爲字元線的著陸墊（Landing Pad)，亦爲快 閃記憶體的控制閘，而導電間隙壁132a爲快閃記憶體的 浮置閘。其中，第3圖所示，係爲做爲著陸墊之導電層136a 的上視圖。 之後於導電層136a上方形成字元線142,此字元線 142透過接觸窗開口 140與做爲著陸墊之導電層136a接 觸，而導電層136a和字元線142間係以絕緣層138做電 性隔離，絕緣層138的材質比如是氧化矽，而字元線142 的材質比如是鋁、鋁銅合金、銅等。其中字元線H2係與 做爲埋入式的源極線和共用汲極線之摻雜區120和118大 致垂直。由於做爲汲極之摻雜區118係爲相鄰之快閃記憶 胞所共用，故爲了避免操作上的干擾，因此位於字元線142 之平行方向的相鄰之快閃記憶胞，係分別連接於不同的字 元線142，請參見第4圖所繪示之第1G圖的上視圖。 後續的內連線製程非關本發明，在此不多贅言。以下 將描述本發明之快閃記憶體的操作方法。 快閃記憶體的操作 本發明之快閃記憶體的等效電路圖如第5圖所示，其 操作模式可分爲兩種，一種是以：FN鸯未除 (Erase)，以熱電子注入g進行編碼；另二種是以JN穿 遂來進行挂除，並上來進行編碼（Program)。 本紙張尺度適用卡國國家標準（CNS)A4規格（210 X 297公釐） -------------r、装--- - - * . (請先閱讀背面之注意事項再填寫本頁) · --線· 經濟部智慧財產局員工消費合作社印製 5242t\vl'.d〇c/006 437 0 0 6 A7 5242t\vl'.d〇c/006 437 0 0 6 A7 經濟部智慧財產局貝工消費合作社印製 B7 五、發明說明（〜） 以第一種操作模式爲例，當對快閃記億體進行抹除 時，對源極線（Si、s2、Sr S4、S5、s6)、共用汲極線（CD，、 CDO和基底施加正電壓，對字元線（WL·、WL·、WL·、WL· ) 施加負電壓，以藉由FN穿遂將浮置閘的電子拉出，以達 到全面性抹除的目的。當對快閃記憶體的快閃記憶胞A進 行編碼時，對選定的共用汲極線（CD,)施加0V電壓，對 選定的源極線（Si)施加正電壓，比如約爲Va，對選定的 字元線（WL0施加比選定的源極（s2)更高的正電壓，比 如約爲2V“ ’對未選定的源極線（Si、S.，、S4、S5、Sh)和 共用汲極線（CD0施加0V電壓，對未選定的字元線（WL·、 WL·、WL·)施加0V電壓或負電壓，以藉由熱電子注入將電 子注入浮置閘，以達到對快閃記憶胞Α編碼的目的。 以第二種操作模式爲例，當對快閃記憶體進行抹除 時，對源極線（Si、S2、S3、S*、S5、S6)、共用汲極線（CD,、 CD2)和基底施加〇V電壓，對字元線（WL·、WL·、WL·、WLO 施加正電壓，以藉由FN穿遂將電子注入浮置閘，以達到 全面性抹除的目的。當對快閃記憶體的快閃記憶胞A進行 編碼時，對選定的共用汲極線（CDJ施加高電壓，比如約 爲V“，對選定的源極線（S2)施加高電壓，比如約爲Vd， 對選定的字元線（WL·)施加負電壓，對未選定的源極線 (Si、S.;、S%、Ss、SO、共用汲極線（CD，）和字元線（WL,、 WL·、WL·)施加0V電壓，以藉由FN穿遂將浮置閘的電子 拉出，以達到對快閃記憶胞A編碼的目的。 綜上所述，本發明具有以下的優點： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---II!!!·1"装---！11 訂·！ I 線 *·---- - (請先閲讀背面之注意事項再填寫本頁) 5242lwf.doc/006 437 0 0 6 a? 五、發明說明（// ) 1. 本發明係應用目前的製程技術製造快閃記憶體， 而此不但快閃記憶體的隔離結構占據基底的面_可以有 效敗障低’其集積度亦可以复效的提高。 2. 本發明之快閃記憶體的結構係爲垂直型，故可以 有效降低快閃記憶胞占據基底的面積。 3. 本發明之快閃記憶體的製程簡單，且大部份爲自 動對準（Self-AUgn)的製程，故使用的光罩數較少，因 此可以降低製程的成本。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 "；----:丨"---.---Ί^--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）S This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ^ --------- 1 --- I-^ -------- Order ---- ----- line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _〇〇, · 4370 υ 6 Α7 _Β7__ 5. Description of the invention (^) Doped regions 118 and 120, respectively, for the drain and source 1, respectively. The source and drain are shared by the buried source line and the buried type. Common Drain line, in which the ions doped in the doped regions 118 and 120 are, for example, N-type ions or P-type ions, depending on whether the flash memory to be formed is N-type or P-type The doping dose is, for example, about 1015 atoms / cm 2 and the energy is about 40-60 keV. Next, a second stage ion implantation step is performed. The conductivity of the implanted ions is opposite to that of the first stage ions, and is used in the substrate 100 at the bottom of the insulating layer 116a and adjacent to the pad oxide layer 102a. The doped regions 122 and 124 are formed between the doped regions 120 respectively, which are used as field implants for shallow trench isolation structures and An ti-punch through Imp 1 an t), where the doping dose is, for example, about 1012 atoms / cm 2. The ion implantation step in the first stage and the ion implantation step in the second stage are interchangeable. Next, referring to FIG. 1E, after the spacer 110a is peeled off, the opening 106 is filled with the filling material layer 126 (for convenience of illustration, the lining oxide layer 108 is included in the filling material layer 126) The filling material layer 126 is beneficial to the subsequent selective nitriding reaction. The material of the filling material layer 126 is preferably silicon oxide. The formation method is, for example, using a chemical vapor deposition method to cover the substrate 100 with an oxide layer, and then performing an etch-back process to strip the pad oxide layer 102a to expose The surface of the substrate 100 is doped with the doped region 118 as a drain. Continuing to form a stop layer 128 over the doped region 118 as a drain, the material is preferably silicon oxynitride, which is 9 ------------- ^-i ^ i-- ----- line < Please read the notes on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 1 437 0 U6 A7 5242lwt'doc / 006 __B7_ V. Description of the invention (e.g., by performing a nitriding reaction (Nitradauon) in a small amount of oxygen, and the nitriding reaction only occurs in the doped region 118) On the surface of the substrate 100, the erbium-filled material layer 126 is used to protect the doped region 118 as a drain and the sidewall of the substrate 100 below it. Next, referring to FIG. 1F, the infill material layer 126 is stripped to expose the doped region 118 as a drain and the sidewall of the substrate 100 below it, and then a through oxide layer is formed on the surface of the exposed substrate 100. 130, and extends to contact the lining oxide layer 114 at the top of the insulating layer 116a, wherein the formation method of the tunneling oxide layer Π0 is, for example, a thermal oxidation method. Continued from the side wall of the substrate 100 between the doped region 120 as the source and the doped region 118 as the drain, a conductive spacer Π2 is formed. The material is, for example, doped polycrystalline silicon, and the conductive spacer 132 is formed. The method is, for example, forming a layer of conformally doped polycrystalline silicon on the substrate 100, and then performing an anisotropic etching process, and using the termination layer 128 as a uranium etching termination layer to form the conductive spacer 132. The conductive spacer 132 will be used as a floating memory for the flash memory in the future. After that, a dielectric layer 134 is formed on the surface of the conductive spacer wall 132. The dielectric layer 134 is, for example, an oxide layer formed by a thermal oxidation method, or a structure of silicon oxide-silicon nitride-silicon oxide. Finally, a conductive material is inserted into the opening 106. The material is, for example, doped polycrystalline silicon. The method is to cover the substrate 100 with a conductive layer, and then perform an etch-back process to form a conductive layer 136 so that adjacent openings are formed. The conductive layer 136 between 106 is in a discontinuous state. Please refer to FIG. 2, which is a top view of FIG. 1F. This conductive layer 136 will be used as a control gate of the flash memory in the future. 10 I -------------- Install -------- Order --------- line (Please read the precautions on the back before filling this page) The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 5242twf, doc / 006 437006 B7 V. Description of the invention (7) Next, referring to Figure 1G, the conductive layer 136 is patterned into a conductive layer 1 36a ( Please refer to FIG. 3 at the same time. At the same time, the dielectric layer 134 and the conductive spacer wall 132 are also patterned into a dielectric layer 134a and a conductive spacer wall 132. The conductive layer 136a is a land pad of a word line. The flash memory is a control gate, and the conductive partition wall 132a is a floating gate of the flash memory. Among them, FIG. 3 is a top view of the conductive layer 136a as a landing pad. Then, a word line 142 is formed over the conductive layer 136a. The word line 142 contacts the conductive layer 136a as a landing pad through the contact window opening 140, and the insulating layer 138 is used as electricity between the conductive layer 136a and the word line 142. For example, the material of the insulating layer 138 is silicon oxide, and the material of the word line 142 is aluminum, aluminum-copper alloy, copper, or the like. The word line H2 is substantially perpendicular to the doped regions 120 and 118 as the buried source line and the shared drain line. Since the doped region 118 serving as the drain is shared by adjacent flash memory cells, in order to avoid operational interference, adjacent flash memory cells located parallel to the word line 142 are respectively Connected to different word lines 142, please refer to the top view of FIG. 1G shown in FIG. Subsequent interconnection processes are not relevant to the present invention, and are not repeated here. The operation method of the flash memory of the present invention will be described below. Flash memory operation The equivalent circuit diagram of the flash memory of the present invention is shown in Figure 5. Its operation mode can be divided into two types. One is: FN 鸯 Erase, and the hot electron is injected into g. Encoding; the other two use JN tunneling to hang up, and come up to encode (Program). This paper size is applicable to the national standard of the country (CNS) A4 (210 X 297 mm) ------------- r, installed -----*. (Please read the note on the back first Please fill in this page again for matters) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5242t \ vl'.d〇c / 006 437 0 0 6 A7 5242t \ vl'.d〇c / 006 437 0 0 6 A7 Printed by the Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Description of the Invention (~) Taking the first operation mode as an example, when erasing the flash memory, the source line (Si, s2, Sr) S4, S5, s6), the common drain lines (CD ,, CDO, and the substrate are applied with a positive voltage, and the word lines (WL ·, WL ·, WL ·, WL ·) are applied with a negative voltage to pass through the FN tunneling. The floating gate's electrons are pulled out to achieve the purpose of comprehensive erasing. When the flash memory cell A of the flash memory is encoded, 0V is applied to the selected common drain line (CD,) and the selected A positive voltage is applied to the source line (Si), such as about Va, and a higher positive voltage is applied to the selected word line (WL0 than the selected source (s2), such as about 2V. "'For an unselected source Epipolar line (Si, S. , S4, S5, Sh) and the common drain line (CD0 apply 0V voltage, apply 0V or negative voltage to the unselected word line (WL ·, WL ·, WL ·) to inject electrons by hot electron injection The floating gate is injected to achieve the purpose of encoding the flash memory cell A. Taking the second operation mode as an example, when the flash memory is erased, the source lines (Si, S2, S3, S * , S5, S6), the common drain line (CD ,, CD2) and the substrate are applied with a voltage of 0V, and a positive voltage is applied to the word line (WL ·, WL ·, WL ·, WLO) to pass electrons through FN tunneling. The floating gate is injected for the purpose of comprehensive erasing. When the flash memory cell A of the flash memory is encoded, a selected common drain line (CDJ is applied with a high voltage, such as about V ", and A high voltage is applied to the selected source line (S2), for example, about Vd, a negative voltage is applied to the selected word line (WL ·), and an unselected source line (Si, S.;, S%, Ss, SO, common drain line (CD,) and word line (WL ,, WL ·, WL ·) apply 0V voltage to pull out the floating gate electrons by FN tunneling to achieve flash memory cells A To sum up, the present invention has the following advantages: The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --- II !!! · 1 " packing ---! 11 Order ·! I line * · -----(Please read the notes on the back before filling in this page) 5242lwf.doc / 006 437 0 0 6 a? V. Description of the invention (//) 1. This invention is applied Current process technology manufactures flash memory, and not only the isolation structure of the flash memory occupies the surface of the substrate, which can effectively reduce obstacles, and its accumulation can also be improved. 2. The structure of the flash memory of the present invention is vertical, so it can effectively reduce the area occupied by the flash memory cells on the substrate. 3. The flash memory of the present invention has a simple manufacturing process, and most of it is a self-aligned (Self-AUgn) manufacturing process, so the number of photomasks used is small, so the manufacturing cost can be reduced. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. " ----: 丨 " ---.--- Ί ^ -------- Order --------- line (Please read the notes on the back before filling in this Page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)