1270179 九、發明說明： 【發明所屬之技術領域】 種製作溝渠電容動 本發明係關於半導體製程，_是有關於一 態隨機存取記憶體元件的方法。 【先前技術】 體等^種元=3小__勢，如__取記憶 體專3己_讀的_也必簡合高鶴度、高密度 中溝渠電容動態隨機存取記憶華職)元件 界’》、 ^痛度D讓架構，其顧係在半導體基射編 = 果 溝=然後再於深溝渠内製作溝渠電容結構，因此能有效縮小記 fe單元之尺寸，妥善利用晶片空間。 口口請參閱第1圖至第_，其緣示的是習知製作溝渠電容dram 單元之剖面示意圖。首先，如第i圖所示，於半導體基底10表面 形成深溝渠結構11。形成深溝渠結構u的方法係先於半導體基底 1〇表面沈積襯氧化矽層12、襯氮化矽層14及硼矽玻璃層16做為 餘刻遮罩(etching mask)，再利用傳統之黃光及蝕刻法，例如活性 離子蝕刻(reactive ion etching, RIE)技術來完成深溝渠結構11。 如第2圖所示，將剩餘的硼矽玻璃層16去除後，接著於深溝 渠結構11的内壁上以及襯氮化石夕層14上沈積一珅石夕玻璃(arsenic silicate glass，ASG)層22。然後，再於深溝渠結構11的下部形成一 1270179 阻，並填_ if 的加_轉縣底1G上塗佈光 W溝渠結構n，隨後再加以，光阻。接著，去除 不阻層24覆蓋之石申石夕玻璃層办即形成如第2圖所示之結構。 所贩々苴圖斤不進行一熱擴散製程’將砷矽玻璃層22中的摻 中二形成埋，，其作為峨 谷 電極。隨後，去除光阻層24以及砷矽玻璃層22。 ❿ 二第4圖所示’接著於深溝雜構u内壁上形成—電容介電 氧切·氮切層或氧化^氮化^氧切層，然· :而::構U内形成一第一多晶矽層29，其上表面低於基底10 义言^。根據習知技藝’第一多晶石夕層Μ經過凹陷侧後，其 ^表面係在後續所形成之領氧化層之下。接著， 晶石夕層29覆蓋之電容介電層… 弟 第圖所示’接著於第一多晶石夕層29上方之深溝渠結構11 内壁上形成一領氧化層32,然後於深溝渠結構11内形成第二多晶 石夕層34。領氧化層32的作法係先以CVD沈積-氧化膜，然後回 餘刻。 如第6圖所*，接著將未被第二多晶石夕層34覆蓋之領氧化声 _基底10並於深溝渠結構„上方形成 (recess)36 〇 6 1270179 如第7圖所示，接著於凹口 36内形成第三多晶矽層44。第三 多晶石夕層44的上表面低於基底10表面。隨後進行一化學氣相沈 積衣程’於半導體基底上沈積一硼梦玻璃層46，並填滿深溝渠 結構11。 如第8圖所示，接著進行一黃光製程，利用光阻牝定義出淺 溝絕緣(STI)區域開口 50以及淺溝絕緣區域以外的主動區域，光阻 的圖案隨後利用非等向性乾钱刻轉移至下方的硼矽玻璃層46以及 襯氮化石夕層14中。 如第9圖所示，接著利用光阻48以及爛石夕玻璃層46為餘刻硬 遮罩，經由淺溝絕緣區域開口 ％向下侧轉體基底⑴、部分的 第三多晶销44、部分的第二多晶韻以及部分義氧化層&， 形成淺溝絕緣區域開口 52，藉此將兩相峰渠電容隔絕。 如第1〇圖所不’在去除剩餘之卿玻璃層奶後，於淺親緣 區域開口 52内填入高密度電漿矽氧化層弘。 最後，如苐11圖所示，: 化矽層14作為研磨停止層， 定厚度。 進行-化學機械研磨製程，利用襯氮 •將高密度絲魏化層5叫磨至預 作方法可大致被歸納 習知溝渠電容動態隨機存取記憶體的製 1270179 成七個主要階段，其依序為： 1·深溝渠蝕刻階段； 2·埋入電盤(buried plate)製作以及電容介電層製作階段； 3·深溝渠第一多晶矽層沈積以及凹陷蝕刻階段； 4·領氧化層製作階段； 5·深溝渠第二多晶矽層製作以及凹陷蝕刻階段； 6·深溝渠第三多晶矽層製作以及凹陷蝕刻階段；以及 7· STI製程。 由此可知，習知溝渠電容動態隨機存取記憶體的製作方法製程 步驟繁雜，需要先後進行三次的多晶矽層29、34及44沈積製程， 母-人沈積製程後再分別將其回餘刻（凹陷钱刻）。此外，隨著電容元 件所佔面積減小，領氧化層的厚度已經影響到第二多晶矽層34於 深溝渠中所能填入的有效空間，也因此造成電容頸部的阻值提 高，不利於記憶體的運作效能。 此外，在定義主動區域以及淺溝絕緣區域時，若稍有不對準情 形發生，即可能造成電容斷開，而無法與開關電晶體構成電連結。 再者，習知溝渠電容動態隨機存取記憶體的製作方法所採用的領 氧化層作法’在蝕刻淺溝絕緣區域時，造成蝕刻配方的困難度。 上述種種缺點皆使得習知溝渠電容動態隨機存取記憶體的製 作方法具有改善的空間。 1270179 【發明内容】 =此本《明之主要目的即在於提供—種綱的雜電容動離 隨機存取纖體㈣作方法，赌虹”知祕之問題。， «本發&較__ ’本發㈣赌魏容祕隨機存取 記憶體讀的方法包含有以下步驟：提供—半導體基底，於其上 形成觀塾層；於該襯墊層帽成—第-開Π ;以該襯錢作為餘 刻遮罩’經㈣第1 口在料導體基底侧出-麟；於該淺 溝中填入絕緣材料’軸—溝親_域；於該轉縣底上形 成一遮罩層，該遮罩層具有―第二開口，其暴露出部分該溝渠絕 緣區域以及部分該襯墊層；_遮罩層作為侧遮罩，經由該第 二開口姓刻該溝渠絕緣區域以及該襯塾層，形成—深溝渠；於該 深溝射形成深鮮電容；進行錄化製程，使觀溝渠電容之 、陳化成、、.S緣⑦氧層，去除該襯墊層，裸露出該半導體基底； :裸路出來的該半導體基底上形細極氧化層；以及於該間極氧 化層上形成—祕，同時於該職魏層上形成-穿越閘極。 根據本發狀錄實補，祕_深綠巾形縣溝渠電容 的方法尚包含有以下步驟：於該縣渠的_形成擴散區域，做 為溝渠電容之儲存雜；於絲溝渠_虹形成電容介電層； 以及在該深溝渠中形成摻雜多晶矽電容下電極。 為了使貝審查委員能更進一步了解本發明之特徵及技術内 12701791270179 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor process, and is a method relating to an all-state random access memory device. [Prior Art] Body, etc. = 3 small __ potential, such as __ memory specific 3 _ read _ also must be high-heavy, high-density Zhonggou Canal dynamic random access memory China) The component world's, ^ pain degree D let the architecture, which is based on the semiconductor base shot = fruit groove = then make a trench capacitor structure in the deep trench, so it can effectively reduce the size of the fe unit, and make good use of the wafer space. Please refer to Figure 1 to Figure _ for the mouth, which is a schematic cross-sectional view of a conventional dram unit for making a trench capacitor. First, as shown in Fig. i, a deep trench structure 11 is formed on the surface of the semiconductor substrate 10. The method of forming the deep trench structure u is to deposit the lining yttrium oxide layer 12, the lining tantalum nitride layer 14 and the borax glass layer 16 as an etching mask before the semiconductor substrate 1 surface, and then use the traditional yellow. Light and etching methods, such as reactive ion etching (RIE) techniques, complete the deep trench structure 11. As shown in FIG. 2, after removing the remaining borosilicate glass layer 16, an arsenic silicate glass (ASG) layer 22 is deposited on the inner wall of the deep trench structure 11 and on the nitrided layer 14 of the nitride layer. . Then, a 1270179 resistance is formed in the lower portion of the deep trench structure 11, and the light w trench structure n is coated on the 1G of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Next, the structure of the Shishen Shishi glass layer covered by the non-resistive layer 24 is removed to form the structure as shown in Fig. 2. The stencil is not subjected to a thermal diffusion process, and the doped arsenic in the arsenic bismuth glass layer 22 is buried, which serves as a thorium electrode. Subsequently, the photoresist layer 24 and the arsenic-based glass layer 22 are removed. ❿ 2, as shown in Figure 4, 'constructed on the inner wall of the deep trench heterostructure u—capacitor dielectric oxygen cut, nitrogen cut layer or oxidized ^ nitride oxide cut layer, then: and: form a first inside the U The polycrystalline germanium layer 29 has an upper surface lower than the substrate 10. According to the conventional technique, after the first polycrystalline layer is passed through the depressed side, its surface is below the subsequently formed collar oxide layer. Next, the capacitor dielectric layer covered by the spar layer 29 is shown in the figure below, and then a collar oxide layer 32 is formed on the inner wall of the deep trench structure 11 above the first polycrystalline layer 29, and then in the deep trench structure. A second polycrystalline layer 34 is formed within 11. The collar oxide layer 32 is first deposited by CVD with an oxide film and then re-etched. As shown in Fig. 6, the oxidized sound_base 10, which is not covered by the second polycrystalline layer 34, is then recessed over the deep trench structure „36 〇6 1270179 as shown in Fig. 7, then A third polysilicon layer 44 is formed in the recess 36. The upper surface of the third polycrystalline layer 44 is lower than the surface of the substrate 10. Subsequently, a chemical vapor deposition process is performed to deposit a boron dream glass on the semiconductor substrate. Layer 46, and filling the deep trench structure 11. As shown in Fig. 8, a yellow light process is then performed, and the shallow trench isolation (STI) region opening 50 and the active region outside the shallow trench isolation region are defined by the photoresist. The pattern of photoresist is then transferred to the underlying borosilicate glass layer 46 and the nitrided nitride layer 14 using anisotropic dry money. As shown in Fig. 9, the photoresist 48 and the ruthenium glass layer 46 are subsequently utilized. For the residual hard mask, shallow trench insulation is formed through the shallow trench insulating region opening % to the lower side rotating substrate (1), a portion of the third polycrystalline pin 44, a portion of the second polycrystalline rhyme, and a portion of the oxide layer & a region opening 52, thereby isolating the two-phase peak-channel capacitance. As shown in Figure 1 After removing the remaining glazing layer milk, a high-density plasma ruthenium oxide layer is filled in the opening 52 of the shallow kinetic region. Finally, as shown in Fig. 11, the ruthenium layer 14 serves as a polishing stop layer and has a thickness. Carrying out the chemical mechanical polishing process, using the nitrogen lining • the high-density silk Weihua layer 5 is ground to the pre-made method, which can be roughly summarized into the seven main stages of the conventional trench capacitor dynamic random access memory system. The order is as follows: 1. The deep trench etch phase; 2. The buried plate fabrication and the capacitor dielectric layer fabrication stage; 3. The deep trench first polysilicon layer deposition and recess etching phase; 4. The collar oxide layer fabrication Stage; 5; deep trench second polysilicon layer fabrication and recess etching phase; 6) deep trench third polysilicon layer fabrication and recess etching phase; and 7 · STI process. It can be seen that the conventional trench capacitor dynamic random The method of manufacturing the access memory is complicated, and it is necessary to carry out the deposition process of the polycrystalline germanium layer 29, 34 and 44 three times in succession, and then return the residual film to the remaining time (the recessed money). The area occupied by the capacitor element is reduced, and the thickness of the collar oxide layer has affected the effective space that the second polysilicon layer 34 can fill in the deep trench, thereby causing an increase in the resistance of the capacitor neck, which is disadvantageous to the memory. In addition, when defining the active area and the shallow trench insulation area, if a slight misalignment occurs, the capacitor may be disconnected and cannot be electrically connected to the switching transistor. Furthermore, the conventional trench capacitor dynamics The method of manufacturing a random access memory method uses a collar oxide layer method to cause difficulty in etching a recipe when etching a shallow trench isolation region. All of the above disadvantages result in a method for fabricating a conventional trench capacitor dynamic random access memory. Room for improvement. 1270179 [Summary of the Invention] = The main purpose of this "Ming's main purpose is to provide a class of hetero-capacitor-moving random access slimming (four) method, gambling "the problem of knowing secret.", «本发& __ The method of reading (four) betting Wei Rong secret random access memory includes the steps of: providing a semiconductor substrate on which a Guanlan layer is formed; and forming a liner layer into a first-opening; As the residual mask, the first port of the (4) is on the side of the material conductor base-lin; the shallow groove is filled with the insulating material 'axis-ditch parent' domain; a mask layer is formed on the bottom of the turn county. The mask layer has a second opening exposing a portion of the trench isolation region and a portion of the liner layer; the mask layer acts as a side mask through which the trench isolation region and the backing layer are pasted, Forming a deep trench; forming a deep fresh capacitor in the deep trench; performing a recording process to make the capacitor of the trench, the aging, and the S layer 7 oxygen layer, removing the liner layer, exposing the semiconductor substrate; a thin oxide layer on the semiconductor substrate that exits the road; and oxidation between the electrodes Formed on the layer - secret, at the same time formed on the Wei layer - through the gate. According to the hairline of the present issue, the secret _ dark green towel-shaped county channel capacitance method also includes the following steps: in the county channel _ Forming a diffusion region as a storage impurity of the trench capacitor; forming a capacitor dielectric layer in the wire trench _ rainbow; and forming a doped polysilicon capacitor lower electrode in the deep trench. In order to enable the Beck review committee to further understand the features of the present invention And technology within 1270179
容，請參閱以下有關本發明之詳細說明與附圖。然而所 供參考與辅助說明用，並非用來對本發明加以限制者。J k 【實施方式】 請參閱第圖至第30圖’其綠示的是本發明製作溝準電容 DRAM單元之剖面示意圖。首先，如第U圖所示，在半導^基底 1〇〇上形成墊氧化層102以及墊氮化石夕層1〇4。接著，在半導^基 #底100上形成淺溝絕緣區域106。本發明較佳實施例之主要特徵: 於先形成淺溝絕緣(STI-first)，此與習知技藝中完成溝渠電容之後 才作淺溝絕緣不同，而且本發明形成淺溝絕緣區域106之步驟盘 邏輯製程完全相容。 、 上述形成淺溝絕緣區域1〇6的方法包括先在墊氮化石夕層1〇4形 ，光阻層(圖未示）’該光阻層具有開口，暴露出淺溝絕緣區域，接 著經由該開口钱刻墊氮化石夕層1〇4,再利用墊氮化石夕層1〇4為侧 鲁遮罩’餘刻半導體基底·，形成淺溝1〇5，然後於淺溝⑽内填 j緣材料’例如以高密度電漿氣相沈積(HDPCVD)方法所沈積的 尚密度電私氧層’織再细魏切層m為研磨停止層， 以化學機械研磨方法將填入淺溝内的絕緣材料平坦化。 如第13圖所示，接著在平坦的半導體基底1〇〇上形成硬遮罩 再於硬遮罩層1〇8上形成抗反射層11〇，然後在抗反射層 I10上形成光阻層112。隨後，利用微影製程，於光阻層112中形 1270179 成開口 113，定義出深溝渠電容之位置。 如第14圖所不，接著利用光阻層m為侧抵擔層，以電槳 乾侧方式經由開σ 113向下_抗反㈣no以及硬遮罩層’ 將開口 113轉移至硬遮罩層1〇8甲，形成開口 115。此時， 開口 115暴露出部分的淺溝絕緣區域106以及部分的墊氮化石夕層 中如第15圖所示，繼續以乾餘刻方式經由開口 115向下飿刻所 暴路出來的、/¾溝絕緣區域彻以及墊氮化石夕層辦。由於墊氮化石夕 層104的綱率較慢，因此，開口 115所暴露出來的墊氮化石夕層 104僅有部分厚度被鱗，而乾侧在侧到淺溝絕緣區域祕 的底口M〇7後停止，形成如圖所示的階梯狀開口 。 接者，如第16圖所示，完全去除抗反射層11Q以及剩下的光 阻層112。如第π圖所示，再利用硬遮罩層應為蝕刻抵播層， 艇、、哭以乾餘刻方式經由開口 117向下餘刻墊氮化梦層以及半 導體基底100，形成階梯狀深溝渠119。 如第18圖所示，在半導體基底100上沈積摻雜矽玻璃層12()， 例如磷石夕玻璃(PSG)或者删石夕玻璃(BSG)。摻雜石夕玻璃層丨2〇覆蓋 在硬遮罩層108以及階梯狀深溝渠119的侧壁及底部。 11 1270179 ㈣娜質擴散到 擴散區域m係作麵^ 根據本發明德佳實施例， 電子或電洞。接著，如第19 =f#_t()ra—子 圖所示，去除摻雜矽玻璃層12〇。Please refer to the following detailed description of the invention and the accompanying drawings. However, the description and the accompanying description are not intended to limit the invention. J k [Embodiment] Referring to the drawings to Fig. 30, the green color is a schematic cross-sectional view of the trench capacitor DRAM cell of the present invention. First, as shown in Fig. U, a pad oxide layer 102 and a pad nitride layer 1〇4 are formed on the semiconductor substrate. Next, a shallow trench isolation region 106 is formed on the semiconductor substrate 100. The main features of the preferred embodiment of the present invention are: STI-first is formed first, which is different from shallow trench insulation after completion of trench capacitance in the prior art, and the steps of forming shallow trench isolation region 106 of the present invention The disk logic process is fully compatible. The method for forming the shallow trench isolation region 1〇6 includes first forming a nitride layer on the pad nitride layer, and the photoresist layer (not shown) has an opening to expose the shallow trench isolation region, and then The opening money is padded with a nitride layer of 1 〇4, and then a pad of nitride layer 〇1 is used as a side mask to form a 'semiconductor substrate', forming a shallow trench 1〇5, and then filling the shallow trench (10) The edge material 'for example, the high density plasma vapor deposition (HDPCVD) method, the density of the private oxygen layer 'weave fine layer' is a polishing stop layer, which is filled into the shallow trench by chemical mechanical polishing. The insulating material is flattened. As shown in FIG. 13, a hard mask is then formed on the flat semiconductor substrate 1 and an anti-reflective layer 11 is formed on the hard mask layer 1A, and then a photoresist layer 112 is formed on the anti-reflection layer I10. . Subsequently, using the lithography process, an opening 113 is formed in the photoresist layer 112 to define the location of the deep trench capacitor. As shown in Fig. 14, the photoresist layer m is used as a side resist layer, and the opening 113 is transferred to the hard mask layer by the open σ 113 downward _ anti-reverse (four) no and the hard mask layer 'in the dry side of the electric paddle. 1〇8A, forming an opening 115. At this time, the opening 115 exposes a portion of the shallow trench isolation region 106 and a portion of the pad nitride layer as shown in FIG. 15 , and continues to engrave the storm path through the opening 115 in a dry manner. 3⁄4 trench insulation area and pad nitride layer. Since the rate of the pad nitride layer 104 is slower, the pad nitride layer 104 exposed by the opening 115 has only a part of the thickness of the scale, and the dry side is at the bottom of the side to the shallow trench insulation region. After 7 stops, a stepped opening as shown is formed. As shown in Fig. 16, the anti-reflection layer 11Q and the remaining photoresist layer 112 are completely removed. As shown in the πth figure, the hard mask layer should be an etched layer, and the boat, crying, and the semiconductor substrate 100 can be padded through the opening 117 in a dry manner to form a stepped deep. Ditch 119. As shown in Fig. 18, a doped yttrium glass layer 12 (e.g., Phosphorus Glass (PSG) or Bakelite Glass (BSG) is deposited on the semiconductor substrate 100. The doped stone layer 丨 2 〇 covers the sidewalls and the bottom of the hard mask layer 108 and the stepped deep trench 119. 11 1270179 (4) The diffusion of the substance into the diffusion region m is a surface. According to the preferred embodiment of the invention, an electron or a hole. Next, as shown in the 19th = f#_t()ra- subgraph, the doped bismuth glass layer 12 is removed.
如第20圖所不’在階梯狀深溝渠 容介電層124，例如石夕氧-氮化石夕_層或者魏·氮切S (ΟΝΟ)層等。隨後，在半導體基底觸上沈積摻雜多嶋以， 且使摻雜多晶梦層126填滿階梯狀深溝渠ιΐ9。 如第21圖所示，利甩墊氮化石夕層1〇4為研磨停止層，進行化 學機械研磨(CMP)製程’研雜階梯狀深溝渠119外轉雜多晶石夕 層126以及硬遮罩層108，以形成平坦的半導體基底表面，而剩下 的摻雜多晶石夕層則在階梯狀深溝渠119構成電容下電極126a。 如第22圖所示，完成前述的CMP製程之後，隨後在半導體基 底1〇〇上形成光阻層132,其具有開口 133,暴露出兩相鄰的電容 下電極126a之間的淺溝絕緣區域106。隨後利用乾蝕刻方式經 由開口 133向下蝕刻預定厚度的淺溝絕緣區域1〇6，使剩下的淺溝 絶緣£域106的上表面低於半導體基底1〇〇的表面(此表面指的是 半導體基底100與墊氧化層102之界面），形成凹陷開口 。然 後，去除光阻層132。 12 1270179 如第23圖所示，接著進行第二次的多秘化學氣相 在半導體基細上沈積摻雜多_ 136，錢晶 136填滿凹陷開口 135。 如第^圖所示’接著利用墊氮化石夕層1〇4為研磨停止層，進 订第一欠的CMP製程，掉凹陷開口 135外的推雜多晶石夕層 136以減平坦的半導體基底表面，而後入凹陷開口出内纖 鲁之掺雜多晶石夕層貝幡成電連接兩轉的電容下電極服的導電帶 腕。此時，電容下電極126a的上麵解錄挪的上表面位 於同一平面上。 如第25 ®所示，接著進彳鴻職程，將電容下電極126a以 及導電帶施的上表面回钱刻至預絲度，在電容下電極126a 以及導電帶136a上形成凹陷開口 137。 如第26圖所不，接著進行熱氧化製程，例如爐管氧化法，將 暴露在凹關口 137内的電容下電極伽以及導電帶職的上 表面以熱祕轉成厚歧少切觸埃找雜氧層14〇。 此外’在本發明之另—實施财，亦可以洲化學氣相沈積 法’渐高密度電漿化學氣相沈積法，在半導體基底觸上沈殿 再利㈣氮切層辦為研磨停止層，以化學機 械研磨CVD⑪氧層’或再搭配回磁彳方法回細彳該⑽夕氧層 13 1270179 开> 成同樣位於溝渠電容上部的絕緣石夕氧層14〇。 如第27圖所示，在完成前述的熱氧化製程後，接著再以钱刻 方式依序去除墊氮切層刚以及墊氧化層搬，裸露出半導體基 底100。如第28圖所示，接著進行熱氧化製程，在裸露出來的半 導體基底1〇〇上成長厚約1()至50埃左右的舰氧化層142。本發 明之另一特«於絕緣石夕氧層14〇的厚度(大於1〇〇埃)比間極氧化 層H2的厚度(約1〇至5〇埃)更厚，藉此避免電容漏電流的問題。 如第29圖所不，接下來在閘極氧化層142上形成閉極⑽以 及閘極156，同時，在絕緣石夕氧層14〇上形成穿越間極細_ gate)152以及154。其中，穿越閘極152以及154恰好分別對準在 溝渠電容結構202及204正上方，而閘極15〇以及閘極156則分 別設在溝渠電容結構202及204的一侧。 此外’在閘極150相對於溝渠電容結構2〇2另一侧的半導體基 底100中形成有汲極/源極換雜區域164，而在閘極156相對於溝 渠電容結構204另一侧的半導體基底1〇〇中形成有汲極/源極摻雜 區域166。上述的閘極以及穿越閘極，可包含有多晶矽層、矽化金 屬層、氮化矽蓋層以及閘極側壁子。 如第30圖所示，最後再於半導體基底10〇上沈積介電層168， 然後於介電層168中形成接觸插塞182、184以及186，其中接觸 14 1270179 插塞182穿過穿越閘極152以及154之間，且貫穿絕緣石夕氧層 140，與導電帶136a電連結，而接觸插塞184與汲極/源極摻雜區 域164電連結，接觸插塞186與汲極/源極摻雜區域166電連結。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第11圖繪示的是習知製作溝渠電容DRAM單元之剖 面示意圖。 第π圖至第3〇圖繪示的是本發明製作溝渠電容DRAM單元 之剖面示意圖。 【主要元件符號說明】 10 半導體基底 11 深溝渠結構 12 襯氧化矽層 14 襯氮化石夕層 16 硼矽玻璃層 22 ASG層 24 光阻層 25 埋入電盤 27 電容介電層 29 第一多晶石夕層 32 領氧化層 34 弟'一多晶發層 36 凹口 44 第三多晶石夕層 46 硼矽玻璃層 48 光阻層 50 淺溝絕緣區域開口 52 淺溝絕緣區域開 15 1270179 56 高密度電漿矽氧化層 100 半導體基底 102 墊氧化層 104 墊氮化矽層 105 淺溝 106 淺溝絕緣區域 107 底部 108 硬遮罩層 110 抗反射層 112 光阻層 113 開口 115 開口 117 開口 119 階梯狀深溝渠 120 摻雜矽玻璃層 122 擴散區域 124 電容介電層 126 摻雜多晶矽層 126a 電容下電極 132 光阻層 133 開口 135 凹陷開口 136 換雜多晶砍層 136a 導電帶 137 凹陷開口 140 絕緣矽氧層 142 閘極氧化層 150 閘極 152 穿越閘極 154 穿越閘極 156 閘極 164 >及極/源極換雜區域 166 波才盈/源極換雜區域 168 介電層 182 接觸插塞 184 接觸插塞 186 接觸插塞 202 溝渠電容 204 溝渠電容 16As shown in Fig. 20, the dielectric layer 124 is formed in a stepped deep trench, such as a Shiyue oxygen-nitridinium layer or a Wei Nitrogen S (ΟΝΟ) layer. Subsequently, a doped polysilicon is deposited on the semiconductor substrate contact, and the doped polycrystalline dream layer 126 is filled with a stepped deep trench ΐ9. As shown in Fig. 21, the Lithium Nitride lining layer 1〇4 is a polishing stop layer, and a chemical mechanical polishing (CMP) process is performed to grind the stepped deep trench 119 and turn the heteropolycrystalline layer 126 and the hard cover. The cap layer 108 is formed to form a flat surface of the semiconductor substrate, and the remaining doped polysilicon layer forms a capacitor lower electrode 126a in the stepped deep trench 119. As shown in FIG. 22, after the foregoing CMP process is completed, a photoresist layer 132 is formed on the semiconductor substrate 1b, which has an opening 133 exposing the shallow trench isolation region between the two adjacent capacitor lower electrodes 126a. 106. Then, a shallow-thickness insulating region 1〇6 of a predetermined thickness is etched downward through the opening 133 by dry etching, so that the upper surface of the remaining shallow trench insulating region 106 is lower than the surface of the semiconductor substrate 1〇〇 (this surface refers to The interface between the semiconductor substrate 100 and the pad oxide layer 102) forms a recessed opening. Then, the photoresist layer 132 is removed. 12 1270179 As shown in Fig. 23, a second polysulfide chemical vapor phase is then applied to deposit a doping _ 136 on the semiconductor substrate fine, and the crystal 136 fills the recess opening 135. As shown in FIG. 4, 'the next step of the CMP process is performed by using the pad nitride layer 1〇4 as the polishing stop layer, and the doped polysilicon layer 136 outside the recess opening 135 is removed to flatten the semiconductor. The surface of the substrate, and then into the recessed opening, the doped polycrystalline stone layer of the inner fiber is electrically connected to the conductive belt wrist of the capacitor of the second electrode. At this time, the upper surface of the upper surface of the capacitor lower electrode 126a is located on the same plane. As shown in the 25th®, the capacitor lower electrode 126a and the upper surface of the conductive tape are etched into the pre-filament, and a recessed opening 137 is formed in the capacitor lower electrode 126a and the conductive strip 136a. As shown in Fig. 26, a thermal oxidation process, such as a furnace tube oxidation method, is performed to expose the upper electrode of the capacitor exposed in the recess 137 and the upper surface of the conductive belt to a thicker and less tangible contact. The heteroxia layer is 14 〇. In addition, in the invention of the invention - the implementation of the fiscal, can also be the chemical vapor deposition of the 'gradual high-density plasma chemical vapor deposition method, on the semiconductor substrate touched Shen Dianli (4) nitrogen cutting layer as a grinding stop layer, The chemical mechanical polishing CVD11 oxygen layer 'or recombined with the magnetic enthalpy method to refine the (10) oxime layer 13 1270179 open > into the insulating oxide oxide layer 14 同样 also located in the upper part of the trench capacitor. As shown in Fig. 27, after the above thermal oxidation process is completed, the pad nitride layer and the pad oxide layer are sequentially removed in a random manner to expose the semiconductor substrate 100. As shown in Fig. 28, a thermal oxidation process is then carried out to grow a ship oxide layer 142 having a thickness of about 1 (?) to about 50 angstroms on the exposed semiconductor substrate. Another thickness of the present invention is thicker than the thickness of the inter-pole oxide layer H2 (about 1 〇 to 5 〇 Å), thereby avoiding leakage current of the capacitor. The problem. As shown in Fig. 29, a closed electrode (10) and a gate 156 are formed on the gate oxide layer 142, and a pass-through _ gate 152 and 154 are formed on the insulating oxide layer 14A. Wherein, the crossing gates 152 and 154 are respectively aligned directly above the trench capacitor structures 202 and 204, and the gate 15〇 and the gate 156 are respectively disposed on one side of the trench capacitor structures 202 and 204. In addition, a drain/source replacement region 164 is formed in the semiconductor substrate 100 on the other side of the gate 150 with respect to the trench capacitor structure 2〇2, and a semiconductor on the other side of the gate capacitor 156 is opposite to the trench capacitor structure 204. A drain/source doped region 166 is formed in the substrate 1 . The gate and the crossing gate may include a polysilicon layer, a deuterated metal layer, a tantalum nitride cap layer, and a gate sidewall. As shown in FIG. 30, a dielectric layer 168 is finally deposited over the semiconductor substrate 10, and then contact plugs 182, 184, and 186 are formed in the dielectric layer 168, wherein the contacts 14 1270179 plug 182 pass through the gate Between 152 and 154, and through the insulating oxide layer 140, electrically connected to the conductive strip 136a, and the contact plug 184 is electrically coupled to the drain/source doped region 164, the contact plug 186 and the drain/source The doped regions 166 are electrically connected. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. 11 are schematic cross-sectional views showing a conventional trench capacitor DRAM cell. Fig. π to Fig. 3 are schematic cross-sectional views showing the fabrication of the trench capacitor DRAM cell of the present invention. [Main component symbol description] 10 Semiconductor substrate 11 Deep trench structure 12 Lining ruthenium oxide layer 14 Lined with nitride layer 110 Boron glass layer 22 ASG layer 24 Photoresist layer 25 Buried electric disk 27 Capacitor dielectric layer 29 First polycrystalline Shi Xi layer 32 collar oxide layer 34 brother 'a polycrystalline layer 36 notch 44 third polycrystalline layer 46 boron germanium glass layer 48 photoresist layer 50 shallow trench insulation region opening 52 shallow trench insulation region open 15 1270179 56 High-density plasma tantalum oxide layer 100 semiconductor substrate 102 pad oxide layer 104 pad nitride layer 105 shallow trench 106 shallow trench insulating region 107 bottom 108 hard mask layer 110 anti-reflective layer 112 photoresist layer 113 opening 115 opening 117 opening 119 Stepped deep trench 120 doped yttrium glass layer 122 diffusion region 124 capacitor dielectric layer 126 doped polysilicon layer 126a capacitor lower electrode 132 photoresist layer 133 opening 135 recessed opening 136 modified polycrystalline chopping layer 136a conductive strip 137 recessed opening 140 Insulating buffer layer 142 gate oxide layer 150 gate 152 crossing gate 154 crossing gate 156 gate 164 > and pole/source replacement area 166 wave only / source replacement The contact field 168 of the dielectric layer 182 in contact with plug 184 plug contacts 186 of the plug 202 trench capacitor 204 trench capacitor 16