1287858 九、發明說明 【發明所屬之技術領域】 本發明是有關於一種單一電晶體隨機存取記憶晶胞 (Single Transistor Random Access Memory Cell； 1T-RAM) 之電容器的製造方法，且特別是有關於一種可改善電容器 空乏（Depletion)之單一電晶體隨機存取記憶晶胞之電容 器的製造方法。 【先前技術】 在積體電路元件尺寸之微縮化趨勢下，導致元件内之 電容器的尺寸也受到限制。為了提升積體電路元件之電 容，目前大都是利用增加電容器之面積的方式，來提高電 容器之電容。 請參照第1圖至第6圖，第1圖至第6圖係繪示習知 單一電晶體隨機存取記憶晶胞之電容器的製程剖面圖。一 般製作單一電晶體隨機存取記憶晶胞之電容器時，首先係 提供由石夕（Silicon)所組成之基材1 00。再利用熱氧化的方 式形成薄薄的一層塾氧化層（Pad Oxide Layer) 102覆蓋在 基材100上，並沉積一層厚度約1千多A之硬罩幕層（Hard Mask Layer)104覆蓋在墊氧化層102上。其中，硬罩幕層 104之材質一般為氮化石夕（Silicon Nitride)，墊氧化層102 可使硬罩幕層1 04順利地沉積在基材1 00上，而硬罩幕層 104可在後續之製程中保護底下之基材100。待硬罩幕層 104形成後，利用微影與蝕刻製程進行溝渠106之定義， 1287858 而將溝渠圖案轉移至硬罩幕層1〇4、墊氧化層1〇2、以及 基材100中，而形成溝渠106。其中，溝渠1〇6之區域又 ‘ 可稱為隔離區，溝渠106旁之區域通常為主動區。溝渠 w 1〇6形成後，以熱氧化的方式於溝渠106所暴露之基材1〇〇 表面上形成一層薄薄的襯氧化層（Uning 〇xide Layer)108，以在後續之介電層11〇沉積過程中，保護基 材100表面免於損傷。於襯氧化層108形成後，沉積介電 層110覆蓋在墊氧化層102、硬罩幕層104、以及襯氧化 層108上，並填滿溝渠106，而形成如第i圖所示之結構。 接下來’以化學機械研磨（Chemical Mechanical Polishing; CMP)的方式移除部分之介電層11〇，直至暴露 出硬罩幕層104為止，並僅剩下溝渠1〇6内之介電層 110。此時，形成罩幕層112覆蓋在硬罩幕層1〇4與介電 層110上，其中罩幕層112之材質為光阻。先利用微影技 術將電容器區域的圖案轉移至罩幕層112中，而暴露出部 分之硬罩幕層1 04與部分之介電層1 i 〇。再利用蝕刻技術 _ 去除溝渠106中部分之介電層110以及部分之襯氧化層 108，而形成開口 114並暴露出溝渠106側壁區之基材 ·- 100，所形成之結構如第2圖所示。為確保硬罩幕層1〇4 、 上之介電層110能完全磨除，大都會進行適度的過度研 磨，如此硬罩幕層104之厚度會從原來之1千多A降低 至約600A與800A之間。在元件陣列邊緣之硬罩幕層1〇4 的厚度甚至會減低至1〇〇 A與200A之間。此外，在蝕刻 過程中’暴露出之硬罩幕層1 04也會受到輕微餘刻，而使 1287858 • 此部分之硬罩幕層104的厚度減低。 凡成電谷器區域之定義後，為避免後續之熱處理製程 、影響草幕層112之移除，此時需先將罩幕層112予以去 、除待罩幕層112去除後，先以熱處理方式於溝渠ι06 中暴路之基材100表面上覆蓋一層犧牲層（Sacrificial Layer)ll6。由於，硬罩幕& m經研磨後，其厚度大幅 '、特別疋位於電容器區域之硬罩幕層1〇4之厚度變得 φ ，薄。為避免在離子植入過程中傷害基材100，因此利用 微影技術再額外形成罩幕層118位於硬罩幕層1〇4上，以 在後續之離子植入過程中保護主動區之基材1〇〇。此時， 即可利用離子植入技術將離子12〇植入犧牲層116側邊之 基材100中，而於溝渠106之電容器區域的基材1〇〇中形 成摻雜區122，如第3圖所示。 請參照第4圖，完成電容器區域之摻雜區122的佈植 後，先移除罩幕層118，再移除硬罩幕層1〇4、墊氧化層 102、以及犧牲層116，而暴露出基材1〇〇表面。隨後， 形成犧牲層124覆蓋在基材100表面，以保護基材1〇〇 表面不文後續離子植入的傷害。再利用離子植入技術將離 子126植入主動區之基材1〇〇中，而在基材中形成井 、 （We 11)區（未繪示）。 然後，先移除犧牲層124，而再次暴露出基材1〇〇表 面。再利用熱氧化方式形成閘極氧化層128覆蓋在基材 10 0表面上。閘極乳化層12 8形成後，沉積導電材料層（僅 繪示其中之導電層13〇以及導電層132)覆蓋在閘極氧化 1287858 層12 8以及介電層11 〇上，並填滿開口 1丨4。再利用微影 與蝕刻技術定義此導電材料層以及閘極氧化層128，而在 主動區之閘極氧化層128上形成導電層13〇，且在位於部 分之溝渠106與部分之主動區上之電容器區域形成導電 層132，並暴路出部分之基材1〇〇，而形成如第5圖所示 之結構。其中，導電層130可做為閘極，而導電層j32 可做為電容器之電極。而導電層132、導電層132下之閘 極氧化層128、以及導電層132下之基材1〇〇構成電容器。 然後，以離子植入的方式於導電層以及導電層 132旁之基材100中形成輕摻雜區（LDD)138。再利用沉積 以及回#刻技術於導電層1 3 〇側壁形成間隙壁13 4，且於 導電層13 2侧壁形成間隙壁13 6。待間隙壁1 3 4與間隙壁 136形成後，利用離子植入方式於導電層13〇兩旁之基材 100中形成汲極140與源極142，而形成如第6圖所示之 結構。此時，已完成單一電晶體隨機存取記憶晶胞之電容 器的製作。 【發明内容】 鑒於上述習知製作單一電晶體隨機存取記憶晶胞之 電谷器時，在進行溝渠外多餘之介電層的研磨後，硬罩幕 層厚度大幅減少，尤其是位於電容器區域之硬罩幕層之厚 度變得更薄。如此一來，硬罩幕層之厚度不足以抵擂後續 離子植入的衝擊，而需再額外形成離子植入之罩幕，故會 導致整體製程之複雜度提高，並造成製程成本增加。 Ϊ287858 、 因此，本發明之目的就是在提供一種單一電晶體隨機 存取記憶晶胞之電容器的製造方法，其係在完成溝渠之隔 離材料層的沉積後，先不進行隔離材料層之研磨移除步 、 驟，而是直接進行電容器區域之定義。並且，於暴露出之 溝渠侧壁上形成犧牲層。由於，隔離材料層與其底下之硬 罩幕層未經研磨，所以具有足夠之厚度來抵擋離子植入的 衝擊。因此，可利用未經研磨之隔離材料層、其底下之硬 鲁 罩幕層、以及犧牲層作為離子植入的罩幕。如此，可省下 一道離子植入之罩幕的佈植程序，而降低製程成本。 本發明之另一目的是在提供一種單一電晶體隨機存 取記憶晶胞之電容器的製造方法，可將電容器之區域擴展 至溝渠側壁之一部分。因此，可充分利用溝渠側壁之一部 分來作為電容器，而可提高記憶晶胞之積集度，進而可輕 易縮減記憶晶胞之尺寸。 本發明之又一目的是在提供一種單一電晶體隨機存 取記憶晶胞之電容器的製造方法，可與記憶晶胞之邏輯製 _程相容，製程簡單易於施行。 根據本發明之上述目的，提出一種單一電晶體隨機存 " 取記憶晶胞之電容器的製造方法，至少包括下列步驟：首 ^ 先提供一基材，其中此基材上至少覆蓋有依序堆疊之一墊 氧化層以及一硬罩幕層，且至少一溝渠形成於基材、墊氧 化層、與硬罩幕層中，而另一部分之基材上方則形成一主 動區。再形成一介電層覆蓋在上述之硬罩幕層以及溝渠所 暴硌之基材上，並填滿溝渠。接下來，定義上述之介電層， 1287858 並暴露出溝渠之一側壁區以及部分之硬罩幕層，而在部分 之溝渠以及部分之主動區上形成一電容器區域。再形成一 第一犧牲層覆蓋在上述溝渠之側壁區上。之後，進行一第 一離子植入步驟，而在電容器區域之基材中形成一摻雜 區。接著，利用研磨方式移除部分之介電層，直至暴露出 硬罩幕層為止。再移除第一犧牲層、硬罩幕層、以及墊氧1287858 IX. Description of the Invention [Technical Field] The present invention relates to a method for manufacturing a capacitor of a Single Transistor Random Access Memory Cell (1T-RAM), and in particular A method of fabricating a capacitor of a single transistor random access memory cell capable of improving capacitor depletion. [Prior Art] In the trend of miniaturization of the size of integrated circuit components, the size of capacitors in the components is also limited. In order to increase the capacitance of integrated circuit components, it is currently common to increase the capacitance of the capacitor by increasing the area of the capacitor. Referring to Figures 1 through 6, Figures 1 through 6 are schematic cross-sectional views showing a capacitor of a conventional single crystal random access memory cell. When a capacitor of a single transistor random access memory cell is generally fabricated, a substrate 100 consisting of a silicon is first provided. Then, a thin layer of a pad oxide layer (Pad Oxide Layer) 102 is formed on the substrate 100 by thermal oxidation, and a hard mask layer 104 having a thickness of about 1,000 A is deposited on the pad. On the oxide layer 102. Wherein, the material of the hard mask layer 104 is generally Silicon Nitride, and the pad oxide layer 102 can smoothly deposit the hard mask layer 104 on the substrate 100, and the hard mask layer 104 can be subsequently The underlying substrate 100 is protected during the process. After the hard mask layer 104 is formed, the definition of the trench 106 is performed by a lithography and etching process, 1287858, and the trench pattern is transferred to the hard mask layer 1〇4, the pad oxide layer 1〇2, and the substrate 100, and A trench 106 is formed. Among them, the area of the trench 1〇6 may be referred to as an isolation area, and the area beside the trench 106 is usually an active area. After the trench w 1〇6 is formed, a thin oxide layer (Uning 〇xide Layer) 108 is formed on the surface of the substrate 1 exposed by the trench 106 by thermal oxidation to form the dielectric layer 11 in the subsequent dielectric layer 11 During the deposition of the crucible, the surface of the substrate 100 is protected from damage. After the liner oxide layer 108 is formed, the deposited dielectric layer 110 overlies the pad oxide layer 102, the hard mask layer 104, and the liner oxide layer 108, and fills the trench 106 to form the structure as shown in FIG. Next, a portion of the dielectric layer 11 is removed by chemical mechanical polishing (CMP) until the hard mask layer 104 is exposed, and only the dielectric layer 110 in the trenches 1〇6 is left. . At this time, the mask layer 112 is formed to cover the hard mask layer 1〇4 and the dielectric layer 110, wherein the mask layer 112 is made of photoresist. The pattern of the capacitor region is first transferred to the mask layer 112 by lithography, and a portion of the hard mask layer 104 and a portion of the dielectric layer 1 i 暴露 are exposed. The etching process is further removed _ removing part of the dielectric layer 110 and part of the lining oxide layer 108 of the trench 106 to form the opening 114 and exposing the substrate - 100 of the sidewall region of the trench 106. The structure formed is as shown in FIG. Show. In order to ensure that the hard mask layer 1〇4 and the upper dielectric layer 110 can be completely removed, the metropolis will be moderately over-grinded, so that the thickness of the hard mask layer 104 will be reduced from the original thousand A to about 600A. Between 800A. The thickness of the hard mask layer 1〇4 at the edge of the array of elements is even reduced to between 1 〇〇A and 200A. In addition, the exposed hard mask layer 104 will also be slightly retouched during the etching process, resulting in a reduction in the thickness of the hard mask layer 104 of this portion. After the definition of the electric grid region, in order to avoid the subsequent heat treatment process and affect the removal of the grass layer 112, the mask layer 112 is first removed, and the mask layer 112 is removed, and then heat treated. The surface of the substrate 100 in the trench ι06 is covered with a sacrificial layer ll6. Since the hard mask & m is polished, the thickness of the hard mask layer 1〇4 which is large in thickness, especially in the capacitor region, becomes φ, thin. In order to avoid damage to the substrate 100 during ion implantation, an additional mask layer 118 is formed on the hard mask layer 1〇4 by lithography to protect the active region substrate during subsequent ion implantation. 1〇〇. At this time, the ion implantation can be implanted into the substrate 100 on the side of the sacrificial layer 116 by ion implantation, and the doped region 122 is formed in the substrate 1〇〇 of the capacitor region of the trench 106, such as the third. The figure shows. Referring to FIG. 4, after the implantation of the doped region 122 of the capacitor region is completed, the mask layer 118 is removed, and then the hard mask layer 1〇4, the pad oxide layer 102, and the sacrificial layer 116 are removed, and exposed. The surface of the substrate 1 is removed. Subsequently, a sacrificial layer 124 is formed to cover the surface of the substrate 100 to protect the substrate from the surface damage caused by subsequent ion implantation. The ion implantation technique is then used to implant the ions 126 into the substrate 1 of the active region to form a well, (We 11) region (not shown) in the substrate. Then, the sacrificial layer 124 is removed first, and the substrate 1 surface is again exposed. A gate oxide layer 128 is formed on the surface of the substrate 10 by thermal oxidation. After the gate emulsification layer 12 8 is formed, a layer of a conductive material (only the conductive layer 13 〇 and the conductive layer 132 are shown) is overlaid on the gate oxide 1287858 layer 12 8 and the dielectric layer 11 ,, and fills the opening 1丨 4. The conductive material layer and the gate oxide layer 128 are defined by lithography and etching techniques, and the conductive layer 13 is formed on the gate oxide layer 128 of the active region, and is located on a portion of the trench 106 and a portion of the active region. The capacitor region forms a conductive layer 132 and ruptures a portion of the substrate 1 to form a structure as shown in FIG. Wherein, the conductive layer 130 can serve as a gate, and the conductive layer j32 can serve as an electrode of the capacitor. The conductive layer 132, the gate oxide layer 128 under the conductive layer 132, and the substrate 1 under the conductive layer 132 constitute a capacitor. A lightly doped region (LDD) 138 is then formed in the substrate 100 adjacent to the conductive layer and conductive layer 132 by ion implantation. The spacers 13 4 are formed on the sidewalls of the conductive layer 13 by the deposition and back-etching techniques, and the spacers 13 6 are formed on the sidewalls of the conductive layer 132. After the spacers 134 and the spacers 136 are formed, the drain 140 and the source 142 are formed in the substrate 100 on both sides of the conductive layer 13 by ion implantation to form a structure as shown in Fig. 6. At this time, the fabrication of a capacitor of a single transistor random access memory cell has been completed. SUMMARY OF THE INVENTION In view of the above-described conventional fabrication of a single transistor random access memory cell, the thickness of the hard mask layer is greatly reduced after the grinding of the excess dielectric layer outside the trench, especially in the capacitor region. The thickness of the hard mask layer becomes thinner. As a result, the thickness of the hard mask layer is insufficient to resist the impact of subsequent ion implantation, and an additional ion implantation mask is required, which leads to an increase in the complexity of the overall process and an increase in process cost. Ϊ 287858. Accordingly, it is an object of the present invention to provide a method of fabricating a capacitor for a single transistor random access memory cell that does not perform a polishing removal of the isolation material layer after the deposition of the isolation material layer of the trench is completed. Steps and steps, but directly define the capacitor area. Also, a sacrificial layer is formed on the exposed sidewalls of the trench. Since the layer of insulating material and the underlying hard mask layer are not ground, they are of sufficient thickness to withstand the impact of ion implantation. Thus, an unground layer of insulating material, a hard mask layer underneath, and a sacrificial layer can be utilized as a mask for ion implantation. In this way, the implantation process of the ion implantation mask can be saved, and the process cost can be reduced. Another object of the present invention is to provide a method of fabricating a capacitor for randomly accessing a memory cell from a single transistor, which extends the area of the capacitor to a portion of the sidewall of the trench. Therefore, a part of the side wall of the trench can be fully utilized as a capacitor, and the accumulation of the memory cell can be improved, and the size of the memory cell can be easily reduced. Another object of the present invention is to provide a method for manufacturing a capacitor for randomly accessing a memory cell in a single transistor, which is compatible with the logic process of the memory cell, and the process is simple and easy to implement. According to the above object of the present invention, a method for manufacturing a capacitor for a single transistor random access memory cell is provided, comprising at least the following steps: first providing a substrate, wherein the substrate is covered with at least sequential stacking A pad oxide layer and a hard mask layer, and at least one trench is formed in the substrate, the pad oxide layer, and the hard mask layer, and another portion of the substrate forms an active region. A dielectric layer is formed over the hard mask layer and the substrate on which the trench is turbulent, and fills the trench. Next, the dielectric layer described above is defined, 1287858 and a sidewall region of the trench and a portion of the hard mask layer are exposed, and a capacitor region is formed on a portion of the trench and a portion of the active region. A first sacrificial layer is formed over the sidewall region of the trench. Thereafter, a first ion implantation step is performed to form a doped region in the substrate of the capacitor region. Next, a portion of the dielectric layer is removed by grinding until a hard mask layer is exposed. Removing the first sacrificial layer, the hard mask layer, and the pad
化層，而暴露出基材以及溝渠之側壁區。然後，形成一第 二犧牲層覆蓋在基材以及溝渠之側壁區上。再進行一第二 離子植入步驟，藉以在上述之主動區之基材中形成一= 區。待井區形成後，移除第二犧牲層。此時，可先形成一 閘極介電層覆蓋在基材以及溝渠之側壁區。再形成一閘極 以及-電極層，其中閘極位於部分之主動區上方之閘極介 電層上’且電極層位於電容器區域上。 依照本發明一較佳實施例，第一離子植入步驟係以介 電層、暴露出之硬罩幕層、以及第—犧牲層為罩幕。此外， 於移除部分之介電層直至暴露出硬罩幕層時，可先於介電 層、第-犧牲層、以及暴露之硬罩幕層上形成例如由光阻 構成之覆蓋層，以提供平坦之研磨表面，並避免研磨喂 (训叫進人電容器區域而造成基材與溝渠内之介電層的 傷害。 本發明在完成溝渠之介電層的沉積與填充後， 仃介電層之研磨，而直接定義電容器區域。因此， "電層以及硬罩幕層均未經研磨的情況下，硬罩幕層之 厚度獲得有效維持，而可直接利用介電層、硬罩幕層:以 10 1287858 及後續形成之第一犧牲層來作為第一離子植入步驟時的 罩幕。故，在第一離子植入步驟時，不需額外製作罩幕， 可簡化製程，進而達到降低製程成本的目的。 【實施方式】 本發明揭露一種單一電晶體隨機存取記憶晶胞之電 容器的製造方法，不需額外之罩幕即可順利進行溝渠侧壁 之電容器區域的離子植入，而有效解決電容器空乏的問 題。因此，可省卻製作離子植入之罩幕的步驟，降低製程 成本。為了使本發明之敘述更加詳盡與完備，可參照下列 描述並配合第7圖至第14圖之圖示。 請參照第7圖至第14圖，第7圖至第14圖係繪示依 照本發明一較佳實施例的一種單一電晶體隨機存取記憶 曰曰胞之電谷器的製程剖面圖。本發明之單一電晶體隨機存 取記憶晶胞之電容器的製作，首先提供半導體材料所組成 之基材200，其中基材2〇〇之材質較佳為矽。再利用例如 熱氧化的方式形成墊氧化層202覆蓋在基材200上。其 中，墊氧化層202之材質較佳為氧化矽（Silicon Oxide)， /塾氧化層202之厚度相冑薄。完成塾氧化& 2〇2之成長 後，利用例如化學氣相沉積（Chemical Vapor Depositi〇n ; :VD)的方式形成硬罩幕層2〇4覆蓋在墊氧化層加上。 其中’硬罩幕層204之材質較佳為氮切。因為由例如氮 化石夕所組成之硬罩幕層2()4對基材綱之附著力不佳，因 此在沉積硬罩幕層2〇4前，先於基材表面上覆蓋一層 1287858 薄薄的墊氧化層202,來使硬罩幕屛〇Λ>| & 干带增204能順利地覆蓋在 基材200上。 在 硬罩幕層2〇4形成後’利用例如料 J如倣影與蝕刻技術進行 溝渠圖案之定義，而去除部分之硬著莖 %旱幕層204、墊氧化芦 202、以及基材200,進而在硬罩幕屉 曰 ’ 204、墊氧化層202、 以及基材200中形成溝渠206。龙ψ 、致、s 〜中，溝渠206所在之區 域可稱為隔離區，而溝渠206外之f a 域又可稱為主動區。 待溝渠206形成後，利用例如熱氧 ^ H ^ . ^ LL 匕的方式於溝渠206 所暴露出之基材200上形成厚度相者 々曰田溥之襯氧化層208 〇 其中，襯氧化層208可用以在後續夕人+ β 丄 、 員之介電層210沉積過程 中’保護溝渠206内之基材2〇〇表面甘 表面。其中，襯氧化層 208之材質可為氧化石夕。此時，即可利用例如高密度電t 化學氣相沉積（High Density Plasma c仰；HDpcvD)技術 形成介電層210覆蓋在硬罩幕層 „ yi ^ 續204、塾氧化層202、襯 氧化層208上，並填滿溝渠2〇6， ^ ^ 阳形成如第7圖所示之 參 、‘構。其中，介電層210之材質可為氧化矽。 接下來，利用例如旋塗r · …蓋在介電層21。上，= 為光阻。此時，先利用例如微影 ：一12之材質較佳 ^ s ^ ^ 倣〜技術將電容器區域之圖案 轉移至罩幕層212中，而暴露中邮八 ..^ 〇 , 恭路出邛分之介電層210。再以 罩幕層212為蝕刻罩幕，利用你丨^』 夕八扪用例如乾式蝕刻技術移除部分 之，丨電層210以及部分之襯氧 F H ^ ^ 0a 曰2〇8 ’而疋義出電容器 區域，並形成開口 214暴露出溝準 再 06側壁的一部分以及 硬罩幕層204之一部分。水钟Θ % ^ 也就疋說，電容器區域除了位於 12 1287858 主動區之硬罩幕層204上外，也位於溝渠2〇6之部分伽 上。因此，隨著電容器區域擴展至溝渠2〇6之二則壁 上，電容器所能提供之電容會增加。在定義電容器。雙 時，暴露之硬罩幕層204會受到些微損傷，而形成如品域 圖所示之結構。 第8 完成電容器區域之定義後，為避免後續之熱處理程 的高溫影響罩幕層212之移除，於是先利用例如韌陝 (Strip)的方式移除罩幕層212。再利用例如熱氧化的方^ 於溝渠206暴露之側壁區的基材2〇〇表面上形成犧牲= 216,其中犧牲層216之厚度較佳是控制在介於ι〇Α ^ 300A之間，且犧牲層216之材質較佳為氧化矽。待犧牲 層216形成後，即可利用例如離子植入的方式，以介電層 210、硬罩幕層204 '以及犧牲層216做為罩幕，將離^ 215植入溝渠206之為犧牲層216所覆蓋之側壁區的基材 200中，而形成摻雜區218，如第9圖所示。其中，摻雜 區218可改善電容器空乏的現象。 多’、 本發明之一特徵就是因為介電層21〇以及硬罩幕層 2〇4未經研磨，因此硬罩幕層204之厚度得以維持，而二 足夠的能力來保護底下之基材200免受離子植入的傷 。。如此一來，不需另外再製作離子植入的罩幕結構，即 可直接利用原有之介電層210與硬罩幕層204來當作離子 植入之罩幕結構。&，可簡化製程步驟，進而降低製程成 本。 換雜區218形成後，可以例如化學機械研磨的技術， 13 1287858 • 直接磨除溝渠206外之介電層21〇,直至暴露出硬罩幕層 204為止。然，在本發明之一較佳實施例中，為避免研磨 : 過程中研磨漿進入開口 214而損及基材2〇〇。因此，可先 、利用例如旋塗的方式形成由例如光阻所構成之覆蓋層 220，或利用例如沉積的方式形成由例如底部抗反射層 (Bottom Anti_Reflection c〇ating; BARC)構成之覆蓋層 22〇，覆蓋於介電層210、硬罩幕層2〇4、墊氧化層202、 ，以及犧牲層21 6上。如此，不僅可防止研磨漿進入開口 214暴路出之電容器區域中，而保護電容器區域，更可提 供平坦之研磨表面，確保研磨之均勻度。待覆蓋層22〇 形成後，再利用例如化學機械研磨的技術，移除部分之介 電層210以及部分之覆蓋層22〇，直至暴露出硬罩幕層2〇4 為止，而僅留下溝渠206内之介電層21〇與覆蓋層22〇, 如第10圖所示。 接著，可先利用例如剝除或蝕刻技術移除剩下之覆蓋 .層220。再利用例如蝕刻技術移除剩下之硬罩幕層、 塾氧化層202、以及犧牲層216，而暴露出基材2〇〇表面 以及邛分之襯氧化層208，進而形成如第u圖所示之紝 構。 、、口 在完成擴展至溝渠206之電容器區域完成定義，以及 ，雜區218形成後，此時即可配合標準邏輯製程，完成電 容器之製作。請參照第12圖，首先利用例如熱氧化的方 式形成犧牲層222覆蓋在暴露之基材2〇〇表面上。再利用 例如離子植入的方式，以犧牲層222為罩幕，將離子 1287858 植入基材200中’藉以在主動區之基材2〇〇中形成井區(未 繪示）。其中，犧牲層222之材質較佳為氧化矽。 接著，利用例如餘刻的方式移除犧牲層加，而再次 暴露出基材200之表面。再利用例如熱氧化的方式形成 閑極介電層226覆蓋在基材之表面上。其中，間極介 電層226之材f較佳為氧切。完成閘極介電層226之成 長後，利用例如化學氣相沉積的方式，形成導電材料層（僅 繪示其中之導電層228與導電層23G)覆蓋在閘極介電層 226以及介電層210上。其中’此導電材料層之材質較佳 可為複晶婦。lysilieon)。再利用例如微影與㈣技術定 義此導電材料層以及閘極介電層226，而在主動區之閘極 介電層226上形成導電層228，且在電容器區域上形成導 電層230 ’並暴露出部分之基材_，所形成之結構如第 13圖所示。其中，冑電層228可做為元件之閘極，導電 層230為電容器之電極層。於是，導電層23〇、導電層 下方之閘極介電層226、以及此部分之閘極介電層226下 方之基材200構成電容器。由於電容器區域從主動區之一 部分擴展到相鄰之溝渠206的部分侧壁上，因此電容器之 電容可獲得有效提升。 然後，利用例如離子植入的方式於導電層228與導電 層230旁之基材200中形成輕摻雜區232。再利用例如沉 積與回#刻步驟分別於導電層228之側壁形成間隙壁 234，以及於導電層230之側壁形成間隙壁236。隨後， 利用例如離子植入的方式，並以導電層228及其侧邊之間 15 1287858 隙壁234 ’與導電層23G及其侧邊之間隙壁⑽作罩幕， 在導電層22 8之兩旁的基材2G()中分別形成源極與及 極21而形成如帛14圖所示之結構。至此，大致上已 完成單-電晶體隨機存取記憶晶胞之電容器的製作。 由上述本發明較佳實施例可知，本發明之一優點 2本發明之單-電晶體隨機存取記憶晶胞之電容器的 製=方法係在凡成溝渠之隔離材料層的沉積後，直接進行 電今器區域之疋義。因此，隔離材料層與其底下之硬罩幕 層未經研磨，所以具有足夠之厚度來抵擋離子植入的衝 擊。如此-來，可直接利用隔離材料層、硬罩幕層、以及 犧牲層作為離子植人的罩幕，無須另外製作離子植入之 罩幕。故，可簡化製程，而可提升製程可靠度，更可達到 降低製程成本的目的。 由上述本發明較佳實施例可知，本發明之又一優點就 是因為可將電容器之區域擴展至溝渠側壁之一部分，而可 充分利用溝渠之部分側壁來作為電容器。因此，可提高記 憶晶胞之積集度，進而達到縮減記憶晶胞之尺寸的目的。 ^由上述本發明較佳實施例可知，本發明之另一優點就 疋因為本發明之單一電晶體隨機存取記憶晶胞之電容器 的製达可與記憶晶胞之邏輯製程相纟，製程簡單易於施 行。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限=本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 16 1287858 護範圍當視後附之申請專利範圍所界定者為準。 • 【圖式簡單說明】 第1圖至第6圖係繪示習知單一電晶體隨機存取記憶 " 晶胞之電容器的製程剖面圖。 第7圖至第14圖係繪示依照本發明一較佳實施例的 一種單一電晶體隨機存取記憶晶胞之電容器的製程剖面 圖0 【主要元件符號說明】 100 : 基材 102 :塾氧化層 104 ： 硬罩幕層 106 ••溝渠 108 ： 襯氧化層 110 ： 介電層 112 ： 罩幕層 114 ： 開口 116 ： 犧牲層 118 ： 罩幕層 120 ： 離子 122 ： 摻雜區 124 ： 犧牲層 126 ： 離子 128 ： 閘極氧化層 130 ： 導電層 132 ： 導電層 134 ： 間隙壁 136 ： 間隙壁 138 ： 輕摻雜區 140 ： 汲極 142 ： 源極 200 ： 基材 202 ： 塾氧化層 204 ： 硬罩幕層 206 ： 溝渠 208 ： 襯氧化層 210 ： 介電層 17 1287858 212 ： 罩幕層 214 ··開口 215 ： 離子 216 :犧牲層 218 ： 摻雜區 220 :覆蓋層 222 ： 犧牲層 224 :離子 226 ： 閘極介電層 228 :導電層 230 ： 導電層 232 ·•輕摻雜區 234 ： 間隙壁 236 :間隙壁 238 ： 源極 240 :汲極 18The layers are exposed to expose the substrate and the sidewall regions of the trench. Then, a second sacrificial layer is formed overlying the substrate and the sidewall regions of the trench. A second ion implantation step is performed to form a = region in the substrate of the active region. After the well zone is formed, the second sacrificial layer is removed. In this case, a gate dielectric layer may be formed to cover the substrate and the sidewall regions of the trench. A gate and an electrode layer are formed, wherein the gate is on the gate dielectric layer above the active region of the portion and the electrode layer is on the capacitor region. In accordance with a preferred embodiment of the present invention, the first ion implantation step is a mask with a dielectric layer, an exposed hard mask layer, and a sacrificial layer. In addition, when a portion of the dielectric layer is removed until the hard mask layer is exposed, a coating layer such as a photoresist may be formed on the dielectric layer, the sacrificial layer, and the exposed hard mask layer to Providing a flat abrasive surface and avoiding abrasive feeding (training into the capacitor region causes damage to the dielectric layer in the substrate and the trench. The present invention completes the deposition and filling of the dielectric layer of the trench, and the dielectric layer Grinding, and directly define the capacitor area. Therefore, the thickness of the hard mask layer is effectively maintained without the electric layer and the hard mask layer being used, and the dielectric layer and the hard mask layer can be directly used. The first sacrificial layer formed by 10 1287858 and the subsequent one is used as a mask for the first ion implantation step. Therefore, in the first ion implantation step, the mask is not required, which simplifies the process and reduces the process. [Embodiment] The present invention discloses a method for manufacturing a capacitor of a single transistor random access memory cell, which can smoothly perform the capacitor region of the sidewall of the trench without an additional mask. Implantation, and effectively solve the problem of capacitor depletion. Therefore, the steps of making the mask for ion implantation can be omitted, and the process cost can be reduced. In order to make the description of the present invention more detailed and complete, the following description can be referred to and in conjunction with Figure 7 FIG. 7 to FIG. 14 , FIG. 7 to FIG. 14 are diagrams showing a single transistor random access memory cell in the electric valley according to a preferred embodiment of the present invention. Process section of the device. The capacitor of the single transistor random access memory cell of the present invention is first provided with a substrate 200 composed of a semiconductor material, wherein the material of the substrate 2 is preferably 矽. The thermal oxidation method forms a pad oxide layer 202 overlying the substrate 200. The material of the pad oxide layer 202 is preferably ruthenium oxide (Silicon Oxide), and the thickness of the ruthenium oxide layer 202 is relatively thin. After the growth of 2〇2, a hard mask layer 2〇4 is formed on the pad oxide layer by, for example, chemical vapor deposition (VD). The material of the hard mask layer 204 is added. Preferred as nitrogen Because the hard mask layer 2 () 4 composed of, for example, nitrite is not good for the adhesion of the substrate, the surface of the substrate is covered with a layer of 1287858 before depositing the hard mask layer 2〇4. The thin pad oxide layer 202 is used to make the hard mask 屛〇Λ>|& dry tape granules 204 smoothly cover the substrate 200. After the hard mask layer 2〇4 is formed, 'for example, J is used. The shadow and etching techniques define the trench pattern, and remove portions of the hard stem stem% layer 204, the pad oxidized reed 202, and the substrate 200, and further in the hard mask 曰' 204, the pad oxide layer 202, and the base. The trench 206 is formed in the material 200. The area where the trench 206 is located may be referred to as an isolation region, and the fa domain outside the trench 206 may be referred to as an active region. After the trench 206 is formed, a thickness phase of the lining oxide layer 208 is formed on the substrate 200 exposed by the trench 206 by means of, for example, thermal oxygen ^ H ^ . LL 匕 , wherein the lining oxide layer 208 It can be used to 'protect the surface of the substrate 2 in the trench 206 during the subsequent deposition of the dielectric layer 210. The material of the lining oxide layer 208 may be oxidized stone. At this time, the dielectric layer 210 can be formed by using, for example, a high-density plasma vapor deposition (HDPCvD) technique, covering the hard mask layer, the tantalum oxide layer 202, and the oxide layer. 208, and fill the trench 2〇6, ^ ^ yang formed as shown in Fig. 7, the structure of the dielectric layer 210 can be yttrium oxide. Next, using, for example, spin coating r ... Covered on the dielectric layer 21. Above, = is the photoresist. At this time, the pattern of the capacitor region is transferred to the mask layer 212 by using, for example, a lithography: a material of 12; Exposure to China Post VIII..^ 〇, Christine Road out of the dielectric layer 210. Then use the mask layer 212 as the etching mask, use your 丨^』 夕八扪 to remove parts by dry etching, for example The electrical layer 210 and a portion of the lining oxygen FH ^ ^ 0a 曰 2 〇 8 ′′ define the capacitor region and form an opening 214 to expose a portion of the sidewall of the trench and a portion of the hard mask layer 204. ^ In other words, the capacitor area is located in addition to the hard mask layer 204 on the active area of 12 1287858. The portion of the channel 2〇6 is gamuted. Therefore, as the capacitor region extends to the wall of the trench 2〇6, the capacitance that the capacitor can provide increases. When the capacitor is defined, the hard mask layer 204 is exposed. It will be slightly damaged to form a structure as shown in the product map. After the definition of the capacitor region is completed, in order to avoid the high temperature effect of the subsequent heat treatment process, the mask layer 212 is removed, so that for example, The mask layer 212 is removed. The sacrificial surface is formed on the surface of the substrate 2 exposed by the sidewall region exposed by the trench 206, for example, by thermal oxidation, wherein the thickness of the sacrificial layer 216 is preferably controlled. The material of the sacrificial layer 216 is preferably yttria. After the sacrificial layer 216 is formed, the dielectric layer 210 and the hard mask layer 204' can be utilized, for example, by ion implantation. And the sacrificial layer 216 is used as a mask to implant the 215 into the substrate 200 of the trench 206 which is covered by the sacrificial layer 216 to form a doped region 218, as shown in FIG. Miscellaneous zone 218 can improve the phenomenon of capacitor depletion. One of the features is that since the dielectric layer 21〇 and the hard mask layer 2〇4 are not ground, the thickness of the hard mask layer 204 is maintained, and two sufficient capabilities are provided to protect the underlying substrate 200 from ion implantation. In this way, the original dielectric layer 210 and the hard mask layer 204 can be directly used as the mask structure of the ion implantation without separately preparing the ion implantation mask structure. The process steps can be simplified, thereby reducing the process cost. After the replacement zone 218 is formed, for example, chemical mechanical polishing techniques can be used, 13 1287858 • The dielectric layer 21〇 outside the trench 206 is directly removed until the hard mask layer is exposed. 204 so far. However, in a preferred embodiment of the invention, in order to avoid grinding: the slurry enters the opening 214 during the process and damages the substrate 2〇〇. Therefore, the cover layer 220 composed of, for example, a photoresist may be formed by, for example, spin coating, or the cover layer 22 composed of, for example, a Bottom Anti-Reflection layer (BAR) may be formed by, for example, deposition. The germanium covers the dielectric layer 210, the hard mask layer 2〇4, the pad oxide layer 202, and the sacrificial layer 21 6 . In this way, not only the slurry can be prevented from entering the capacitor region where the opening 214 is violently exited, but also the capacitor region can be protected, and a flat abrasive surface can be provided to ensure the uniformity of the grinding. After the cap layer 22 is formed, a portion of the dielectric layer 210 and a portion of the cap layer 22 are removed by a technique such as chemical mechanical polishing until the hard mask layer 2〇4 is exposed, leaving only the trench The dielectric layer 21〇 and the cap layer 22〇 in the 206 are as shown in FIG. The remaining cover layer 220 can then be removed using, for example, stripping or etching techniques. The remaining hard mask layer, tantalum oxide layer 202, and sacrificial layer 216 are removed by, for example, etching techniques to expose the surface of the substrate 2 and the lining oxide layer 208, thereby forming a layer as shown in FIG. Show the structure. The port is completed in the capacitor area extended to the trench 206, and after the impurity region 218 is formed, the standard logic process can be used to complete the fabrication of the capacitor. Referring to Fig. 12, a sacrificial layer 222 is first formed on the surface of the exposed substrate 2 by, for example, thermal oxidation. The well region (not shown) is formed in the substrate 2 of the active region by, for example, ion implantation using the sacrificial layer 222 as a mask to implant the ions 1287858 into the substrate 200. The material of the sacrificial layer 222 is preferably yttrium oxide. Next, the sacrificial layer is removed by, for example, a residual method, and the surface of the substrate 200 is exposed again. The dummy dielectric layer 226 is formed over the surface of the substrate by, for example, thermal oxidation. The material f of the interlayer dielectric layer 226 is preferably oxygen cut. After the growth of the gate dielectric layer 226 is completed, a conductive material layer (only the conductive layer 228 and the conductive layer 23G are shown) is overlaid on the gate dielectric layer 226 and the dielectric layer by, for example, chemical vapor deposition. 210 on. Wherein the material of the conductive material layer is preferably a polycrystalline woman. Lysilieon). The conductive material layer and the gate dielectric layer 226 are defined by, for example, lithography and (4) techniques, while the conductive layer 228 is formed on the gate dielectric layer 226 of the active region, and the conductive layer 230' is formed on the capacitor region and exposed. The portion of the substrate _ is formed as shown in Fig. 13. The germanium layer 228 can serve as a gate of the device, and the conductive layer 230 is an electrode layer of the capacitor. Thus, the conductive layer 23, the gate dielectric layer 226 under the conductive layer, and the substrate 200 under the gate dielectric layer 226 of this portion constitute a capacitor. Since the capacitor region extends from a portion of the active region to a portion of the sidewall of the adjacent trench 206, the capacitance of the capacitor can be effectively increased. Lightly doped regions 232 are then formed in the substrate 200 adjacent to the conductive layer 228 and the conductive layer 230 by, for example, ion implantation. The spacers 234 are formed on the sidewalls of the conductive layer 228, respectively, by, for example, deposition and etchback steps, and the spacers 236 are formed on the sidewalls of the conductive layer 230. Subsequently, by means of, for example, ion implantation, and between the conductive layer 228 and its sides 15 1287858 gap wall 234 ' and the conductive layer 23G and its side spacers (10) as a mask, on both sides of the conductive layer 22 8 The source and the gate 21 are formed in the base material 2G () to form a structure as shown in FIG. So far, the fabrication of a capacitor of a single-transistor random access memory cell has been substantially completed. According to the preferred embodiment of the present invention, one of the advantages of the present invention is that the method for manufacturing the capacitor of the single-transistor random access memory cell of the present invention is directly performed after deposition of the isolation material layer of the Fancheng trench. The meaning of the electric current area. Therefore, the layer of spacer material and the underlying hard mask layer are not ground and therefore have sufficient thickness to withstand the impact of ion implantation. In this way, the isolation material layer, the hard mask layer, and the sacrificial layer can be directly used as a mask for ion implantation without the need for an additional ion implantation mask. Therefore, the process can be simplified, the process reliability can be improved, and the process cost can be reduced. From the above-described preferred embodiments of the present invention, it is a further advantage of the present invention that the area of the capacitor can be extended to a portion of the sidewall of the trench, and a portion of the sidewall of the trench can be utilized as a capacitor. Therefore, the degree of accumulation of the memory cell can be improved, thereby achieving the purpose of reducing the size of the memory cell. According to the preferred embodiment of the present invention described above, another advantage of the present invention is that the fabrication of the capacitor of the single transistor random access memory cell of the present invention can be achieved by the logic process of the memory cell, and the process is simple. Easy to implement. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to be limited to the present invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the protection of the present invention is defined by the scope of the appended patent application. • [Simplified Schematic] Fig. 1 to Fig. 6 show a process sectional view of a conventional single crystal random access memory " cell capacitor. 7 to 14 are cross-sectional views showing a process of a single transistor random access memory cell capacitor according to a preferred embodiment of the present invention. [Main component symbol description] 100: Substrate 102: 塾 oxidation Layer 104: Hard mask layer 106 • Ditch 108: lining oxide layer 110: dielectric layer 112: mask layer 114: opening 116: sacrificial layer 118: mask layer 120: ion 122: doped region 124: sacrificial layer 126 : ion 128 : gate oxide layer 130 : conductive layer 132 : conductive layer 134 : spacer 136 : spacer 138 : lightly doped region 140 : drain 142 : source 200 : substrate 202 : tantalum oxide layer 204 : Hard mask layer 206 : trench 208 : lining oxide layer 210 : dielectric layer 17 1287858 212 : mask layer 214 · · opening 215 : ion 216 : sacrificial layer 218 : doped region 220 : cover layer 222 : sacrificial layer 224 : Ion 226 : gate dielectric layer 228 : conductive layer 230 : conductive layer 232 · lightly doped region 234 : spacer 236 : spacer 238 : source 240 : drain 18