TWI578346B - Capacitor structure and method of forming the same - Google Patents

Description

Capacitor structure and its forming method

The present invention relates to a capacitor structure, and more particularly to a capacitor structure having a 矽 through electrode.

In the modern information society, micro-processing systems consisting of integrated circuits (ICs) have long been widely used in all aspects of life, such as automatic control of household appliances, mobile communication devices, personal computers, etc. The use of integrated circuits. With the increasing advancement of technology and the imagination of human society for electronic products, various electronic products with integrated circuits have also developed in the direction of more yuan, more precision and smaller.

In the current electronic products, various semiconductor technologies are used to form circuit elements on a germanium substrate, such as a metal oxide semiconductor transistor (MOS transistor), a capacitor, or a resistor. These circuit components are electrically connected to each other to form a complex circuit system. In general, the capacitor structure will have an upper electrode, a dielectric layer, and a lower electrode. The conventional capacitor structure is disposed in an inter-metal dielectric layer (IMD layer) above the germanium substrate, and has a structure of "metal-insulator-metal (MIM)". However, due to the current shrinkage of electronic products, the space for forming a capacitor structure is gradually reduced, and the size of the capacitance value is also limited, and it is impossible to cope with Accumulated product components.

The present invention thus provides a capacitor structure and a method of forming the same, which is characterized in that the process and structure of the conventional tantalum through electrode are applied, and the capacitance value of the capacitor structure can be effectively increased.

According to an embodiment of the present invention, the present invention provides a capacitor structure including a substrate, a through-electrode, a dielectric layer, and a doped region. The substrate has a first surface and a second surface opposite the first surface. The through electrode runs through the first surface and the second surface. A dielectric layer is disposed in the substrate and surrounds the 矽 through electrode. The doped region is disposed between the substrate and the dielectric layer. Wherein, the 矽through electrode is a first electrode of the capacitor structure, and the doped region is a second electrode of the capacitor structure.

According to another embodiment of the present invention, the present invention also provides a method of forming a capacitor structure. A substrate is first provided having a first surface and a second surface relative to the first surface. A first opening and a second opening are then formed on the first surface of the substrate. A doped region is then formed in the substrate adjacent the second opening. A liner layer is formed on the surfaces of the first opening and the second opening. The liner layer in the second opening is subsequently removed. A dielectric layer is then formed over the doped regions in the second opening. Finally, a conductive layer is formed on the first surface of the substrate to fill the first opening and the second opening.

The capacitor structure of the present invention and the method of forming the same are from the structure of the conventional 矽 through electrode And the formation method is modified to form the capacitor structure of the present invention while forming the tantalum penetration electrode. The advantage of using the 矽 through electrode as the upper electrode is that the area between the electrode and the dielectric layer can be increased, so that the capacitance value can be effectively increased to obtain a capacitor structure of better quality.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Referring to Figures 1 through 9, there is shown a schematic diagram of the steps of a method of forming a capacitor structure in accordance with the present invention. As shown in FIG. 1, a substrate 300 is first provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, or a silicon carbide substrate. Or a silicon-on-insulator substrate (SOI substrate). In one embodiment, substrate 300 has a first conductive configuration, such as substrate 300 being a phosphorus-containing germanium substrate (P ^- substrate). The substrate 300 has a first surface 302 and a second surface 304 disposed opposite each other. In one embodiment of the invention, the first surface 302 is, for example, the active surface of the substrate 300, and the second surface 304 is, for example, the backside surface of the substrate 300. The thickness of the substrate 300 is generally 700 to 1000 micrometers, but not limited thereto. Next, a first opening 306, a second opening 308 and a third opening 309 are formed on the first surface 302 of the substrate 300. The depth of the first opening 306, the second opening 308 and the third opening 309, and the aperture may be selected differently depending on the product design. In one embodiment of the present invention, the depth of the first opening 306 and the second opening 308 are substantially the same, and the depth of the third opening 309 is smaller than the depth of the first opening 306 and the second opening 308, such as the first opening 306 and The depth of the second opening 308 is 50 to 100 microns, and the depth of the third opening 309 is 5 microns. In other embodiments, the depth of the first opening 306 and the depth of the second opening 308 may be different, for example, the depth of the first opening 306 may be greater than the depth of the second opening 308. In addition, the first opening 306, the second opening 308, and the third opening 309 may be formed in different cases in different cases. In one embodiment, if the first opening 306 and the second opening 308 have the same depth, the two openings may be formed in the same photolithography-etching-process (PEP) step, for example, forming a third opening. After 309, the first opening 306 and the second opening 308 are formed. Alternatively, the first opening 306 and the second opening 308 may be formed first, and then the third opening 309 is formed. In an embodiment of the present invention, the photomask forming the third opening 309 may further include a zero mark, thereby forming a third opening 309 and an alignment mark simultaneously in the substrate 300 (FIG. 1) Not shown). This alignment mark can be used for alignment when forming the first opening 306 and/or the second opening 308, or as an alignment for use in subsequent steps. In this way, a lithography and etching process can be saved. In addition, in another embodiment, the first opening 306, the second opening 308, and the third opening 309 may also be formed at the same time. The first opening 306, the second opening 308, and the third opening 309 of different depths are formed in the same etching process, for example, by different opening sizes. Alternatively, the first opening 306, the second opening 308, and the third opening 309 of different depths are simultaneously formed by a half tone mask or the like.

As shown in FIG. 2, a doped region 310 is formed on a specific region of the substrate 300, for example, a surface of the second opening 308 and the third opening 309. In one embodiment, the doped regions 310 are formed only on the surfaces of the second opening 308 and the third opening 309 without being formed on the surface of the first opening 306. The method of forming the doping region 310 is, for example, a gas phase doping (GPD) process. For example, a mask such as a patterned photoresist layer (not shown) may be formed on one side of the first surface 302 of the substrate 300 to cover the first opening 306, and then a doping gas is provided to make the second opening. The 308 and the third opening 309 are exposed to the doping gas, followed by an annealing process. In one embodiment, the doped region 310 has a second conductive form, and the second conductive form is different from the first conductive form of the substrate 300. For example, when the substrate 300 is a phosphorous-containing germanium substrate, the doped region 310 is an arsenic-containing region. . It should be noted that the doping regions 310 (at FIG. 2A) between the second opening 308 and the third opening 309 are preferably connected to each other, that is, the doping region 310 is contiguously formed in the second Between the opening 308 and the third opening 309. However, in one embodiment, the doped regions 310 at A may not be connected at this time. In addition, in another embodiment of the present invention, the doping region 310 may also be formed entirely on the substrate 300, for example, also on the surface of the first opening 306.

As shown in FIG. 3, a liner layer 312 is formed on the first surface 302 of the substrate 300, for example, a composite structure of a single oxide layer, a single nitride layer, or an oxide layer plus a nitride layer. In one embodiment, the liner layer 312 is formed by thermal oxidation, and thus conformally formed along the surfaces of the first opening 306, the second opening 308, and the third opening 309, and has a thickness substantially The upper is 2000 angstroms to 1 micron. In one embodiment, the thermal oxidation process can be combined with the annealing process in the gas phase doping process described above. Together, that is, after the thermal oxidation process is performed, the liner layer 312 and the doped region 310 can be simultaneously formed. In another embodiment, if the parameters of the thermal oxidation process are appropriately adjusted, the range of the doping regions 310 may be increased, so that the doping regions 310 at A may be more surely connected and continuous. In other embodiments, the liner layer 312 can also be formed in other ways, such as an atomic layer deposition (ALD) process.

As shown in FIG. 4, the second opening 308 and the backing layer 312 on the surface of the third opening 309 are removed. In an embodiment of the present invention, for example, an alignment mark (not shown) is formed to form a patterned photoresist layer (not shown) covering a region other than the second opening 308 and the third opening 309, and then Performing a wet etching process and/or a dry etching process to remove the pad layer 312 here, and exposing the doping region 310 at the bottom of the second opening 308 and the third opening 309, and finally removing the patterned photoresist layer. . In addition, in the foregoing embodiment, after the doping region 310 and the pad layer 312 are formed (FIG. 3), the pad layer 312 in the second opening 308 and the third opening 309 is removed (FIG. 4). In another embodiment of the present invention, the pad layer 312 may be formed first, then the pad layer 312 in the second opening 308 and the third opening 309 may be removed, and then the doping region 310 may be formed.

Subsequently, as shown in FIG. 5, a very thin dielectric layer 314 is formed on the surface of the second opening 308 and the third opening 309, such as a single oxide layer, a single nitride layer, or an oxide layer plus a nitride layer. And other composite structures. The method of forming the dielectric layer 314 is, for example, a thermal oxidation process, and the thickness of the dielectric layer 314 is preferably less than the thickness of the liner layer 312, for example, 40 to 100 angstroms. Since the dielectric layer 314 is formed by thermal oxidation, the dielectric Layer 314 is preferably formed only on the surface of second opening 308 and third opening 309. In an embodiment of the present invention, after forming the dielectric layer 314, a cap layer (not shown) may be selectively formed on the first surface 302 of the substrate 300 to cover at least the second opening 308. And the surface of the third opening 309. The thickness of the cap layer is also preferably smaller than the thickness of the dielectric layer 314, and the material is, for example, silicon nitride, or forms an oxide layer-nitride layer-oxide layer (ONO) together with the dielectric layer 314.

As shown in FIG. 6, the dielectric layer 314 (and the cap layer) on the surface of the third opening 309 is removed. In one embodiment of the present invention, for example, a patterned photoresist layer (not shown) is formed to cover a region other than the third opening 309, and then a wet etching process and/or a dry etching process is performed to remove The dielectric layer 314 (and the cap layer) is here, and the underlying doped region 310 is exposed, and finally the patterned photoresist layer is removed.

As shown in FIG. 7, a surface of the first opening 306, the second opening 308, and the third opening 309 is filled with a selective barrier layer 316 and a conductive layer 318. The conductive layer 318 will completely fill the first opening 306, the second opening 308, and the third opening 309. In one embodiment of the present invention, the barrier layer 316 is formed by physical vapor deposition (PVD), and the material thereof is, for example, titanium nitride (TiN). The conductive layer 318 is formed by electroplating, and the material thereof is, for example, copper. Therefore, after forming the barrier layer 316, a copper seed layer (not shown) is formed, and then copper plating is performed. A step of. Finally, a planarization process, such as a chemical mechanical polish (CMP) process or an etching back process or a combination of the two, is performed to remove the liner layer 312. A conductive layer 318 and a barrier layer 316. Or in another embodiment, the liner layer 312 on the substrate 300 can be further removed.

As shown in FIG. 8, a metal interconnect system 320 is formed on one side of the first surface 302 of the substrate 300. Metal interconnect system 320 includes, for example, a plurality of metal layers and a plurality of dielectric layers. In one embodiment, the metal interconnect system 320 electrically connects the first opening 306, the second opening 308, and the conductive layer 318 in the third opening 309 to provide input/output of their electronic signals, respectively.

As shown in FIG. 9, a thinning process is finally performed from one side of the second surface 304 of the substrate 300. The thinning process is performed to expose the conductive layer 318 (or the barrier layer 316) in the first opening 306 and the second opening 308. At this time, the second surface 304 of the substrate 300 forms the third surface 305. In this way, the 矽 through electrode 322a is formed on the left side of the ninth figure, and the capacitor structure 324 of the present invention is formed in the middle and the right side, wherein the conductive layer 318 in the second opening 308 forms the 矽 through electrode 322b, and the third Conductive layer 318 in opening 309 then forms a circuit pick 323.

It should be noted that if the depths of the first opening 306 and the second opening 308 are different from the beginning, the principle is that the conductive layer 318 in the first opening 306 can be exposed. Please refer to FIG. 10, which is a schematic diagram showing the steps of another method for forming a capacitor structure according to the present invention. If the depth of the first opening 306 is greater than the depth of the second opening 308, the thinning process will at least expose the conductive layer 318 in the first opening 306, and the conductive layer 318 in the second opening 308 is not exposed. Similarly, on the left side of the 10th figure, a 矽through is formed. The electrode 322a, while the middle and the right side, form the capacitor structure 324 of the present invention, wherein the conductive layer 318 in the second opening 308 forms one electrode of the capacitor structure 324, and the conductive layer 318 in the third opening 309 forms the circuit. Contact 323.

As shown in FIG. 9, the capacitor structure 324 of the present invention includes a substrate 300, a germanium through electrode 322b, a dielectric layer 314, and a doped region 310. The substrate 300 has a first surface 302 and a third surface 305. The through electrode 322b extends through the first surface 302 and the third surface 305. The dielectric layer 314 is disposed between the substrate 300 and the tantalum through electrode 322b, preferably surrounding the sidewall of the tantalum through electrode 322b. The doped region 310 is continuously disposed in the substrate 300 between the circuit contacts 323 and the 矽 through electrodes 322b, and preferably surrounds the dielectric layer 314. If an appropriate electronic signal is applied from the metal interconnect system 320, the through electrode 322b is the first electrode of the capacitor structure 324, and the doped region 310 serves as the second electrode of the capacitor structure 324. A very thin dielectric layer 314 is formed to form a "metal-insulator-metal" structure. In addition, a tantalum penetration electrode 322a is disposed in the substrate 300, which penetrates the first surface 302 and the third surface 305, and the liner layer 312 surrounds the crucible through electrode 322a. Preferably, the pad layer 312 does not surround the germanium through electrode 322b in the capacitor structure 324, and the doped region 310 does not surround the via electrode 322a.

In addition, as shown in FIG. 10, in another embodiment of the present invention, the depth of the first opening 306 may be greater than the depth of the second opening 308, that is, the depth of the through-electrode 322a may be greater than that of one of the capacitor structures 324. depth. As such, the capacitor structure 324 of the present invention can further obtain the doping of the conductive layer 318 in the second opening 308 and the bottom of the second opening 308. The capacitance value of the corresponding area of the impurity region 310.

One of the features of the present invention is that the use of a tantalum through electrode as the upper electrode allows the area between the electrode and the dielectric layer to be increased and the capacitance value to be effectively increased. For example, in one embodiment, if the depth of the second opening 308 is 100 micrometers and the thickness of the dielectric layer 314 is 100 angstroms, the capacitance value of the capacitor structure 324 may be greater than 50 fF/μm ² , which is much larger than the conventional technology. The capacitance value of the capacitor structure formed in the metal inter-dielectric layer (MID) is 2fF/μm ² .

The capacitor structure of the present invention and the method of forming the same are improved from the conventional structure and the formation method of the through electrode, and the capacitor structure of the present invention can be formed while forming the tantalum penetration electrode. And according to the time point of formation of the metal interconnect system, the method of the present invention can be applied to, for example, "TSV first" or "TSV last" or even "Through through electrode" (TSV) Middle)" process.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300‧‧‧Base

302‧‧‧ first surface

304‧‧‧ second surface

305‧‧‧ third surface

306‧‧‧ first opening

308‧‧‧ second opening

309‧‧‧ third opening

310‧‧‧Doped area

312‧‧‧ liner

314‧‧‧ dielectric layer

316‧‧‧ barrier layer

318‧‧‧ Conductive layer

320‧‧‧Metal interconnection system

322a‧‧‧矽through electrode

322b‧‧‧矽through electrode

323‧‧‧circuit contacts

324‧‧‧Capacitor structure

1 to 9 are schematic views showing the steps of a method of forming a capacitor structure in accordance with the present invention.

Figure 10 is a schematic illustration of the steps of another method of forming a capacitor structure in accordance with the present invention.

300‧‧‧Base

302‧‧‧ first surface

305‧‧‧ third surface

310‧‧‧Doped area

312‧‧‧ liner

314‧‧‧ dielectric layer

316‧‧‧ barrier layer

318‧‧‧ Conductive layer

320‧‧‧Metal interconnection system

322a‧‧‧矽through electrode

322b‧‧‧矽through electrode

323‧‧‧circuit contacts

324‧‧‧Capacitor structure

Claims (20)

A method of forming a capacitor structure includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a first opening and a side on a side of the first surface of the substrate a second opening; forming a doped region in the substrate adjacent to the second opening; forming a liner layer on the surface of the first opening and the second opening; removing the liner layer in the second opening Forming a dielectric layer on the doped region in the second opening; and forming a conductive layer on the substrate to fill the first opening and the second opening. The method of forming a capacitor structure according to claim 1, wherein the doped region and the liner layer are formed first, and the liner layer in the second opening is removed. The method of forming a capacitor structure according to claim 1, wherein the liner layer is formed first, then the liner layer in the second opening is removed, and then the doped region is formed. The method of forming a capacitor structure according to claim 1, wherein the depth of the first opening is the same as the depth of the second opening. The method of forming a capacitor structure according to claim 1, wherein the depth of the first opening is different from the depth of the second opening. The method of forming a capacitor structure according to claim 1, further comprising forming a circuit contact, the circuit contact electrically connecting the doped region. The method of forming a capacitor structure according to claim 6, wherein the step of forming the circuit contact comprises: forming a third opening on a side of the first surface of the substrate; and adjacent to the third opening The doped region is formed in the substrate, wherein the doped region is continuously disposed between the second opening and the third opening; and the third opening is filled with the conductive layer. The method of forming a capacitor structure according to claim 7, wherein the step of forming the circuit contact further comprises: forming the liner layer on a surface of the third opening; removing the liner in the third opening a pad layer; forming the dielectric layer in the third opening; and removing the dielectric layer in the third opening. The method of forming a capacitor structure according to claim 7, wherein the third opening has a depth smaller than a depth of the first opening and the second opening. The method for forming a capacitor structure according to claim 6, further comprising forming a metal interconnecting system on one side of the first surface of the substrate, wherein the metal interconnecting system is electrically connected to the circuit a point and the conductive layer in the second opening. The method of forming a capacitor structure according to claim 1, further comprising performing a thinning process from one side of the second surface of the substrate to expose the conductive layer in the first opening. The method of forming a capacitor structure according to claim 11, wherein the thinning process is performed to simultaneously expose the first opening and the conductive layer in the second opening. A capacitor structure comprising: a substrate having a first surface and a second surface opposite to the first surface; a through electrode disposed in the substrate, the first surface of the substrate and the first surface a second surface; a dielectric layer disposed in the substrate and surrounding the germanium through electrode; and a doped region disposed between the substrate and the dielectric layer, wherein the germanium through electrode is a one of the capacitor structures a first electrode, and the doped region is a second electrode as the capacitor structure. The capacitor structure of claim 13 further comprising a circuit contact disposed on a side of the first surface of the substrate, and the circuit contact is electrically connected to the doped region. The capacitor structure of claim 14, wherein the doped region is continuously disposed in the substrate between the circuit contact and the meandering electrode. The capacitor structure of claim 14, further comprising a metal interconnecting system, wherein the metal interconnecting system is electrically connected to the circuit contact and the through-electrode. The capacitor structure of claim 13, wherein the substrate is further provided with: a second 矽 through electrode extending through the first surface and the second surface; and a lining layer surrounding the second The crucible penetrates the electrode but does not surround the crucible through electrode in the capacitor structure. The capacitor structure of claim 17, wherein the doped region does not surround the second 矽 through electrode. The capacitor structure of claim 17, wherein the dielectric layer has a thickness less than a thickness of the liner layer. The capacitor structure of claim 13, wherein the doped region surrounds the dielectric layer and the germanium through electrode.