CN116782758A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN116782758A CN116782758A CN202310944582.8A CN202310944582A CN116782758A CN 116782758 A CN116782758 A CN 116782758A CN 202310944582 A CN202310944582 A CN 202310944582A CN 116782758 A CN116782758 A CN 116782758A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 43
- 239000010410 layer Substances 0.000 claims abstract description 214
- 229910052751 metal Inorganic materials 0.000 claims abstract description 204
- 239000002184 metal Substances 0.000 claims abstract description 204
- 239000011229 interlayer Substances 0.000 claims abstract description 78
- 239000003990 capacitor Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims description 26
- 238000005240 physical vapour deposition Methods 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 238000000231 atomic layer deposition Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 229910052718 tin Inorganic materials 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 238000011049 filling Methods 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000000608 laser ablation Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 15
- 238000001259 photo etching Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
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- 238000010884 ion-beam technique Methods 0.000 description 2
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- 239000000126 substance Substances 0.000 description 1
- -1 tiAl Chemical compound 0.000 description 1
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Abstract
The application provides a semiconductor device and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein an MIM capacitor is formed on the substrate; forming a first contact hole and a second contact hole in the first interlayer dielectric layer; and forming a first metal and a second metal to respectively lead out an upper polar plate and a lower polar plate of the MIM capacitor while forming a floating metal resistor. The top contact hole penetrates through the second interlayer dielectric layer to expose the floating metal layer. The heights of the top contact holes are consistent, so that the etching loss of the floating metal layer is conveniently controlled. The top contact hole includes a third contact hole, a fourth contact hole, and a fifth contact hole. The floating metal resistor is directly led out through the fifth contact hole; the upper polar plate of the MIM capacitor is led out through the first contact hole, the first metal and the third contact hole in sequence; the lower polar plate of the MIM capacitor is led out through the second contact hole, the second metal and the fourth contact hole in sequence. One layer of mask plate is reduced, and the cost is reduced; the problem that the photoetching alignment mark is not clearly seen is solved, and the efficiency is improved.
Description
Technical Field
The application belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
As shown in fig. 1, the semiconductor device includes a substrate 01, a MIM (metal-insulator-metal) capacitor 02 is formed on the substrate 01, and the MIM capacitor 02 includes a lower plate 021, an upper plate 023, and an inter-plate dielectric layer 022 between the lower plate 021 and the upper plate 023. An interlayer dielectric layer one 03 is formed on the MIM capacitor 02, a floating metal resistor 05 needs to be manufactured on the surface of the interlayer dielectric layer one 03, and an interlayer dielectric layer two 06 is formed on the floating metal resistor 05. The subsequent etching process is needed to form contact holes, wherein the contact holes comprise contact hole K 1 Contact hole II K 2 And contact hole three K 3 . Contact hole K 1 The surface of the upper polar plate 023 is exposed through the interlayer dielectric layer II 06 and the interlayer dielectric layer I03; contact hole II K 2 The surface of the lower polar plate 021 is exposed through the second interlayer dielectric layer 06 and the first interlayer dielectric layer 03. Contact hole three K 3 The floating metal resistor 05 is exposed through the interlayer dielectric layer two 06. Upper electrode plate 023 passes through contact hole K 1 Plug one 041 in (a) is connected to pad one 071 on the top layer, and the lower electrode plate 021 passes through contact hole two K 2 The second plug 042 is connected to the second pad 072, and the floating metal resistor 05 passes through the third K contact hole 3 Plug three 043 in (c) is connected to pad three 073. Due to contact hole K 1 Bottom of (2) contact hole II K 2 Is all three K with the contact hole at the bottom 3 The bottom of the contact hole is formed in the same etching process, so that the floating metal resistor 05 is easy to be over-etched, and the product quality is affected; the contact holes are formed by separate etching in different etching processes, and the problems of increased process cost and low yield are also existed.
Disclosure of Invention
The application aims to provide a semiconductor device and a manufacturing method thereof, which reduce one layer of mask plate and reduce cost; the problem that the photoetching alignment mark is not clearly seen is solved, and the efficiency is improved.
The application provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, wherein an MIM capacitor is formed on the substrate, and the MIM capacitor comprises a lower polar plate and an upper polar plate which are opposite;
forming a first interlayer dielectric layer covering the MIM capacitor and the substrate; forming a first contact hole leading out the upper polar plate and a second contact hole leading out the lower polar plate in the first interlayer dielectric layer respectively;
forming a floating metal layer on the surface of the first interlayer dielectric layer, wherein the floating metal layer comprises a first metal, a second metal and a floating metal resistor; the upper polar plate is connected with the first metal through the first contact hole, and the lower polar plate is connected with the second metal through the second contact hole;
forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the floating metal layer;
forming a top contact hole, wherein the top contact hole penetrates through the second interlayer dielectric layer to expose the floating metal layer; the top contact hole comprises a third contact hole leading out of the first metal, a fourth contact hole leading out of the second metal and at least one fifth contact hole leading out of the floating metal resistor; filling metal in the top contact hole;
and forming a top metal layer on the surface of the second interlayer dielectric layer, wherein the top metal layer comprises a plurality of welding pads for connecting and leading out the metal in each top contact hole.
Further, the floating metal layer is formed by at least one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, laser ablation deposition and selective epitaxial growth.
Further, the material of the floating metal layer comprises at least one of TiN, copper, aluminum and tungsten.
Further, the manufacturing method further comprises the following steps: and filling metal in the first contact hole and the second contact hole to form a first plug and a second plug respectively.
Further, the manufacturing method further comprises the following steps: and sequentially forming an isolation layer and a dielectric barrier layer between the substrate and the MIM capacitor.
Further, after forming the top metal layer, the method further comprises:
forming an insulating layer covering the upper surface and the side walls of the top metal layer;
and forming a passivation layer covering the insulating layer and the surface of the second interlayer dielectric layer.
The present application also provides a semiconductor device including:
a substrate, on which a MIM capacitor is formed, the MIM capacitor comprising a lower plate and an upper plate opposite to each other;
a first interlayer dielectric layer covering the MIM capacitor and the substrate; a first contact hole for leading out the upper polar plate and a second contact hole for leading out the lower polar plate are respectively formed in the first interlayer dielectric layer;
a floating metal layer is formed on the surface of the first interlayer dielectric layer, and the floating metal layer comprises a first metal, a second metal and a floating metal resistor; the upper polar plate is connected with the first metal through the first contact hole, and the lower polar plate is connected with the second metal through the second contact hole;
a second interlayer dielectric layer covering the first interlayer dielectric layer and the floating metal layer;
the top contact hole penetrates through the second interlayer dielectric layer to expose the floating metal layer; the top contact hole comprises a third contact hole leading out of the first metal, a fourth contact hole leading out of the second metal and at least one fifth contact hole leading out of the floating metal resistor; the top contact hole is filled with metal;
and a top metal layer is formed on the surface of the second interlayer dielectric layer, and comprises a plurality of welding pads for connecting and leading out the metal in each top contact hole.
Further, the MIM capacitor further comprises an inter-plate dielectric layer between the upper plate and the lower plate.
Further, the floating metal resistor is led out to the top metal layer through two parallel fifth contact holes.
Further, the material of the floating metal layer comprises at least one of TiN, copper, aluminum and tungsten.
Compared with the prior art, the application has the following beneficial effects:
the application provides a semiconductor device and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein an MIM capacitor is formed on the substrate; a first interlayer dielectric layer is formed overlying the MIM capacitor and the substrate. Forming a first contact hole for leading out an upper polar plate and a second contact hole for leading out a lower polar plate in the first interlayer dielectric layer respectively; forming a floating metal layer, wherein the floating metal layer comprises a first metal, a second metal and a floating metal resistor; and forming a first metal and a second metal to respectively lead out an upper polar plate and a lower polar plate of the MIM capacitor while forming a floating metal resistor. The top contact hole penetrates through the second interlayer dielectric layer to expose the floating metal layer; the top contact hole comprises a third contact hole for leading out the first metal, a fourth contact hole for leading out the second metal and at least one fifth contact hole for leading out the floating metal resistor; and filling metal in the top contact hole. The heights of the top contact holes are consistent, so that the etching loss of the floating metal layer is conveniently controlled. The floating metal resistor is directly led out through the fifth contact hole; the upper polar plate of the MIM capacitor is led out through the first contact hole, the first metal and the third contact hole in sequence; the lower polar plate of the MIM capacitor is led out through the second contact hole, the second metal and the fourth contact hole in sequence. One layer of mask plate is reduced, and the cost is reduced; solving the problem that the photoetching alignment mark is not clearly seen; longer waiting time is avoided after the contact hole for leading out the floating metal resistor is formed, and efficiency is improved.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor device.
Fig. 2 is a flow chart of a method for fabricating a semiconductor device according to an embodiment of the application.
Fig. 3 to 6 are schematic views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the application.
Wherein, the reference numerals are as follows:
01-substrate; 02-MIM capacitor; 021-lower plate; 022-inter-plate mediumA layer; 023-upper plate; k (K) 1 -a contact hole one; k (K) 2 -a second contact hole; k (K) 3 -contact holes three; 03-an interlayer dielectric layer I; 041-plug one; 042-plug two; 043-plug three; 05-floating metal resistance; 06-an interlayer dielectric layer II; 071-pad one; 072-bond pad two; 073-bonding pad three;
10-a substrate; 11-isolating layer; a 20-MIM capacitor; 21-a lower polar plate; 22-inter-plate dielectric layer; 23-upper polar plate; 30-a first interlayer dielectric layer; v (V) 1 -a first contact hole; v (V) 2 -a second contact hole; v (V) 3 -a third contact hole; v (V) 4 -a fourth contact hole; v (V) 5 -a fifth contact hole; 41-a first plug; 42-a second plug; 51-a first metal; 52-a second metal; 53-floating metal resistance; 60-a second interlayer dielectric layer; 71-a third plug; 72-a fourth plug; 73-a fifth plug; 81-a first bonding pad; 82-a second bonding pad; 83-a third pad; 91-an insulating layer; 92-passivation layer.
Detailed Description
As described in the background art, in fig. 1, the contact hole is formed in the same etching process, which is easy to cause over etching of the floating metal resistor 05, so that the product quality is affected; the contact holes are etched separately in different etching processes, which has the problems of increasing the process cost and low yield.
Specifically, an attempt is made to form contact holes three K in a first etching process 3 Then forming a contact hole K in another etching process 1 And contact hole II K 2 . Because the floating metal resistor 05 has poor light transmittance, the alignment mark of the front layer cannot be seen through the flat interlayer dielectric layer 03 when the floating metal resistor 05 is photoetched. A mask is added before the floating metal resistor 05 is deposited to open the alignment mark of the photoresist. One more layer of mask is added, and the cost is increased. Firstly etching contact holes three K 3 Contact hole three K 3 In a long waiting state, there is a problem of low yield.
Based on the above-mentioned intensive research analysis, the present application provides a semiconductor device and a method for manufacturing the same. The application is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present application will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the application.
For ease of description, some embodiments of the application may use spatially relative terms such as "above" …, "" below "…," "top," "below," and the like to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that these terms so used may be substituted where appropriate.
An embodiment of the present application provides a method for manufacturing a semiconductor device, as shown in fig. 2, including:
step S1, providing a substrate, wherein an MIM capacitor is formed on the substrate, and the MIM capacitor comprises a lower polar plate and an upper polar plate which are opposite to each other;
s2, forming a first interlayer dielectric layer covering the MIM capacitor and the substrate; forming a first contact hole leading out the upper polar plate and a second contact hole leading out the lower polar plate in the first interlayer dielectric layer respectively;
s3, forming a floating metal layer on the surface of the first interlayer dielectric layer, wherein the floating metal layer comprises a first metal, a second metal and a floating metal resistor; the upper polar plate is connected with the first metal through the first contact hole, and the lower polar plate is connected with the second metal through the second contact hole;
s4, forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the floating metal layer;
s5, forming a top contact hole, wherein the top contact hole penetrates through the second interlayer dielectric layer to expose the floating metal layer; the top contact hole comprises a third contact hole leading out of the first metal, a fourth contact hole leading out of the second metal and at least one fifth contact hole leading out of the floating metal resistor; filling metal in the top contact hole;
and S6, forming a top metal layer on the surface of the second interlayer dielectric layer, wherein the top metal layer comprises a plurality of welding pads for connecting and leading out the metal in each top contact hole.
The following describes in detail the steps of the method for manufacturing a semiconductor device according to an embodiment of the present application with reference to fig. 3 to 6.
As shown in fig. 3, a substrate 10 is provided, and an isolation layer 11 and a MIM capacitor 20 are sequentially formed on the substrate 10. Specifically, an isolation layer 11 is formed on the substrate 10, and a dielectric barrier layer (not shown) may be further distributed between the isolation layer 11 and the MIM capacitor 20, where the dielectric barrier layer includes a doped silicon carbide film (Nitride Doped Silicon Carbide, abbreviated as NDC), and is used to prevent the metal in the bottom plate 21 from diffusing into the isolation layer 11 and the substrate 10.
Illustratively, the substrate 10 may be at least one of the following mentioned materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. Isolation structures (not shown) are also formed in the substrate, which are Shallow Trench Isolation (STI) structures or local silicon oxide (LOCOS) isolation structures that divide the base into different active regions in which various semiconductor devices, such as NMOS and PMOS, may be formed.
Next, a lower plate 21 is formed on the spacer layer 11; the material of the lower plate 21 is metal, wherein the lower plate 21 may be formed by one of Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG), and in the present application, for example, physical Vapor Deposition (PVD), the material of the lower plate 21 includes at least one of copper, aluminum, tungsten, tiAl and TiN, and other suitable metal materials. In an example, the lower plate 21 is, for example, an Al thin film or a Cu thin film. In another example, the lower plate 21 is, for example, a stack of a bottom-up Al film, a Ti film, and a TiN film.
A material layer of the inter-plate dielectric layer 22 is formed to cover the lower electrode plate 21 and the isolation layer 11, and a material layer of the upper electrode plate 23 is formed on the surface of the material layer of the inter-plate dielectric layer 22. A photoresist layer (not shown) having a pattern defining the upper plate 23 is formed on the material layer of the upper plate 23 using a photolithography process. The photoresist layer may be a photoresist formed by a spin coating process, and then formed by processes such as exposure, development, cleaning, etc. Then, the material layer of the upper electrode plate 23 and the material layer of the inter-plate dielectric layer 22 are etched by using the photoresist layer as a mask, so as to form the patterned upper electrode plate 23 and inter-plate dielectric layer 22. Both the upper plate 23 and the inter-plate dielectric layer 22 expose a portion of the lower plate 21. Dry etching of the material layer of the upper plate 23 and the material layer of the inter-plate dielectric layer 22 may be employed, including but not limited to: reactive Ion Etching (RIE), ion beam etching, and plasma etching. The deposition method of the inter-plate dielectric layer 22 may be selected from Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), and the like. The material of the inter-plate dielectric layer 22 includes silicon nitride (Si 3 N 4 ) Silicon oxynitride (SiON), HFO 2 、ZrO、Al 2 O 3 And at least one of ZrO, as well as other suitable materials. The method for forming the upper electrode plate 23 is the same as the method for forming the lower electrode plate 21, and will not be described here again. The material of the upper plate 23 may be at least one of copper, aluminum, tungsten, tiAl, and TiN, as well as other suitable metallic materials.
Next, as shown in fig. 4, a first interlayer dielectric layer 30 is formed; the first interlayer dielectric layer 30 covers the MIM capacitor 20 and the isolation layer 11. The deposition method of the first interlayer dielectric layer 30 may be a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like. In the present application, a Chemical Vapor Deposition (CVD) method is preferred, and the material of the first interlayer dielectric layer 30 includes, but is not limited to, silicon dioxide (SiO 2). Chemical mechanical polishing is performed on the first interlayer dielectric layer 30 to achieve planarization.
First contact holes V for leading out the upper electrode plate 23 are respectively formed in the first interlayer dielectric layer 30 1 And a second contact hole V leading out of the lower plate 21 2 The method comprises the steps of carrying out a first treatment on the surface of the And at the first contact hole V 1 And a second contact hole V 2 The filler metal forms a first plug 41 and a second plug 42, respectively. The process of forming the contact hole may employ a dry etching process. Dry etching includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, and plasma etching. First contact hole V 1 Exposing the upper surface of the upper plate 23. Second contact hole V 2 The upper surface of the lower polar plate 21 is exposed, the second contact hole V 2 In the region of the lower plate 21 not covered (overlapped) by the upper plate 23.
A material layer of a floating metal layer is formed on the surface of the first interlayer dielectric layer 30. Specifically, photoresist can be formed on the material layer of the floating metal layer through spin coating, and then the patterned floating metal layer is formed through processes such as exposure, development, cleaning and the like. The patterned floating metal layer includes a first metal 51 connected to the first plug 41, a second metal 52 connected to the second plug 42, and a floating metal resistor 53. The floating metal layer forming method may be one of a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, and an Atomic Layer Deposition (ALD) method, and is selected as a Physical Vapor Deposition (PVD) method in the present application, a material of the floating metal layer such as TiN, and in other examples, the material of the floating metal layer may also include at least one of copper, aluminum, tungsten, and TiAl, and other suitable metal materials. The thickness of the floating metal layer is, for example, 800 to 2000 angstroms.
Next, as shown in fig. 5, a second interlayer dielectric layer 60 is formed, and the second interlayer dielectric layer 60 covers the floating metal layer and the first interlayer dielectric layer 30. Forming a top contact hole penetrating the second interlayer dielectric layer 60 to expose the floating metal layer; the top contact hole includes a third contact hole V leading out of the first metal 51 3 Fourth contact hole V for leading out second metal 52 4 And at least one fifth contact hole V leading out the floating metal resistor 53 5 The method comprises the steps of carrying out a first treatment on the surface of the And an interconnect metal layer (plug) is formed in the top contact hole by a deposition or electroplating process.Third contact hole V 3 A third plug 71 and a fourth contact hole V 4 A fourth plug 72 and a fifth contact hole V 5 A fifth plug 73 is formed. The plug material may be tungsten, copper or other suitable material. The floating metal resistor 53 passes through at least one fifth contact hole V 5 The plug in (C) is led out to the top metal layer. In particular, a redundancy design may be performed, for example, the floating metal resistor 53 is led out to the top metal layer through the fifth plugs 73 of two branches, and in case of a circuit break of one of the branches, the other branch may also function.
Next, as shown in fig. 5 and 6, a top metal layer is formed on the second interlayer dielectric layer 60, and the top metal layer includes a plurality of pads to connect and lead out the plugs in the top contact holes. Forming an insulating layer 91 covering the upper surface and the sidewalls of the top metal layer; a passivation layer 92 is formed to cover the insulating layer 91 and the surface of the second interlayer dielectric layer 60. The interconnect metal layer (plug) and the top metal layer in the top contact hole may be formed in the same process or may be formed separately. The method for forming the top metal layer can be Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), etc. The floating metal resistor 53 is directly led out to the third welding pad 83 through the fifth contact hole; the upper electrode plate 23 of the MIM capacitor 20 is led out to the first welding pad 81 through the first contact hole, the first metal 51 and the third contact hole in sequence; the lower electrode plate 21 of the MIM capacitor is led out to the second pad 82 through the second contact hole, the second metal 52 and the fourth contact hole in sequence.
The present application also provides a semiconductor device, as shown in fig. 6, comprising:
a substrate 10, a MIM capacitor 20 is formed on the substrate 10, the MIM capacitor 20 includes a lower plate 21 and an upper plate 23 opposite to each other;
a first interlayer dielectric layer 30 covering MIM capacitor 20 and substrate 10; a first contact hole for leading out the upper polar plate 23 and a second contact hole for leading out the lower polar plate 21 are respectively formed in the first interlayer dielectric layer 30;
a floating metal layer is formed on the surface of the first interlayer dielectric layer 30, and the floating metal layer comprises a first metal 51, a second metal 52 and a floating metal resistor 53; the upper electrode plate 23 is connected with the first metal 51 through a first contact hole, and the lower electrode plate 21 is connected with the second metal 52 through a second contact hole;
a second interlayer dielectric layer 60 covering the first interlayer dielectric layer 30 and the floating metal layer;
a top contact hole penetrating the second interlayer dielectric layer 60 to expose the floating metal layer; the top contact hole comprises a third contact hole leading out of the first metal 51, a fourth contact hole leading out of the second metal 52 and at least one fifth contact hole leading out of the floating metal resistor 53; the top contact hole is filled with metal;
the second interlayer dielectric layer 60 has a top metal layer formed on the surface thereof, and the top metal layer includes a plurality of pads for connecting and extracting the metals in the top contact holes.
MIM capacitor 20 further comprises an inter-plate dielectric layer 22 between upper plate 23 and lower plate 21. The floating metal resistor 53 is led out to the top metal layer through two parallel fifth contact holes. The material of the floating metal layer 53 includes at least one of TiN, copper, aluminum, and tungsten.
In summary, the present application provides a semiconductor device and a method for manufacturing the same, including: providing a substrate, wherein an MIM capacitor is formed on the substrate; a first interlayer dielectric layer is formed overlying the MIM capacitor and the substrate. Forming a first contact hole for leading out an upper polar plate and a second contact hole for leading out a lower polar plate in the first interlayer dielectric layer respectively; forming a floating metal layer, wherein the floating metal layer comprises a first metal, a second metal and a floating metal resistor; and forming a first metal and a second metal to respectively lead out an upper polar plate and a lower polar plate of the MIM capacitor while forming a floating metal resistor. The top contact hole penetrates through the second interlayer dielectric layer to expose the floating metal layer; the top contact hole comprises a third contact hole for leading out the first metal, a fourth contact hole for leading out the second metal and at least one fifth contact hole for leading out the floating metal resistor; and filling metal in the top contact hole. The heights of the top contact holes are consistent, so that the etching loss of the floating metal layer is conveniently controlled. The floating metal resistor is directly led out through the fifth contact hole; the upper polar plate of the MIM capacitor is led out through the first contact hole, the first metal and the third contact hole in sequence; the lower polar plate of the MIM capacitor is led out through the second contact hole, the second metal and the fourth contact hole in sequence. One layer of mask plate is reduced, and the cost is reduced; solving the problem that the photoetching alignment mark is not clearly seen; longer waiting time is avoided after the contact hole for leading out the floating metal resistor is formed, and efficiency is improved.
In the present specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, so that the same similar parts between the embodiments are all mutually referred to. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points are referred to the description of the method section.
The foregoing description is only illustrative of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present application using the method and technical content disclosed above without departing from the spirit and scope of the application, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present application fall within the scope of the technical solution of the present application.
Claims (10)
1. A method of fabricating a semiconductor device, comprising:
providing a substrate, wherein an MIM capacitor is formed on the substrate, and the MIM capacitor comprises a lower polar plate and an upper polar plate which are opposite;
forming a first interlayer dielectric layer covering the MIM capacitor and the substrate; forming a first contact hole leading out the upper polar plate and a second contact hole leading out the lower polar plate in the first interlayer dielectric layer respectively;
forming a floating metal layer on the surface of the first interlayer dielectric layer, wherein the floating metal layer comprises a first metal, a second metal and a floating metal resistor; the upper polar plate is connected with the first metal through the first contact hole, and the lower polar plate is connected with the second metal through the second contact hole;
forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the floating metal layer;
forming a top contact hole, wherein the top contact hole penetrates through the second interlayer dielectric layer to expose the floating metal layer; the top contact hole comprises a third contact hole leading out of the first metal, a fourth contact hole leading out of the second metal and at least one fifth contact hole leading out of the floating metal resistor; filling metal in the top contact hole;
and forming a top metal layer on the surface of the second interlayer dielectric layer, wherein the top metal layer comprises a plurality of welding pads for connecting and leading out the metal in each top contact hole.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the floating metal layer is formed by at least one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, laser ablation deposition, and selective epitaxial growth.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the floating metal layer comprises at least one of TiN, copper, aluminum, and tungsten.
4. The method of manufacturing a semiconductor device according to claim 1, further comprising: and filling metal in the first contact hole and the second contact hole to form a first plug and a second plug respectively.
5. The method of manufacturing a semiconductor device according to claim 1, further comprising: and sequentially forming an isolation layer and a dielectric barrier layer between the substrate and the MIM capacitor.
6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, further comprising, after forming the top metal layer:
forming an insulating layer covering the upper surface and the side wall of the top metal layer;
and forming a passivation layer covering the insulating layer and the surface of the second interlayer dielectric layer.
7. A semiconductor device, comprising:
a substrate, on which a MIM capacitor is formed, the MIM capacitor comprising a lower plate and an upper plate opposite to each other;
a first interlayer dielectric layer covering the MIM capacitor and the substrate; a first contact hole for leading out the upper polar plate and a second contact hole for leading out the lower polar plate are respectively formed in the first interlayer dielectric layer;
a floating metal layer is formed on the surface of the first interlayer dielectric layer, and the floating metal layer comprises a first metal, a second metal and a floating metal resistor; the upper polar plate is connected with the first metal through the first contact hole, and the lower polar plate is connected with the second metal through the second contact hole;
a second interlayer dielectric layer covering the first interlayer dielectric layer and the floating metal layer;
the top contact hole penetrates through the second interlayer dielectric layer to expose the floating metal layer; the top contact hole comprises a third contact hole leading out of the first metal, a fourth contact hole leading out of the second metal and at least one fifth contact hole leading out of the floating metal resistor; the top contact hole is filled with metal;
and a top metal layer is formed on the surface of the second interlayer dielectric layer, and comprises a plurality of welding pads for connecting and leading out the metal in each top contact hole.
8. The semiconductor device of claim 7, wherein the MIM capacitor further comprises an inter-plate dielectric layer between the upper plate and the lower plate.
9. The semiconductor device of claim 7, wherein the floating metal resistor is extracted to the top metal layer through two fifth contact holes in parallel.
10. The semiconductor device according to claim 7, wherein a material of the floating metal layer comprises at least one of TiN, copper, aluminum, and tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310944582.8A CN116782758A (en) | 2023-07-28 | 2023-07-28 | Semiconductor device and method for manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310944582.8A CN116782758A (en) | 2023-07-28 | 2023-07-28 | Semiconductor device and method for manufacturing the same |
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| CN116782758A true CN116782758A (en) | 2023-09-19 |
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| CN202310944582.8A Pending CN116782758A (en) | 2023-07-28 | 2023-07-28 | Semiconductor device and method for manufacturing the same |
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| Country | Link |
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| CN (1) | CN116782758A (en) |
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- 2023-07-28 CN CN202310944582.8A patent/CN116782758A/en active Pending
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