CN116887667A - MIM capacitor and manufacturing method thereof - Google Patents
MIM capacitor and manufacturing method thereof Download PDFInfo
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- CN116887667A CN116887667A CN202310946000.XA CN202310946000A CN116887667A CN 116887667 A CN116887667 A CN 116887667A CN 202310946000 A CN202310946000 A CN 202310946000A CN 116887667 A CN116887667 A CN 116887667A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 278
- 239000011229 interlayer Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims description 121
- 239000002184 metal Substances 0.000 claims description 121
- 238000000034 method Methods 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 12
- 238000000231 atomic layer deposition Methods 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000000608 laser ablation Methods 0.000 claims description 3
- -1 tiAl Chemical compound 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 25
- 238000001020 plasma etching Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 239000012212 insulator Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application provides a MIM capacitor and a manufacturing method thereof, wherein the MIM capacitor comprises: a substrate, a lower polar plate, an upper polar plate and an interlayer dielectric layer which are positioned on the substrate; the upper polar plate is in a step shape and comprises an upper step part, a lower step part and a step side wall; the upper step part covers part of the lower polar plate; an inter-plate dielectric layer is formed between the upper step part and the lower polar plate, and a side wall dielectric layer is formed between the side wall of the lower polar plate and the side wall of the step; the first contact hole exposes the upper surface of the lower step portion; the second contact hole exposes the upper surface of the lower electrode plate. The upper polar plate is in a step shape, and an electric signal of the upper polar plate is led out from the lower step part through the first contact hole, so that the height difference between the bottom of the first contact hole and the bottom of the second contact hole is reduced, the etching difficulty is reduced, and the over etching of the first contact hole is avoided; the first contact hole does not overlap the region of the upper step part and the lower polar plate, so that the problem of short circuit between the upper polar plate and the lower polar plate caused by over etching of the first contact hole is thoroughly avoided.
Description
Technical Field
The application belongs to the technical field of integrated circuit manufacturing, and particularly relates to an MIM capacitor and a manufacturing method thereof.
Background
MIM (Metal-insulator-Metal) capacitors are widely used in semiconductor integrated circuits as charge storage, coupling and filtering devices. FIG. 1 shows a MIM capacitor junctionA cross-sectional view of the structure; fig. 2 is a top view of fig. 1. As shown in fig. 1 and 2, the MIM capacitor structure comprises a bottom dielectric layer 01, a bottom metal layer 02, a bottom plate 03, a top plate 05, and an inter-plate dielectric layer 04 between the bottom plate 03 and the top plate 05, and the structure can realize a charge storage function. The MIM capacitor structure further comprises an interlayer dielectric layer 06 covering the lower electrode plate 03 and the upper electrode plate 05, wherein a top metal layer is formed on the surface of the interlayer dielectric layer 06, and a contact hole V is formed in the interlayer dielectric layer 06 1 Contact hole two V 2 And contact hole three V 3 The upper polar plate 05 passes through the contact hole V 1 The interconnection metal in (a) is connected to the first metal layer 07 of the top layer, and the lower electrode plate 03 passes through the second V contact hole 2 The interconnection metal in the metal layer is connected to the second metal layer 08 at the top layer, and the metal layer 02 at the bottom layer passes through the contact hole III V 3 Is connected to the top metal layer three 09.
Contact hole V 1 Contact hole two V 2 And contact hole three V 3 Formed in the same etching process. Contact hole V 1 The bottom of the electrode is the upper surface of the upper polar plate 05, and the contact hole is two V 2 The bottom of (a) is the upper surface of the lower polar plate 01, and the contact hole is three V 3 The bottom of (2) is the lower surface of the lower polar plate 03. Because the upper surface of the upper polar plate 05 has a larger height difference from the upper surface and the lower surface of the lower polar plate 03 respectively, i.e. the contact hole is V 1 Respectively with contact hole two V 2 And contact hole three V 3 All have larger height difference, and the contact hole is V 1 With contact hole III V 3 The height difference between the two is h 1 Contact hole V 1 Is easy to have over-etching risk and is one V due to the contact hole 1 In the overlapping (stacked) position of both the upper plate 05 and the lower plate 03, thus contacting the hole-V 1 Is prone to shorting the upper plate 05 to the lower plate 03, thereby disabling the MIM capacitor.
Disclosure of Invention
The application aims to provide an MIM capacitor and a manufacturing method thereof, wherein an upper polar plate is in a step shape, and an electric signal of the upper polar plate is led out from a lower step part to a first top metal layer through a first contact hole, so that the height difference between the bottom of the first contact hole and the bottom of a second contact hole is reduced, the etching difficulty is reduced, and the over etching of the first contact hole is avoided; meanwhile, the first contact hole is led out from the lower step part, and the first contact hole is not in an overlapped (laminated) area of the upper step part and the lower polar plate, so that the problem of short circuit between the upper polar plate and the lower polar plate caused by over etching of the first contact hole is thoroughly avoided.
The application provides a manufacturing method of an MIM capacitor, which comprises the following steps:
providing a substrate, and sequentially forming a lower polar plate and an inter-plate dielectric layer on the substrate;
forming a side wall dielectric layer, wherein the side wall dielectric layer is positioned on the side wall of the lower polar plate and the inter-plate dielectric layer;
forming an upper polar plate which is in a step shape and comprises an upper step part, a lower step part and a step side wall connecting the upper step part and the lower step part;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the upper polar plate and the inter-plate dielectric layer;
forming a contact hole in the interlayer dielectric layer, wherein the contact hole comprises a first contact hole and a second contact hole; the first contact hole exposes the upper surface of the lower step part, and the second contact hole exposes the upper surface of the lower polar plate and is positioned in a region of the lower polar plate which is not covered by the upper step part;
forming a top metal layer on the surface of the interlayer dielectric layer, wherein the top metal layer comprises a first top metal layer and a second top metal layer; the lower step part is led out to the first top metal layer through the first contact hole, and the lower polar plate is led out to the second top metal layer through the second contact hole.
Further, the manufacturing method further comprises the following steps: and forming a bottom dielectric layer between the substrate and the lower polar plate, and forming a bottom metal layer in the bottom dielectric layer.
Further, the forming of the contact hole further includes forming a third contact hole, where the third contact hole penetrates through the interlayer dielectric layer and exposes the bottom metal layer; the top metal layer further comprises a third top metal layer, and the bottom metal layer is led out to the third top metal layer through the third contact hole.
Further, the upper electrode plate is formed by at least one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, laser ablation deposition and selective epitaxial growth.
Further, the material of the upper electrode plate comprises at least one of copper, aluminum, tungsten, tiAl and TiN.
The application also provides an MIM capacitor, which comprises:
a substrate, a lower polar plate, an upper polar plate and an interlayer dielectric layer which are positioned on the substrate;
the upper polar plate is in a step shape and comprises an upper step part, a lower step part and a step side wall connecting the upper step part and the lower step part; the upper step part covers part of the lower polar plate; an inter-plate dielectric layer is formed between the upper step part and the lower polar plate, and a side wall dielectric layer is formed between the side wall of the lower polar plate and the side wall of the step;
the interlayer dielectric layer covers the upper polar plate and the inter-plate dielectric layer; a contact hole is formed in the interlayer dielectric layer, the contact hole comprises a first contact hole and a second contact hole, and the first contact hole exposes the upper surface of the lower step part; the second contact hole exposes the upper surface of the lower polar plate, and is positioned in a region of the lower polar plate which is not covered by the upper step part; a top metal layer is formed on the surface of the interlayer dielectric layer, and comprises a first top metal layer and a second top metal layer; the lower step part is led out to the first top metal layer through the first contact hole, and the lower polar plate is led out to the second top metal layer through the second contact hole.
Further, a bottom dielectric layer and a dielectric barrier layer are sequentially formed on the substrate, a bottom metal layer is formed in the bottom dielectric layer and the dielectric barrier layer, and the lower polar plate is located on the surface of the dielectric barrier layer.
Further, the contact hole further comprises a third contact hole, the top metal layer further comprises a third top metal layer, and the bottom metal layer is led out to the third top metal layer through the third contact hole.
Further, the difference in height between the bottom of the first contact hole and the bottom of the third contact hole is 1000 angstroms or less.
Further, two parallel first contact holes are formed between the lower step part and the first top metal layer, a first interconnection layer and a second interconnection layer are respectively formed in the two first contact holes, and the lower step part is led out to the first top metal layer through the parallel first interconnection layer and second interconnection layer.
Compared with the prior art, the application has the following beneficial effects:
the application provides a MIM capacitor and a manufacturing method thereof, wherein the MIM capacitor comprises: a substrate, a lower polar plate, an upper polar plate and an interlayer dielectric layer which are positioned on the substrate; the upper polar plate is in a step shape and comprises an upper step part, a lower step part and a step side wall; the upper step part covers part of the lower polar plate; an inter-plate dielectric layer is formed between the upper step part and the lower polar plate, and a side wall dielectric layer is formed between the side wall of the lower polar plate and the side wall of the step; a first contact hole and a second contact hole are formed in the interlayer dielectric layer, and the first contact hole exposes the upper surface of the lower step part; the second contact hole exposes the upper surface of the lower polar plate; the lower step part is led out to the first top metal layer through the first contact hole, and the lower polar plate is led out to the second top metal layer through the second contact hole. The upper polar plate is in a step shape, and an electric signal of the upper polar plate is led out from the lower step part to the first top metal layer through the first contact hole, so that the height difference between the bottom of the first contact hole and the bottom of the second contact hole is reduced, the etching difficulty is reduced, and the over etching of the first contact hole is avoided; meanwhile, the first contact hole is led out from the lower step part, and the first contact hole is not in an overlapped (laminated) area of the upper step part and the lower polar plate, so that the problem of short circuit between the upper polar plate and the lower polar plate caused by over etching of the first contact hole is thoroughly avoided.
Drawings
Fig. 1 is a cross-sectional view of a MIM capacitor structure.
Fig. 2 is a top view of fig. 1.
Fig. 3 is a flow chart of a method for fabricating a MIM capacitor according to an embodiment of the present application.
Fig. 4 to 11 are schematic views illustrating steps of a method for fabricating a MIM capacitor according to an embodiment of the present application.
Wherein, the reference numerals are as follows:
01-a bottom dielectric layer; 02-a bottom metal layer; 03-lower polar plate; 04-an inter-plate dielectric layer; 05-upper polar plate; v (V) 1 -a contact hole one; v (V) 2 -a second contact hole; v (V) 3 -contact holes three; 06-an interlayer dielectric layer; 07-top metal layer one; 08-top metal layer two; 09—top metal layer three;
11-a substrate; 12-a bottom dielectric layer; 13-an underlying metal layer; 14-a dielectric barrier layer; 21-a lower polar plate; 22-inter-plate dielectric layer; c-side wall material layers; 23-a side wall dielectric layer; 24-upper polar plate; 24 a-a lower step; 24 b-step side walls; 24 c-an upper step; 25-an interlayer dielectric layer; 31-a first contact hole; 32-a second contact hole; 33-a third contact hole; 41-a first top metal layer; 411-a first interconnect layer; 412-a second interconnect layer; 42-a second top metal layer; 43-third top metal layer.
Detailed Description
The application is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present application will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the application.
For ease of description, some embodiments of the application may use spatially relative terms such as "above" …, "" below "…," "top," "below," and the like to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that these terms so used may be substituted where appropriate.
The embodiment of the application provides a manufacturing method of an MIM capacitor, which is shown in figure 3 and comprises the following steps:
step S1, providing a substrate, and sequentially forming a lower polar plate and an inter-plate dielectric layer on the substrate;
s2, forming a side wall dielectric layer, wherein the side wall dielectric layer is positioned on the side wall of the lower polar plate and the inter-polar plate dielectric layer;
s3, forming an upper polar plate which is in a step shape and comprises an upper step part, a lower step part and a step side wall connecting the upper step part and the lower step part;
s4, forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the upper polar plate and the inter-plate dielectric layer;
s5, forming contact holes in the interlayer dielectric layer, wherein the contact holes comprise first contact holes and second contact holes; the first contact hole exposes the upper surface of the lower step part, and the second contact hole exposes the upper surface of the lower polar plate and is positioned in a region of the lower polar plate which is not covered by the upper step part;
s6, forming a top metal layer on the surface of the interlayer dielectric layer, wherein the top metal layer comprises a first top metal layer and a second top metal layer; the lower step part is led out to the first top metal layer through the first contact hole, and the lower polar plate is led out to the second top metal layer through the second contact hole.
The following describes in detail the steps of the method for fabricating the MIM capacitor according to the embodiment of the present application with reference to fig. 4 to 11.
As shown in fig. 4, a substrate 11 is provided, and a lower plate 21 and an inter-plate dielectric layer 22 are sequentially formed on the substrate 11. Specifically, a substrate 11 is provided, on which a bottom dielectric layer 12 may be formed on the substrate 11, and a bottom metal layer 13 is distributed in the bottom dielectric layer 12. The bottom dielectric layer 12 may further have a dielectric barrier layer 14 disposed thereon, where the dielectric barrier layer 14 includes a doped silicon carbide film (Nitride Doped Silicon Carbide, abbreviated as NDC), and the dielectric barrier layer 14 is used to prevent diffusion of metal in the subsequently formed bottom plate 21 into the bottom dielectric layer 12 and the substrate 11.
Illustratively, the substrate 11 may be at least one of the following mentioned materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. Isolation structures (not shown) are also formed in the substrate, which are Shallow Trench Isolation (STI) structures or local silicon oxide (LOCOS) isolation structures that divide the base into different active regions in which various semiconductor devices, such as NMOS and PMOS, may be formed.
Next, a material layer of the lower plate 21 and a material layer of the inter-plate dielectric layer 22 are sequentially formed on the dielectric barrier layer 14, and a photoresist layer (not shown) having a pattern defining the lower plate 21 is formed on the material layer of the inter-plate dielectric layer 22 using a photolithography process. The photoresist layer may be a photoresist formed by a spin coating process, and then formed by processes such as exposure, development, cleaning, etc. Then, the material layer of the inter-plate dielectric layer 22 and the material layer of the lower electrode plate 21 are etched by using the photoresist layer as a mask, so that the patterned lower electrode plate 21 and the inter-plate dielectric layer 22 are formed. Dry etching of the material layer of the inter-plate dielectric layer 22 and the material layer of the lower plate 21 may be employed, including but not limited to: reactive Ion Etching (RIE), ion beam etching, and plasma etching.
The material of the lower plate 21 is metal, wherein the lower plate 21 may be formed by one of Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG), and in the present application, for example, physical Vapor Deposition (PVD), the material of the lower plate 21 includes at least one of copper, aluminum, tungsten, tiAl and TiN, and other suitable metal materials. In an example, the lower plate 21 is, for example, an Al thin film or a Cu thin film. In another example, the lower plate 21 is, for example, a stack of a bottom-up Al film, a Ti film, and a TiN film.
The deposition method of the inter-plate dielectric layer 22 may be selected from Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), and the like. The material of the inter-plate dielectric layer 22 includes silicon nitride (Si 3 N 4 ) Silicon oxynitride (SiON), HFO 2 、ZrO、Al 2 O 3 And at least one of ZrO, as well as other suitable materials. As an example, the thickness of the bottom plate 21 is, for example, 2000 a to 5000 a, and the thickness of the inter-plate dielectric layer 22 is, for example, 300 a to 800 a.
As shown in fig. 5 and 6, a side wall dielectric layer 23 is formed; specifically, a side wall material layer C is formed, and covers the side walls of the lower electrode plate 21 and the inter-plate dielectric layer 22, the upper surface of the inter-plate dielectric layer 22, and the upper surfaces of the dielectric barrier layer 14 and the bottom metal layer 13. Etching the side wall material layer C, and removing the side wall material layer C on the upper surface of the inter-plate dielectric layer 22 and the upper surfaces of the dielectric barrier layer 14 and the bottom metal layer 13; and leaving the side wall material layer C of the side walls of the lower polar plate 21 and the inter-plate dielectric layer 22 to form a side wall dielectric layer 23. The side wall material layer C may be etched by Reactive Ion Etching (RIE), ion beam etching, plasma etching, or the like. The material of the sidewall dielectric layer 23 includes silicon nitride (Si 3 N 4 ) Or silicon oxynitride (SiON), etc.
As shown in fig. 7, the upper plate 24 is formed in a stepped shape, and includes an upper stepped portion 24c, a lower stepped portion 24a, and a stepped side wall 24b (a part in a broken line frame) connecting the upper stepped portion 24c and the lower stepped portion 24 a. The method for forming the upper electrode plate 24 is the same as the method for forming the lower electrode plate 21, and will not be described here again. The upper step 24c covers part of the lower plate 21, and the inter-plate dielectric layer 22 located between the overlapping areas of the upper step 24c and the lower plate 21 serves as a dielectric layer of the MIM capacitor. The material of the upper plate 24c may be selected from at least one of copper, aluminum, tungsten, tiAl, and TiN, as well as other suitable metallic materials. And a side wall dielectric layer 23 is formed between the side wall of the lower polar plate 21 and the step side wall 24b of the upper polar plate 24 to prevent the upper polar plate 24 from being short-circuited with the lower polar plate 21.
Next, an interlayer dielectric layer 25 is formed; an interlayer dielectric layer 25 covers the upper plate 24 and the inter-plate dielectric layer 22. The deposition method of the interlayer dielectric layer 25 may be a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like. In the present application, a Chemical Vapor Deposition (CVD) method is preferred, and the material of the interlayer dielectric layer 25 includes, but is not limited to, silicon dioxide (SiO 2). Chemical mechanical polishing is performed on the interlayer dielectric layer 25 to achieve planarization.
As shown in fig. 8, contact holes are formed in the interlayer dielectric layer 25, and the contact holes include a first contact hole 31, a second contact hole 32, and a third contact hole 33. The process of forming the contact hole may employ a dry etching process. Dry etching includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, and plasma etching. The first contact hole 31 exposes the upper surface of the lower step portion 24a of the upper plate 24. The second contact hole 32 exposes the upper surface of the lower plate 21, and the second contact hole 32 is located in a region of the lower plate 21 not covered (overlapped) by the upper step portion 24 c. The third contact hole 33 exposes the upper surface of the underlying metal layer 13.
Fig. 9 is a cross-sectional view of a MIM capacitor according to an embodiment of the present application after a top metal layer is formed; fig. 10 is a top view of the MIM capacitor portion of fig. 9. As shown in fig. 9 and 10, a top metal layer is formed, and the top electrode plate 24, the bottom electrode plate 21, and the bottom metal layer 13 are led out to the top metal layer, respectively. An interconnect metal layer (plug) is formed in the contact hole by a deposition or electroplating process, and the interconnect metal layer may be made of tungsten, copper or other suitable materials. The lower step portion 24a of the upper electrode plate 24 is led out to the first top metal layer 41 through the interconnection metal layer in the first contact hole 31, and specifically redundancy design may be performed, for example, the lower step portion 24a is led out to the first top metal layer 41 through the two branch first interconnection layers 411 and the second interconnection layers 412, and in case one branch has a problem of disconnection, the other branch may also function. The region of the lower plate 21 not covered (overlapped) by the upper step portion 24c is led out to the second top metal layer 42 through the interconnect metal layer in the second contact hole 32. The bottom metal layer 13 is led out to the third top metal layer 43 through the interconnection metal layer in the third opening 33, so as to realize interconnection between metal layers of different layers in the MIM capacitor.
The interconnection metal layer (plug) and the top metal layer in the contact hole can be formed in the same process or can be formed separately. The method for forming the top metal layer can be Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), etc. As an example, the lower step 24a of the upper plate 24 of the MIM capacitor has a thickness of 1000 a or less.
Fig. 11 is a cross-sectional view of a first contact hole over-etching state of a MIM capacitor according to an embodiment of the present application. As shown in fig. 11, in case that the first contact hole 31 is over-etched, for example, the first contact hole 31 has penetrated the lower step portion 24a of the upper plate 24 of a part of the thickness, the interconnection metal layer (plug) filled in the first contact hole 31 may also achieve electrical connection with the lower step portion 24 a.
As shown in fig. 9, in the first example, the contact holes include a first contact hole 31 and a second contact hole 32. In this example, the upper electrode plate 24 is stepped, and an electrical signal of the upper electrode plate 24 is led out from the lower stepped portion 24a through the first contact hole 31, and the lower electrode plate 21 is led out through the second contact hole 32. The first example reduces the difference in height between the bottom of the first contact hole 31 and the bottom of the second contact hole 32, thereby reducing the etching difficulty and avoiding over-etching of the first contact hole 31; the first contact hole 31 does not overlap the upper step portion 24c and the lower electrode plate 21, and the problem of short circuit between the upper electrode plate 24 and the lower electrode plate 21 caused by over etching of the first contact hole 31 is thoroughly avoided.
As shown in fig. 9, in the second example, the contact holes include a first contact hole 31, a second contact hole 32, and a third opening 33. The bottom metal layer 13 is led out to the third top metal layer 43 through the interconnection metal layer in the third opening 33, so as to realize interconnection between metal layers of different layers in the MIM capacitor. In the second example, the upper electrode plate 24 is stepped, the electrical signal of the upper electrode plate 24 is led out from the lower stepped portion 24a through the first contact hole 31, the lower electrode plate 21 is led out through the second contact hole 32, and the underlying metal layer 13 is led out through the third opening 33. The second example reduces the difference in height between the bottom of the first contact hole 31 and the bottom of the second contact hole 32, and also reduces the difference in height h between the bottom of the first contact hole 31 and the bottom of the third opening 33 2 . Exemplary, the height difference h between the bottom of the first contact hole 31 and the bottom of the third opening 33 2 1000 angstroms or less. Such asFIG. 1 shows a contact hole-V before modification 1 With contact hole III V 3 The height difference between the two is h 1 . By improving the embodiment, the height difference between the bottoms of the contact holes for leading out the signals of the upper polar plate and the bottoms of the contact holes for leading out the bottom metal layer 13 is changed from h 1 Reduced to h 2 Δh is reduced, so that the etching difficulty is reduced, and over-etching of the first contact hole 31 is avoided; the first contact hole 31 does not overlap the upper step portion 24c and the lower electrode plate 21, and the problem of short circuit between the upper electrode plate 24 and the lower electrode plate 21 caused by over etching of the first contact hole 31 is thoroughly avoided.
The present application also provides a MIM capacitor, as shown in fig. 9, comprising:
a substrate 11, a lower electrode plate 21, an upper electrode plate 24 and an interlayer dielectric layer 25 which are positioned on the substrate 11;
the upper electrode plate 24 is in a step shape and comprises an upper step part 24c, a lower step part 24a and a step side wall 24b connecting the upper step part 24c and the lower step part 24 a; the upper step 24c covers part of the lower plate 21; an inter-plate dielectric layer 22 is formed between the upper step portion 24c and the lower electrode plate 21, and a side wall dielectric layer 23 is formed between the side wall of the lower electrode plate 21 and the step side wall 24 b.
An interlayer dielectric layer 25 covers the upper electrode plate 24 and the inter-plate dielectric layer 22; a contact hole is formed in the interlayer dielectric layer 25, the contact hole including a first contact hole 31 and a second contact hole 32, the first contact hole 31 exposing an upper surface of the lower step portion 24 a; the second contact hole 32 exposes the upper surface of the lower plate 21, and the second contact hole 32 is located in a region of the lower plate 21 not covered by the upper step portion 24 c; a top metal layer is formed on the surface of the interlayer dielectric layer 25, and the top metal layer comprises a first top metal layer 41 and a second top metal layer 42; the lower step portion 24a is led out to the first top metal layer 41 through the first contact hole 31, and the lower electrode plate 21 is led out to the second top metal layer 42 through the second contact hole 32.
Specifically, the substrate 11 is further formed with a bottom dielectric layer 12 and a dielectric barrier layer 14 in sequence, a bottom metal layer 13 is formed in the bottom dielectric layer 12 and the dielectric barrier layer 14, and the lower electrode plate 21 is located on the surface of the dielectric barrier layer 14. The contact holes further include third contact holes 33, the top metal layer further includes third top metal layer 43, and bottom metal layer 13 is led out to third top metal layer 43 through third contact holes 33. The difference in height between the bottoms of the first contact holes 31 and the third contact holes 43 is 1000 angstroms or less.
In summary, the present application provides a MIM capacitor and a method for manufacturing the same, the MIM capacitor includes: a substrate, a lower polar plate, an upper polar plate and an interlayer dielectric layer which are positioned on the substrate; the upper polar plate is in a step shape and comprises an upper step part, a lower step part and a step side wall; the upper step part covers part of the lower polar plate; an inter-plate dielectric layer is formed between the upper step part and the lower polar plate, and a side wall dielectric layer is formed between the side wall of the lower polar plate and the side wall of the step; a first contact hole and a second contact hole are formed in the interlayer dielectric layer, and the first contact hole exposes the upper surface of the lower step part; the second contact hole exposes the upper surface of the lower polar plate; the lower step part is led out to the first top metal layer through the first contact hole, and the lower polar plate is led out to the second top metal layer through the second contact hole. The upper polar plate is in a step shape, and an electric signal of the upper polar plate is led out from the lower step part to the first top metal layer through the first contact hole, so that the height difference between the bottom of the first contact hole and the bottom of the second contact hole is reduced, the etching difficulty is reduced, and the over etching of the first contact hole is avoided; meanwhile, the first contact hole is led out from the lower step part, and the first contact hole is not in an overlapped (laminated) area of the upper step part and the lower polar plate, so that the problem of short circuit between the upper polar plate and the lower polar plate caused by over etching of the first contact hole is thoroughly avoided.
In the present specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, so that the same similar parts between the embodiments are all mutually referred to. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points are referred to the description of the method section.
The foregoing description is only illustrative of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present application using the method and technical content disclosed above without departing from the spirit and scope of the application, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present application fall within the scope of the technical solution of the present application.
Claims (10)
1. The manufacturing method of the MIM capacitor is characterized by comprising the following steps of:
providing a substrate, and sequentially forming a lower polar plate and an inter-plate dielectric layer on the substrate;
forming a side wall dielectric layer, wherein the side wall dielectric layer is positioned on the side wall of the lower polar plate and the inter-plate dielectric layer;
forming an upper polar plate which is in a step shape and comprises an upper step part, a lower step part and a step side wall connecting the upper step part and the lower step part;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the upper polar plate and the inter-plate dielectric layer;
forming a contact hole in the interlayer dielectric layer, wherein the contact hole comprises a first contact hole and a second contact hole; the first contact hole exposes the upper surface of the lower step part, and the second contact hole exposes the upper surface of the lower polar plate and is positioned in a region of the lower polar plate which is not covered by the upper step part;
forming a top metal layer on the surface of the interlayer dielectric layer, wherein the top metal layer comprises a first top metal layer and a second top metal layer; the lower step part is led out to the first top metal layer through the first contact hole, and the lower polar plate is led out to the second top metal layer through the second contact hole.
2. The method of fabricating a MIM capacitor according to claim 1, further comprising: and forming a bottom dielectric layer between the substrate and the lower polar plate, and forming a bottom metal layer in the bottom dielectric layer.
3. The method of claim 2, wherein forming the contact hole further comprises forming a third contact hole that penetrates the interlayer dielectric layer and exposes the underlying metal layer; the top metal layer further comprises a third top metal layer, and the bottom metal layer is led out to the third top metal layer through the third contact hole.
4. The method of claim 1, wherein forming the top plate comprises at least one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, laser ablation deposition, and selective epitaxial growth.
5. The method of claim 1, wherein the material of the top plate comprises at least one of copper, aluminum, tungsten, tiAl, and TiN.
6. A MIM capacitor, comprising:
a substrate, a lower polar plate, an upper polar plate and an interlayer dielectric layer which are positioned on the substrate;
the upper polar plate is in a step shape and comprises an upper step part, a lower step part and a step side wall connecting the upper step part and the lower step part; the upper step part covers part of the lower polar plate; an inter-plate dielectric layer is formed between the upper step part and the lower polar plate, and a side wall dielectric layer is formed between the side wall of the lower polar plate and the side wall of the step;
the interlayer dielectric layer covers the upper polar plate and the inter-plate dielectric layer; a contact hole is formed in the interlayer dielectric layer, the contact hole comprises a first contact hole and a second contact hole, and the first contact hole exposes the upper surface of the lower step part; the second contact hole exposes the upper surface of the lower polar plate, and is positioned in a region of the lower polar plate which is not covered by the upper step part; a top metal layer is formed on the surface of the interlayer dielectric layer, and comprises a first top metal layer and a second top metal layer; the lower step part is led out to the first top metal layer through the first contact hole, and the lower polar plate is led out to the second top metal layer through the second contact hole.
7. The MIM capacitor according to claim 6 wherein an underlying dielectric layer and a dielectric barrier layer are further formed in sequence on the substrate, an underlying metal layer is formed in the underlying dielectric layer and the dielectric barrier layer, and the lower plate is located on the surface of the dielectric barrier layer.
8. The MIM capacitor according to claim 7 wherein the contact hole further comprises a third contact hole and the top metal layer further comprises a third top metal layer through which the bottom metal layer is extracted to the third top metal layer.
9. The MIM capacitor according to claim 8 wherein the difference in height between the first contact hole bottom and the third contact hole bottom is 1000 angstroms or less.
10. The MIM capacitor according to claim 6 wherein two first contact holes are formed in parallel between the lower step portion and the first top metal layer, wherein a first interconnect layer and a second interconnect layer are formed in the two first contact holes, respectively, and wherein the lower step portion is led out to the first top metal layer through the first interconnect layer and the second interconnect layer in parallel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310946000.XA CN116887667A (en) | 2023-07-28 | 2023-07-28 | MIM capacitor and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310946000.XA CN116887667A (en) | 2023-07-28 | 2023-07-28 | MIM capacitor and manufacturing method thereof |
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| CN116887667A true CN116887667A (en) | 2023-10-13 |
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