JPH01150338A - Formation of wiring - Google Patents

Abstract

PURPOSE:To largely simplify a wiring formation process by selectively forming semiconductor layers by vapor growth in first and second openings, forming wiring layers on the semiconductor layers of the opening, and forming another wiring layer on the wiring layer. CONSTITUTION:First openings 7a, 7b are formed in insulating layers 3, 6 containing the end 4d of a polycrystalline Si layer 4 on semiconductor substrates 1a, 1b, and a second opening 8 for exposing an impurity region 5c for connecting another wiring layer is formed on a substrate 1c. The end 4d of the layer 4 and an impurity region 5a are exposed in the opening 7a, and the end 4d and an impurity region 5b are exposed in the opening 7b. Then, a polycrystalline Si layer 9 is formed by vapor growth in the respective openings, a high resistance wiring layer 10 is formed on a whole surface, and the thick interlayer insulating layer 6 of the flat surface is selectively removed. This layer is covered with a silicon nitride film 11, and an interlayer insulating layer 12 is formed on the film 11. Subsequently, an opening 14 is formed on the substrate 1c, and an aluminum wiring layer 13 is, after reflowing, electrically connected through the layers 10, 9 to the region 5c of the substrate 1c.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring formation method for a semiconductor device having a so-called shared contact, and in particular, for example, an SRAM.
The present invention relates to a wiring formation method used in semiconductor memory devices such as (static RAM).

[Summary of the invention]

The present invention relates to a wiring forming method in which a semiconductor layer is formed in an opening by vapor phase growth such as selective epitaxial method to electrically connect a first wiring layer and a semiconductor substrate. A semiconductor layer is formed in each opening by selective vapor growth, a second wiring layer is formed on each semiconductor layer, and a second wiring layer is formed on the second wiring layer. By forming the third wiring layer in the third wiring layer, the process can be simplified.

[Conventional technology]

In the manufacturing process of ultra-large-scale integrated circuits, especially memory devices, as their capacity increases, prices decrease, and design rules shrink, there are demands to reduce memory cell size, simplify processes, and improve the aspect ratio of contact holes in aluminum wiring layers. requested.

Incidentally, one of the factors that determines the memory cell size is the area occupied by the connection portion between the semiconductor substrate in which the impurity diffusion region is formed and the interconnection layer made of a polycrystalline silicon layer that becomes the gate.

FIG. 2 is a sectional view of a conventional so-called shared contact portion. A gate insulating film 53 and a field oxide film 52 are formed on a semiconductor substrate 51, and a polycrystalline silicon layer 54 serving as a gate electrode is formed on top of the gate insulating film 53. The end of this polycrystalline silicon layer 54 extends into an opening 57 formed in the interlayer insulation 155, and the N0 type impurity region w4 formed on the surface of the semiconductor substrate 51 is formed in the opening 57.
The gate insulator Ji53 on the surface is removed inside.

End surfaces 54a of these polycrystalline silicon layers 54
A second polycrystalline silicon layer 58 is formed in the opening 57 so as to be connected to both the surface 51a of the impurity region 56 and the surface 51a of the impurity region 56.

In the structure shown in Fig. 2, the occupied area is
It is not easy to reduce the cell size because it is affected by the pattern rule of the N-th polycrystalline silicon layer 58. That is, since a margin is required when patterning the second polycrystalline silicon layer 58, the cell size cannot be reduced much.

Therefore, as shown in FIG. 3, a technique has been proposed in which the so-called shared contact portion is buried with a polycrystalline silicon layer. In this method, a gate insulating layer 63 and a field oxide film 62 are formed on a semiconductor substrate 61, and a polycrystalline silicon layer 64, which becomes a gate electrode, is formed on top of the gate insulating layer 63 and a field oxide film 62, the end of which forms an impurity region 62.
8. Form it so that it is on top. Then, the glabellar insulation N66, which is formed to have a substantially flat surface, is opened so as to be exposed above the end portion and the impurity region 68, and the opening 6
[Problem to be Solved by the Invention] Polycrystalline silicon N65 is buried in the inside of the polycrystalline silicon N65, and the electrical connection of the shared contact part is established by polycrystalline silicon N65. With the technique of embedding with the crystalline silicon layer 65, electrical connections can be made without depending on pattern rules, and the cell size can be reduced.

However, the normal shared contact structure (second
Compared to the case of adopting the method shown in FIG.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a wiring forming method that simplifies the manufacturing process.

[Means for solving problems]

The present invention includes a step of selectively forming a first wiring layer on a first insulating layer formed on a semiconductor substrate, and a step of forming a second insulating layer having a substantially flat surface on the first insulating layer and the first insulating layer. forming a first opening on the first wiring layer, forming a first opening in the first and second insulating layers including an end of the first wiring layer, and forming a first opening on the first wiring layer; forming a second opening exposing a region to be connected to the first and second openings;
a step of selectively vapor phase growing a semiconductor layer in each of the openings, and a step of forming a second wiring layer on the semiconductor layer formed in each of the first and second openings;
The above-mentioned problems are solved by a wiring forming method characterized by comprising a step of forming the third wiring layer on the second wiring layer.

[Effect]

In a semiconductor device 1 such as a memory device, not only a so-called shared contact but also a buried contact that connects an upper wiring layer directly to the semiconductor substrate may be used.
The wiring forming method of the present invention realizes process simplification by performing these steps in a common process.

That is, a first opening is formed in the first and second insulating layers including the ends of the first wiring layer, and at the same time, a third wiring layer for making a buried contact is formed. By forming a second opening that exposes a region to be connected and simultaneously selectively vapor-growing a semiconductor layer in both the first and second openings, for example, a semiconductor layer can be formed only in the first opening. The process is simplified compared to the case where the second opening is filled with a semiconductor layer and then a semiconductor layer is filled only into the second opening.

Further, by forming a second insulating layer having a substantially flat surface on the first wiring layer, the first wiring layer is coated sufficiently thickly. Therefore, the wiring layer can be patterned on the second insulating layer without considering the effect on the first wiring layer, and the first wiring layer can be oxidized to cover only the necessary parts. Compared to the method of removing the oxide film, the process is simplified.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

The wiring forming method of this example is a wiring forming method for a static RAM having a high resistance load type memory cell, and it realizes a simplified process and further reduces the cell size and improves the aspect ratio of the aluminum wiring layer. Improvements can also be made at the same time.

(a) First, semiconductor substrates 1a and lb, which are P-type silicon substrates, for example, are shown separately from the same wafer.

A field oxide film 2 and a gate oxide film 3 constituting a first insulating layer are formed on the surface of 1c. Next, a 1Nth polycrystalline silicon layer 4, which will become a first wiring layer, is formed on these semiconductor substrates 1a, lb, and lc. This first polycrystalline silicon layer 4 is used, for example, as a gate electrode of a transistor. This first polycrystalline silicon layer 4 is patterned and left only on the semiconductor substrates 1a and Ib. As shown in FIG. 1a, each impurity region 5a, 5b, 5c is formed in each semiconductor substrate 1a.

The entire surface of the substrate is covered with a thick interlayer insulating layer 6, which is a second insulating layer and is formed facing the surfaces of lb and lc and has a substantially flat surface as shown in FIG. 1a. The glabellar insulating layer 6 whose surface is approximately flat is made of, for example, a silicon oxide film of about 3
It can be obtained by depositing the film to a thickness of approximately 0.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300000000 film-based materials with the entire surface by etching back the entire surface.

(bl) Next, as shown in FIG.
．． First openings 7a and 7b are formed in 6, and a second opening 8 is formed on the semiconductor substrate IC so as to expose impurity region 5C, which is a region to which the third wiring layer is connected.

The openings 7a, 7b, and 8 can be formed by selectively forming a resist layer on the substantially flat interlayer insulating layer 6 and using this as a mask, for example, by the RIB method. Each such opening 7
a, 7b, and 8, in the first opening 7a,
The end portion 4 of the first polycrystalline silicon layer 4 is located inside the polycrystalline silicon layer 4.
d and the impurity region 5a are exposed, and the end portion 4d of the polycrystalline silicon layer 4 and the impurity region 5b are exposed in the first opening 7b. Further, inside the second opening 8, the impurity region 5c is exposed. In this way, by simultaneously forming the openings 7a, 7b, and 8 in the portion where the buried contact is to be made as well as the shared contact portion, the process is simplified.

(C) Next, as shown in FIG. 1C, the first opening ? A semiconductor layer is selectively grown in vapor phase in each of the openings a, 7b and the second opening 8. In this embodiment, the semiconductor layer is a polycrystalline silicon layer (DOPO3) 9. The polycrystalline silicon layer 9 is deposited to have a thickness of about 5,000, for example, and is coated with a resist and left only in each of the openings 7a, 7b, and 8 by etching back. Moreover, instead of leaving the polycrystalline silicon layer 9 by etching back, the openings 7a and 7b are formed as a semiconductor layer by selective CVD or selective epitaxial growth.

A semiconductor layer can also be formed within 8.

Formation of such polycrystalline silicon N9 also involves openings 7a,
Similar to the formation of 7b and 8, this is performed not only for the portion where the shared contact is to be made but also the portion where the buried contact is to be made at the same time.

(d) Next, as shown in FIG. 1d, a high resistance wiring [10] as a second wiring layer is formed on the entire surface.

This high resistance wiring JILO is used for static RAM, for example.
This layer functions as a load resistance for memory cells. Its RPI thickness is 500 and is made of, for example, a polycrystalline silicon layer. This high resistance wiring layer 10 includes each of the openings 7a,
Polycrystalline silicon layer 9 formed in 7b, 8 and each opening 7
Connect at a, 7b, and 8, respectively.

(e) Next, as shown in FIG. 1e, the high resistance wiring layer IO is selectively removed. On the semiconductor substrate la, the high resistance wiring 110 is made of polycrystalline silicon N in the opening 7a.
9 remains connected. On the semiconductor substrate lb,
The high resistance wiring layer 10 is a polycrystalline silicon layer 9 within the opening 7b.
removed so that it is considered non-contact. At this time, the first polycrystalline silicon layer 4, which is the first FFA layer, is sufficiently covered with the thick eyebrow insulating layer 6, and there is no surface oxidation of the first polycrystalline silicon M4. There is no need to pattern the oxide film, that is, there is no problem even if the surface of the polycrystalline silicon layer 9 within the opening 7b of the tube 2 is removed to some extent. On the semiconductor substrate IC, the high-resistance wiring layer 10 is not removed, but remains in a pattern wider than the opening diameter of the opening 8. Therefore, mask alignment can be easily performed in the next step.

The selective removal of these high-resistance wiring layers IO is performed on the thick interlayer insulating layer 6 having a substantially flat surface, which is particularly advantageous for miniaturization.

(f) After selectively forming the high resistance wiring layer 10 in this way, the silicon nitride film 11 is formed to cover the high resistance wiring layer 10. This silicon nitride film 11
An interlayer insulating layer 12 such as BPSG or Ag2O layer is formed thereon. Next, as shown in FIG.
An opening 14 is formed in the opening 1 . The opening 14 can be formed in the high-resistance wiring layer IO having a pattern wider than the opening diameter of the opening 8, which facilitates the opening work. After reflowing the opening 14, an aluminum wiring AN 13 as a third wiring layer is formed in the opening 14. This aluminum wiring layer 13 is the same as the high resistance wiring layer 10.
．． It is electrically connected to the impurity region 5c of the semiconductor substrate 1c via the polycrystalline silicon layer 9. Note that the aluminum wiring layer 13 can be formed by sputtering, and since the step difference is greatly reduced by the polycrystalline silicon layer 9 during connection, a reliable electrical connection can be made.

The wiring forming method of this example, which consists of the steps described above, is as follows:
Portions where shared contact is made (semiconductor substrates 1a, l)
The area where the buried contact is made parallel to the region b) (
Openings 7a, 7b, and 8 and a polycrystalline silicon layer 9 are also formed in the semiconductor substrate IC region). Therefore, the process can be significantly simplified compared to a method in which interconnections are formed while individually embedding a polycrystalline silicon layer. In addition, the portion where shared contact is to be made is also connected to the high resistance wiring layer 10.

Non-connection can be selected by selectively removing the high-resistance wiring layer 10, and at this time, the first polycrystalline silicon layer 4
Since there is no need to perform surface oxidation or patterning of the oxide film, one mask is frozen, and the process can be performed easily and reliably.

Further, the high resistance wiring layer 10 also functions as a connection layer in a portion where a buried contact is to be made, making it easy to form the opening 14 and realizing reliable electrical connection.

Further, in the wiring forming method of this embodiment, the interlayer insulating layer 6 which is a substantially flat second insulation layer is formed, and the aluminum wiring layer 13 and the high resistance wiring W! Improves J10 coverage.

In addition, in the above-mentioned embodiment, the material for filling the openings 7a, 7b, and 8 was described as the polycrystalline silicon layer 9.
Including, but not limited to, silicide.

Alternatively, a structure in which a polycrystalline silicon layer is added to silicide may be used. Also, the impurity region is P type.

Type N does not matter. Further, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] In the wiring forming method of the present invention, both the first opening and the second opening are formed, and at the same time, a semiconductor layer is formed by selective vapor growth. Therefore, the process can be simplified accordingly.

Further, a second insulating layer having a substantially flat surface is formed, and the first
Since the first wiring layer is coated sufficiently thickly, it is possible to save the trouble of oxidizing and re-patterning the first wiring layer.
The process will be simplified.

[Brief explanation of the drawing]

1a to 1f are process cross-sectional views of an example of the wiring forming method of the present invention, FIG. 2 is a cross-sectional view of a shared contact portion according to a conventional wiring forming method, and FIG. 3 is a cross-sectional view of another conventional wiring forming method. FIG. 3 is a cross-sectional view of a shared contact portion according to the wiring forming method of FIG. 1a to IC...Semiconductor substrate 2...Field oxide film 3...Gate oxide film 4...First layer polycrystalline silicon layer 4a...End portions 5a to 5C...Impurity region 6 ...Interlayer insulating layers 7a, 7b...First opening 8...Second opening 9...Polycrystalline silicon N (semiconductor layer) 10...High resistance wiring layer 12... Interlayer insulating layer 13...aluminum wiring layer Fig. 1a Fig. 1C Fig. 2 Fig. 3

Claims (1)

[Claims] A step of selectively forming a first wiring layer on a first insulating layer formed on a semiconductor substrate, and a second insulating layer having a substantially flat surface formed on the first insulating layer. forming a first opening in the first and second insulating layers including an end of the first wiring layer; forming a second opening that exposes a region to which the wiring layer is to be connected; selectively growing a semiconductor layer in the first and second openings by vapor phase growth; forming a second wiring layer on the semiconductor layer formed in each opening; and forming a third wiring layer on the second wiring layer. Wiring formation method.