JPH0451528A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To make the area of the diffused layer small for reducing the parasitic capacity of a semiconductor device by making the end of the gate electrode side and the end of the other side in the diffused layer constituting the source and the drain symmetric to each other with respect to the center of the gate electrode. CONSTITUTION:First, an interelement separate oxide film 34 is prepared in the direction perpendicular to the main gate electrode, and after preparing a gate electrode 36 the 2nd interelement separate oxide film 52 is selectively oxidated in the direction parallel to the gate electrode masking the gate electrode 36 and its side wall and is formed in self-conformity with the gate electrode. A polycrystal silicon 43 that is in contact with the diffused layer 38 deposits a flat heat resistive organic insulating film 41 once, and after opening a contact holes the film 41 is bonded to the inner wall of the contact holes. Further, after a diffused layer 38 is prepared and the space inside the contact holes is filled with metal such as tungsten, the etchback method that etches the heat resistive organic insulating film slightly below the surface thereof is used to separate each contact hole.

Description

[Detailed description of the invention] [Usage field on M beam]

The present invention relates to a semiconductor device having a fine insulated gate field effect transistor and a method for manufacturing the same.

[Conventional technology]

For devices with an MO8 structure, challenges in achieving high integration and high speed ratio include miniaturization and reduction in the area of the diffusion layer. Assuming that the power supply voltage becomes (1/K) with device miniaturization, on the proportional reduction side where the electric field is constant, the area of the diffusion layer becomes (1/K"), and the depletion layer width increases as the substrate concentration increases. However, since the diffusion layer capacitance also becomes (1/K), the capacitance decreases and improves device characteristics.In other words, MO8 by gate self-line process
In a type field effect transistor, one transistor can be formed by crossing the active region with the minimum line width with the gate electrode, which also has the minimum line width, and this transistor with the minimum area can be reduced proportionally. . However, in reality, it is difficult to reduce the area of the diffusion layer according to rules because various process margins must be considered in the design. In addition, examples related to this type of device include:
Devices Electronics for Integrated Circuits Second Edition (John
Wiley Publishing, 1986) JJ444 A+449 pages (D
electronics for int
-egrated C1rcuits 2nd edi
tion, John Viley & 5ons, In
c, 1986).

[Problem to be solved by the invention]

FIG. 2 is a cross-sectional view and a plan layout of a basic MO8 field effect transistor. A basic MO8 type field effect transistor is explained based on FIG. 2. An element isolation oxide film 34 is formed by selective oxidation, and a gate electrode 36 is formed in accordance with the defined active region. death. Using the gate electrode as a mask, a diffusion layer 38 that will become a source and a drain is formed in the active region by ion implantation, and then an insulating film is deposited. It is made by opening a contact hole 65 in this diffusion layer and gate electrode and forming wiring. In the figure, 47 is a wiring layer, and 62 is a mask layer for growing the element isolation oxide film 34. Considering the above basic process, the reason for increasing the diffusion layer area is (1) ensuring a margin for misalignment when overlapping the active region and gate electrode, and (2) making contact holes to the open diffusion layer. When matching the
These are two factors: securing a margin for misalignment between the contact hole and the gate electrode. In order to improve device characteristics by reducing the size of the diffusion layer region and reducing parasitic capacitance, a process and device structure that eliminates the need for these two alignment margins is required. Furthermore, in the conventional example described above, since the gate electrode is formed in alignment with the active region, the diffusion layers constituting the source and drain are not necessarily formed in symmetrical positions with respect to the gate electrode. An object of the present invention is to provide a semiconductor device having an insulated gate field effect transistor with a smaller diffusion layer region and reduced parasitic capacitance, and a method for manufacturing the same.

[Means to solve the problem]

The above purpose is to (1) provide a diffusion layer that is provided in a semiconductor substrate of a first conductivity type and constitutes a source and drain of a second conductivity type that is different in conductivity type from the substrate; and a diffusion layer that is electrically connected to the diffusion layer; A semiconductor comprising an insulated gate field effect transistor having a conductive wiring layer and a gate electrode arranged with an insulating film interposed between the substrate and the gate electrode controlling a current flowing between the diffusion layers. A semiconductor device, wherein an end of the diffusion layer constituting the source and drain on the side of the gate electrode and an end on the opposite side thereof are each symmetrical with respect to the center of the gate electrode, (2) Above 1
In the semiconductor device described above, an inter-element isolation insulating film provided for electrically isolating the insulated gate field effect transistor from other elements comprises a plurality of regions having different thicknesses. , (3) a diffusion layer that is provided in a semiconductor substrate of a first conductivity type and constitutes a source and drain of a second conductivity type that is different in conductivity type from the substrate, and a conductive layer that is electrically connected to the diffusion layer. with the wiring layer. The substrate has a gate electrode disposed through an insulating film, and the gate electrode controls the current flowing between the diffusion layers. In a semiconductor device having an element isolation insulating film provided for electrical isolation from elements, the diffusion layer and the wiring layer are electrically connected via a conductive connection layer, and the connection layer is A semiconductor device, characterized in that the device is disposed extending over a part of the inter-element isolation insulating film and a part of the gate electrode, (4) provided in a semiconductor substrate of a first conductivity type, the substrate A diffusion layer constituting a source and drain of a second conductivity type different from the first conductivity type, a conductive wiring layer electrically connected to the diffusion layer, and a conductive wiring layer arranged with the substrate through an insulating film. an insulated gate field effect transistor having a gate electrode and controlling a current flowing between the diffusion layers by the gate electrode; and an element provided for electrically isolating the insulated gate field effect transistor from other elements. In a semiconductor device having an isolation insulating film, an end of the element isolation insulating film facing the side surface of the gate electrode and an end of the diffusion layer on the side of the gate electrode are each defined by the gate electrode. (5) a semiconductor device characterized by being placed in the position 3 or 4 above;
In the semiconductor device described above, the element isolation insulating film includes:
A semiconductor device characterized by comprising a plurality of regions having different thicknesses, (6) Step 1 of growing an inter-element isolation insulating film for electrically isolating each element on the surface of a first conductivity type semiconductor substrate. , step 2 of growing a gate insulating film of an insulated gate field effect transistor, a conductor layer to be a gate electrode and at least one first layer 4! ! Step 3: Depositing edge films and processing them into the desired gate electrode shape. A second insulating film is deposited on the entire surface of the substrate, and a second I! film is formed on the sidewalls of the gate electrode by anisotropic dry etching. Step 4 of leaving the edge film; Step 5 of growing a second element isolation insulating film using the second insulating film as a mask; Step 6 of removing the second insulating film, using at least the second element isolation insulating film and the gate electrode as a mask, ion implantation of impurities of a second conductivity type different from that of the substrate is performed to form a diffusion layer. 7. Depositing a third insulating film and leaving the third insulating film on the sidewalls of the gate electrode by anisotropic dry etching 8. Manufacture of a semiconductor device characterized in that a second conductivity type impurity is further introduced into the diffusion layer using at least the third insulating film and the second element isolation insulating film as a mask to form a source and a drain. (7) In the method for manufacturing a semiconductor device as described in 6 above, the method for introducing @2 conductivity type impurities includes introducing impurities from a semiconductor layer containing second conductivity type impurities formed on the diffusion layer. A method for manufacturing a semiconductor device, characterized in that it is carried out by diffusion, (8) step 1 of growing an inter-element isolation insulating film for electrically isolating each element on the surface of a first conductivity type semiconductor substrate; Step 2 of growing a gate insulating film of a gate type field effect transistor. A conductor layer serving as a gate electrode and at least one first layer #! Deposit the lamina,
Step 3 of processing them into a desired gate electrode shape; Step 4 of depositing a second insulating film on the entire surface of the substrate and leaving the second insulating film on the side walls of the gate electrode by anisotropic dry etching;
The second lI! Step 5: growing a second element isolation insulating film using the edge film as a mask. Step 6 of removing the second insulating film, using at least the second element isolation insulating film and the gate electrode as a mask, ion implantation of impurities of a second conductivity type different from that of the substrate is performed to form a diffusion layer. Step 7.
A third insulating film is deposited and a third #! film is deposited on the sidewalls of the gate electrode by anisotropic dry etching. Step 8 of leaving the edge film; Step 9 of depositing a heat-resistant organic insulating film; Step 10 of opening a contact hole in the heat-resistant organic insulating film. step 11 of depositing a second conductivity type semiconductor layer at least within the contact hole; step 12 of depositing a conductive material on the semiconductor layer; Step 13 of leaving the conductive material in the contact hole and removing other conductive materials by anisotropic dry etching; Step 14 of leaving the semiconductor layer in the contact hole and removing other semiconductor layers by anisotropic dry etching. , a step 15 of removing the heat-resistant organic insulating film, a step 16 of depositing a fourth insulating film, a step 17 of etching back the fourth insulating film to expose the surface of the conductive material, and a step 17 of exposing the surface of the conductive material. This is achieved by a method for manufacturing a semiconductor device characterized by comprising a step 18 of forming a connecting wiring layer. FIG. 1 shows the structure of an example of an insulated gate field effect transistor of the present invention. Here, with respect to the two factors that increase the area of the diffusion layer, we have developed a structure in which the connection layer 46' that connects to the wiring layer contacts the small diffusion layer in a self-aligned manner, and a structure in which the interconnection layer 46' contacts the small diffusion layer in a self-aligned manner. This was achieved through a self-aligned process of two-stage oxidation. These characteristics are summarized below along with the device formation process. The element isolation insulating film that isolates the active region is not formed all at once, but first the element isolation oxide film 34 is formed mainly in the direction perpendicular to the gate electrode, and then after the gate electrode 36 is formed, Using the gate electrode 36 and its sidewalls (not shown) as a mask, selective oxidation is performed in a direction parallel to the gate electrode, thereby forming the second element isolation oxide film 52 in a self-aligned manner with the gate electrode. This provides the smallest active area. In order to form a contact hole without leaving any alignment margin for the diffusion layer created in this small active area,
The polycrystalline silicon 43 in contact with the diffusion layer 38 is not formed immediately after the formation of the gate electrode, but rather by first depositing a flat heat-resistant organic insulating film 41 (see FIG. 3d) and then forming a polycrystalline silicon layer 43 to expose the diffusion layer. After opening the contact hole, it is applied to the inner wall of the contact hole. When deposited, this polycrystalline silicon is connected at the surface of the heat-resistant organic insulating film, which is an interlayer film, but after the space in the contact hole is filled with a metal such as tungsten. By applying an etch-back method that slightly digs down from the surface of the heat-resistant organic insulating film, each contact hole is separated by self-alignment. In this structure, after filling the gate electrode 36 with a heat-resistant organic insulating film, a contact hole larger in size than the area of the diffusion layer must be opened. Furthermore, in a fine transistor, this contact hole naturally overlaps the gate electrode 36 and the element isolation oxide film 34,52. Therefore, when opening the contact hole, the element isolation oxide film 34 and the inter-element isolation oxide film 34 are removed. It is necessary to prevent the oxide film 37, 39 covering the gate electrode from being scraped, but as used in this method, the heat-resistant organic insulating film can be processed using oxygen plasma, and the oxide film can be processed using oxygen plasma. Because of its extremely high resistance, contact hole openings in the heat-resistant organic insulating film can be formed freely even on stepped portions without cutting away the underlying layer.

[Effect]

The semiconductor device of the present invention eliminates an unnecessary portion of the transistor diffusion layer that is provided in a conventional semiconductor device due to processing constraints, although it is a load on the operation of the device. In other words, the formation of the element isolation oxide film is self-aligned with the gate electrode, eliminating the need for processing margins in the process.Furthermore, since the contact hole is opened using an organic film, the patterning of the contact hole is Because it can be done without cutting at all,
The process margin here becomes unnecessary. Therefore, it is not necessary for both the gate electrode and the contact hole to the wiring layer, which determine the size of the diffusion layer, to have a margin, and the minimum area of the diffusion layer can be realized.

【Example】

Example 1 An example of the present invention will be described in detail using FIGS. 3(a) to 3(g). As shown in FIG. 3(a), a well region in which an N-type MOS transistor and a P-type MOS transistor are to be formed is formed in a single crystal semiconductor substrate by known ion implantation and heat treatment methods. Here, an explanation will be given using an N type M-, OS as an example. The board 31 is. The P-type well 32, which is a P-type silicon substrate containing boron and has a resistivity of about 10 Ω·min, and in which an N-type MOS transistor is formed, contains boron at a concentration of about 1015/cn3. Further, as shown in the figure, the element isolation oxide film 34 is grown to a thickness of about 400 nm by a known thermal oxidation method. In order to eliminate the leakage current path formed under this oxide film, boron was introduced as an impurity before the growth of the oxide film, but it may be introduced after the growth of the oxide film. Next, a gate oxide film 35 with a thickness of about 10 nm is grown by thermal oxidation, and then formed on the gate electrode 36 and its upper layer. An oxide film 37 and a nitride film 33 are deposited by CVD. Here, the gate electrode 36 is made of polycrystalline silicon containing a high concentration of P with a thickness of about 1100 nm, but this is made of polycide, which is a laminated film of polycrystalline silicon and silicide, or tungsten, etc. It doesn't matter if it's metal. Furthermore, it goes without saying that the conductivity types of the gate electrodes may be different between the N-type MOS transistor and the P-type MoS transistor, and the thickness of the oxide film 37 covering the gate electrode is approximately 150 nm. The thickness of the nitride film 33 is approximately 150 nm. One of the features of the present invention is that contact holes are formed by a self-alignment process. Since the contact hole on the gate electrode is also formed at the same time as the diffusion layer, before depositing this nitride film 33, the oxide film 37 in the area where the contact hole is to be formed on the gate electrode is removed using a resist method. This patterning can be performed on the element isolation oxide film, and therefore does not affect the layout of the diffusion layer. The gate electrode 36, together with the oxide film 37 and nitride film 33 thereon, is patterned as shown in the figure. Next, as shown in Figure 3(b), approximately 5
A nm oxide film (not shown) is formed on the side surface of the gate electrode,
After depositing the nitride film 51 to a thickness of 200 nm using the CVD method, anisotropic etching is performed to selectively deposit the nitride film 51 only on the side surfaces of the gate electrode.
Leave 1. Next, as shown in FIG. 3(C), the nitride film 33.51
A second element isolation oxide film 52 having a thickness of 200 nm is formed by thermal oxidation using the mask as a mask, and then the nitride film 33.51 is removed by wet etching using hot phosphoric acid. Using the element isolation oxide film and this gate electrode as a mask, N
As, which is an impurity in the mold, is introduced by ion implantation. The amount of ion implantation is approximately 1013/c''. Next, as shown in FIG. 3(d), an oxide film 39 is deposited over the entire wafer using a method that provides good step coverage, and then When anisotropic dry etching is performed using the dry etching method, an oxide film remains only on the side walls of the gate electrode 36, and the gate electrode is insulated.The thickness of the oxide film deposited here is 60 nm. , the gate length becomes finer,
In transistors where lateral diffusion of impurities cannot be ignored,
After forming this sidewall oxide film 39, it is also possible to ion-implant impurities exceeding 10"/(m") to offset the lateral diffusion with the sidewall oxide film. In this case, the above-mentioned 1013/cn" In addition, in general integrated circuits, devices with different dimensions coexist, and the dimensions also differ depending on the application, so it is not necessarily necessary to implant impurities as shown in this example. Not only fine devices are used. Therefore, for devices with large dimensions, it is necessary to complete the formation of the diffusion layer in this step. However, regarding contact formation, regardless of the dimensions of the device, please refer to the book described later. The process of the invention is used. Furthermore, by applying PIQ (polyimide isoindoquinazolinedione) and forming a heat-resistant organic insulating film 41 with a thickness of about 500 nm, the surface becomes almost flat. Next, as shown in FIG. 3(e). As shown in FIG. 2, an oxide-based coating film (not shown) is formed on the heat-resistant organic insulating film 41, and
Furthermore, photoresist is applied to form a resist pattern (not shown) for contact holes. This itinerary diagram is omitted. This method is the same as the multilayer resist method in which PIQ is used for the bottom layer film. To open a contact hole in the heat-resistant organic insulating film 41, a resist pattern is transferred to a base oxide coating film, and using this as a mask, the heat-resistant organic insulating film 41 is processed by oxygen plasma. Since the underlying oxide film and silicon are not scraped at all by oxygen plasma, the problem of base scraping that occurs when forming conventional contact holes can be avoided. After etching the remaining oxide film and cleaning the exposed diffusion layer surface with a diluted fluoro-nitric acid solution to remove the damaged layer caused by dry etching, polycrystalline silicon 43 is removed using a known CVD method.
Deposit to a thickness of 0 nm. The film thickness is determined by the contact hole diameter (
In this embodiment, the thickness is 0.25 μm), and is at least thick enough to not fill the contact hole. Furthermore, although not shown in the figure, using a resist mask, As is an impurity having the same conductivity type as each diffusion layer.
Introduced using ion implantation method. This diffuses the impurity and forms a diffusion layer 38. After removing the resist mask and cleaning the surface, tungsten 46 is deposited on the entire surface and also embedded in the contact hole. Next, as shown in FIG. 3(f), the tungsten 46 is etched back until the surface of the polycrystalline silicon 43 is exposed, leaving the tungsten packed inside the contact hole as a connection layer 46'. Furthermore, the polycrystalline silicon 43 is etched back to expose the surface of the heat-resistant organic insulating film 41, and the polycrystalline silicon in contact with the diffusion layer is separated and separated into contact holes. After that, the heat-resistant organic insulating film 41 is removed by an asher. Next, as shown in FIG. 3(g), an oxide film (not shown) with good shape coverage is deposited to a thickness of 50 nm as a base layer, and then BPSG (borophosphorus glass) 5 is deposited as an oxide film between the eyebrows.
4 is deposited and heat treated. This heat treatment makes the surface almost flat. At this time, the oxide film can prevent impurities from entering the polycrystalline silicon from the BPSG. The tungsten surface of the connection layer 46' is exposed by planarization by heat treatment and etching back. Thereafter, tungsten 55, which will become a wiring layer, is deposited over the entire surface and patterned to form the wiring layer 47 shown in FIG. After this, the wiring process is repeated as necessary, but is omitted here. In this manner, the transistor shown in FIG. 1 was manufactured. FIG. 4 shows the planar pattern of the transistor of the present invention up to five contact layers. Here, 62 is a mask layer for growing an element isolation oxide film, and 36 is
The gate electrode, 65 is a contact hole, and 66 is a mask for removing the oxide film to open the contact hole on the gate electrode. In the present invention, an oxide film removal process must be performed in order to form a contact hole to the gate electrode. However, since this process is performed in a semi-self-aligned manner, the mask required for this process can be larger than the actual contact hole, as shown in Figure 4. There is no problem with the process.

【Effect of the invention】

According to the present invention, even in a minute device with a gate electrode length of less than 0.3 μm, a high-performance device with a small diffusion layer capacitance can be realized by a self-alignment process. Another major feature is that unlike conventional transistors, a heat-resistant organic film is used to form the polycrystalline silicon in contact with the diffusion layer, so there is no need to worry about scratching the base during etching. Furthermore, since the impurity diffusion method from polycrystalline silicon can be used,1 compared to the normal ion implantation method,
We were able to make the diffusion layer thinner.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an insulated gate field effect transistor according to an embodiment of the present invention, FIG. 2 is a sectional view and plan layout diagram of a conventional insulated gate field effect transistor, and 3rd FIG. 4 is a process flow diagram showing the manufacturing process of the transistor of the present invention shown in the figure, and FIG. 4 is a plan layout diagram thereof. 31...Substrate 32...P-type well 33
．． 51...Nitride film 34...Element isolation oxide film 35...Gate oxide film 36...Gate electrode 37
．． 39... Oxide film 38... Diffusion layer 41... Heat-resistant organic insulating film 43... Polycrystalline silicon 46.55... Tungsten 46'... Connection layer 47... Wiring layer 52・・・
・Second element isolation oxide film 54...BPSG 62...Mask layer 65
・・・Contact hole

Claims (1)

[Claims] 1. A diffusion layer provided in a semiconductor substrate of a first conductivity type and constituting a source and a drain of a second conductivity type different from the conductivity type of the substrate, and electrically connected to the diffusion layer. an insulated gate field effect transistor, which has a conductive wiring layer formed on the substrate, and a gate electrode arranged with an insulating film interposed between the substrate and the gate electrode to control a current flowing between the diffusion layers. A semiconductor device, wherein an end of the diffusion layer constituting the source and the drain on the side of the gate electrode and an end on the opposite side thereof are each symmetrical with respect to the center of the gate electrode. . 2. In the semiconductor device according to claim 1, the inter-element isolation insulating film provided to electrically isolate the insulated gate field effect transistor from other elements comprises a plurality of regions having different thicknesses. Characteristic semiconductor devices. 3. A diffusion layer that is provided in a semiconductor substrate of a first conductivity type and constitutes a source and drain of a second conductivity type that is different in conductivity type from the substrate, and conductive wiring electrically connected to the diffusion layer. an insulated gate field effect transistor having a gate electrode disposed between the layer and the substrate through an insulating film, the gate electrode controlling a current flowing between the diffusion layers; and the insulated gate field effect transistor. In a semiconductor device having an inter-element isolation insulating film provided for electrically isolating an element from other elements, the diffusion layer and the wiring layer are electrically connected via a conductive connection layer, and the connection layer 1. A semiconductor device, wherein the semiconductor device is arranged to extend over a part of the element isolation insulating film and a part of the gate electrode. 4. A diffusion layer that is provided in a semiconductor substrate of a first conductivity type and constitutes a source and drain of a second conductivity type that is different in conductivity type from the substrate, and conductive wiring electrically connected to the diffusion layer. an insulated gate field effect transistor having a gate electrode disposed between the layer and the substrate through an insulating film, the gate electrode controlling a current flowing between the diffusion layers; and the insulated gate field effect transistor. In a semiconductor device having an element isolation insulating film provided for electrically isolating the element from other elements, an end of the element isolation insulating film opposite to a side surface of the gate electrode, and an end of the diffusion layer facing the gate electrode. A semiconductor device characterized in that the ends of the gate electrodes are located at positions defined by the gate electrodes. 5. The semiconductor device according to claim 3 or 4, wherein the element isolation insulating film comprises a plurality of regions having different thicknesses. 6. Step 1 of growing an inter-element isolation insulating film for electrically isolating each element on the surface of the first conductivity type semiconductor substrate;
Step 2 of growing a gate insulating film of an insulated gate field effect transistor; Step 3 of depositing a conductor layer that will become a gate electrode and at least one layer of the first insulating film; and processing them into a desired gate electrode shape; Step 3: a substrate; Step 4: depositing a second insulating film on the entire surface and leaving the second insulating film on the sidewalls of the gate electrode by anisotropic dry etching; using the second insulating film as a mask, forming a second element isolation insulating film; Step 5 of growing the second insulating film; Step 6 of removing the second insulating film; using at least the second element isolation insulating film and the gate electrode as a mask, impurities of a second conductivity type different from that of the substrate are ionized; step 7 of implanting to form a diffusion layer; step 8 of depositing a third insulating film and leaving the third insulating film on the sidewalls of the gate electrode by anisotropic dry etching; 2. A method of manufacturing a semiconductor device, comprising further introducing impurities of a second conductivity type into the diffusion layer using the second inter-element isolation insulating film as a mask to form a source and a drain. 7. In the method of manufacturing a semiconductor device according to claim 6, the method for introducing the second conductivity type impurity is by diffusion from a semiconductor layer containing the second conductivity type impurity formed on the diffusion layer. 1. A method of manufacturing a semiconductor device, characterized in that: 8. Step 1 of growing an inter-element isolation insulating film for electrically isolating each element on the surface of the first conductivity type semiconductor substrate;
Step 2 of growing a gate insulating film of an insulated gate field effect transistor; Step 3 of depositing a conductor layer that will become a gate electrode and at least one layer of the first insulating film; and processing them into a desired gate electrode shape; Step 3: a substrate; Step 4: depositing a second insulating film on the entire surface and leaving the second insulating film on the sidewalls of the gate electrode by anisotropic dry etching; using the second insulating film as a mask, forming a second element isolation insulating film; Step 5 of growing the second insulating film; Step 6 of removing the second insulating film; using at least the second element isolation insulating film and the gate electrode as a mask, impurities of a second conductivity type different from that of the substrate are ionized; Step 7 of implanting to form a diffusion layer, depositing a third insulating film, and leaving the third insulating film on the sidewalls of the gate electrode by anisotropic dry etching Step 8, depositing a heat-resistant organic insulating film Step 9, Step 10 of opening a contact hole in the heat-resistant organic insulating film, Step 11 of depositing a second conductivity type semiconductor layer at least in the contact hole, Step 12 of depositing a conductive material on the semiconductor layer, Step 13 of leaving the conductive material in the contact hole and removing other conductive materials by anisotropic dry etching; Step 14 of leaving the semiconductor layer in the contact hole and removing other semiconductor layers by anisotropic dry etching; Step 15 of removing the heat-resistant organic insulating film, Step 16 of depositing a fourth insulating film, Step 17 of etching back the fourth insulating film to expose the surface of the conductive material, and connecting with the conductive material. 1. A method for manufacturing a semiconductor device, comprising a step 18 of forming a wiring layer.