JP3129703B2 - Semiconductor device having MOS transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a metal-oxide-semiconductor (MOS) type field effect transistor (hereinafter, referred to as a MOS transistor).
And a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, in a manufacturing process of a semiconductor device having a MOS transistor, plasma etching,
Plasma ashing, Plasma CVD (Chemical Vap
or a process using plasma (hereinafter, referred to as a plasma process) such as chemical vapor deposition or chemical vapor deposition. In particular, a plasma process is indispensable for miniaturization and high integration of a semiconductor device. On the other hand, when the plasma process is used, a phenomenon occurs in which the characteristics of the MOS transistor are deteriorated or the element itself is destroyed due to the influence of charged particles in the plasma. Therefore, there is a problem that the reliability and the yield of the semiconductor device are reduced. The effect of a plasma process on a MOS transistor in a conventional semiconductor device will be described below.

FIG. 8 shows an example of a conventional semiconductor device.

The conventional semiconductor device shown in FIG. 8 has a semiconductor substrate 101 made of silicon. Semiconductor substrate 101
A field insulating layer 102 made of silicon oxide is formed in a surface region of the device, and an element forming region (not shown) separated by the field insulating layer 102 is formed. A gate insulating film 103 made of silicon oxide is selectively formed on the element formation region. A gate electrode 104 made of polycrystalline silicon is selectively formed on the gate insulating film 103, and both ends of the gate electrode 104 extend on the field insulating layer 102. A pair of source / drain regions (not shown) are formed in the element formation region so as to sandwich a region immediately below the gate electrode 104. A MOS transistor is formed on the semiconductor substrate 101 by the source / drain regions and the gate electrode 104.

On the field insulating layer 102, a first interlayer insulating layer 105 made of silicon oxide is formed. The first interlayer insulating layer 105 covers the source / drain region and the gate electrode 104. First interlayer insulating layer 1
05, a through hole 106 reaching the surface of the gate electrode 104;
Are formed. The inside of the through hole 106 is filled with a conductor plug 107 made of tungsten. The bottom of the conductor plug 107 contacts the top of the gate electrode 104 so that the conductor plug 107
04 is electrically connected.

On the first interlayer insulating layer 105, a wiring layer 108 made of a patterned aluminum layer is formed. The bottom of this wiring layer 108 is
7 is in contact with the top. Thereby, the wiring layer 108
Is electrically connected to the conductor plug 107,
It is electrically connected to gate electrode 104 via conductor plug 107. On the first interlayer insulating layer 105, a second interlayer insulating layer 109 is formed so as to cover the first wiring layer.

[0008] The conventional semiconductor device of FIG. 8 having the above configuration is manufactured as follows.

First, a field insulating layer 102 is selectively formed on a surface region of a semiconductor substrate 101. Semiconductor substrate 1
In the surface region 01, element formation regions separated by the field insulating layer 102 are defined. Next, after a silicon oxide film is formed over the element formation region of the semiconductor substrate 101, a polycrystalline silicon layer is deposited over the entire semiconductor substrate 101. After a patterned photoresist is formed on the polycrystalline silicon layer, etching is performed using the patterned photoresist as a mask to selectively and simultaneously remove the silicon oxide film and the polycrystalline silicon layer. Thus, the gate insulating film 103 and the gate electrode 104 are formed. Further, phosphorus is ion-implanted into the element formation region using the field insulating layer 102 and the gate electrode 104 as a mask, so that a pair of
Forming a drain region;

Next, a first interlayer insulating layer 105 is formed by depositing a silicon oxide layer on the entire surface of the semiconductor substrate 101. Then, a patterned photoresist is formed on the first interlayer insulating layer 105, and the patterned photoresist is used as a mask to form a reactive ion etching (Reactive Ion Etching, RI).
The first interlayer insulating layer is selectively removed by etching according to the method E) to form the through-hole 106. After removing the photoresist, a tungsten layer is formed on the first interlayer insulating layer 105 by a CVD method. The thickness of the tungsten layer is set so that the tungsten layer is buried in the entire through hole 106. After that, chemical mechanical polishing (Chemical M
Unnecessary portions of the tungsten layer are removed by mechanical polishing (CMP) to form conductor plugs 107.

Next, an aluminum layer is formed on the first interlayer insulating layer 105 by a sputtering method. This aluminum layer is formed so as to cover the entire surface of the semiconductor substrate 101. Subsequently, after a patterned photoresist is formed on the aluminum layer, R
Etching is performed by the IE method, and the aluminum layer is selectively removed to form the wiring layer 108. After removing the photoresist, a silicon oxide layer is deposited on the interlayer insulating layer 105 to form a third interlayer insulating layer 109.

As described above, the manufacturing process of the conventional semiconductor device shown in FIG. 8 includes several plasma processes. Hereinafter, the influence of the plasma process on the MOS transistor will be described by taking the etching performed in the step of forming the wiring layer 108 as an example.

The term "plasma" refers to a state in which charged particles such as ionized ions and electrons are present at a high density. When the plasma becomes locally non-uniform, the charge balance is lost, and thus the charge is supplied from the plasma to the conductor.

In the step of forming the wiring layer 108, RIE
The aluminum layer is etched by the method. At the initial stage of the etching, the aluminum layer formed so as to cover the entire surface of the semiconductor substrate 101 is not covered with the semiconductor substrate 10 via source / drain regions and the like.
1 connected. With this connection, a low-resistance current path is formed between the aluminum layer and the semiconductor substrate 101. Therefore, electric charges supplied from the plasma to the aluminum layer, which is a conductor, are discharged to the semiconductor substrate 101 through this low-resistance current path. Therefore,
The plasma does not affect the MOS transistor. In the final stage of the etching, so-called over-etching is performed. In this case, since the wiring layer 108 is formed by patterning the aluminum layer, the electric charge supplied to the wiring layer 108 flows into the electrically floating gate electrode 104. Then, charges are accumulated in the gate insulating film 103. The threshold voltage of the MOS transistor fluctuates due to the accumulated charge. That is, the characteristics of the MOS transistor deteriorate.
In the worst case, dielectric breakdown occurs in the gate insulating film 104, and the element is destroyed.

The larger the area of a conductor exposed to plasma (hereinafter, referred to as antenna area), the larger the amount of electric charge supplied to the conductor. Since the antenna area of the wiring layer 108 having a long wiring length is large, the gate electrode 104
The amount of charge flowing into the device increases. Therefore, the above MOS
Deterioration of transistor characteristics and destruction of elements are likely to occur.

In the step of forming the wiring layer 108, a plasma ashing method may be used for removing the photoresist. In some cases, the interlayer insulating layer 109 is formed by a plasma CVD method. In those cases, MOS
Deterioration of the characteristics of the transistor and destruction of the element will be further advanced.

In order to solve this problem, various techniques have been conventionally proposed.

FIG. 9 shows an example of a conventional semiconductor device intended to solve this problem. This conventional semiconductor device is disclosed in JP-A-6-204467.

The conventional semiconductor device shown in FIG. 9 includes a semiconductor substrate 201 made of silicon. Semiconductor substrate 201
A field insulating layer 202 made of silicon oxide is formed in a surface region of the device, and an element formation region (not shown) separated by the field insulating layer 202 is formed. A gate insulating film 203 made of silicon oxide is selectively formed on the element formation region. A gate electrode 204 made of polycrystalline silicon is selectively formed on the gate insulating film 203, and both ends of the gate electrode 204 extend over the field insulating layer 202. A pair of source / drain regions (not shown) are formed in the element formation region so as to sandwich a region immediately below the gate electrode 204. A MOS transistor is formed on the semiconductor substrate 201 by the source / drain regions and the gate electrode 204.

On the field insulating layer 202, a first interlayer insulating layer 205 made of silicon oxide is formed. This first interlayer insulating layer 205 covers the source / drain region and the surface of the gate electrode 204. In the first interlayer insulating layer 205, a through hole 206 reaching the surface of the gate electrode 204 is formed. The inside of the through-hole 206 is filled with a conductor plug 207 made of tungsten. The bottom of the conductor plug 207 is in contact with the top of the gate electrode 204, whereby the conductor plug 207 is electrically connected to the gate electrode 204.

On the first interlayer insulating layer 205, a first wiring layer 208 made of a patterned aluminum layer is formed. The first wiring layer 208 includes a short wiring pattern portion 208A and a long wiring pattern portion 208B. The bottom of the wiring pattern portion 208A is in contact with the top of the conductor plug 207. Thereby,
The wiring pattern portion 208A is electrically connected to the conductor plug 207 and further electrically connected to the gate electrode 204.

A second interlayer insulating layer 209 is formed on the first interlayer insulating layer 205 so as to cover the first wiring layer 208. The second interlayer insulating layer 209 has
Two through holes 210A and 210B are formed. The surfaces of the wiring pattern portions 208A and 208B are exposed from these through holes. On the second interlayer insulating layer 209,
Second wiring layer 2 made of patterned aluminum layer
11 are formed. The second wiring layer 211 extends inside the through holes 210A and 210B, and contacts the tops of the wiring pattern portions 208A and 208B at the bottoms thereof. Thus, the wiring pattern portion 20
8B is the wiring pattern portion 2 via the second wiring layer 211.
08A and further electrically connected to the gate electrode 204.

In the conventional semiconductor device of FIG. 9, the wiring pattern portions 208A and 208B are electrically connected via the second wiring layer 211. Therefore, the wiring pattern portion 208B is not electrically connected to the gate electrode 204 in the step of forming the first wiring layer 208. Therefore, even if the step of forming the first wiring layer 208 includes a plasma process, and the charge is supplied from the plasma to the wiring pattern portion 208B, the charge does not flow into the gate electrode 204. Since the wiring pattern portion 208A electrically connected to the gate electrode 204 has a short length and a small antenna area, the amount of charges supplied from the plasma is reduced. As a result, deterioration of the characteristics of the MOS transistor and destruction of the element are suppressed.

FIG. 10 shows another example of a conventional semiconductor device intended to solve the above problem. This conventional semiconductor device has a structure in which the first wiring layer is divided into two wiring pattern portions similarly to the conventional semiconductor device of FIG.
It differs from the conventional semiconductor device of FIG. 9 in that those two wiring pattern portions are electrically connected via a second wiring layer extending inside the two through holes. Note that FIG.
The conventional semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 7-235541.

The conventional semiconductor device shown in FIG. 10 includes a semiconductor substrate 301 made of silicon. Semiconductor substrate 30
A field insulating layer 302 made of silicon oxide is formed in a surface region of the semiconductor device 1, and an element forming region (not shown) separated by the field insulating layer 302 is formed. A gate insulating film 303 made of silicon oxide is selectively formed on the element formation region. A gate electrode 304 made of polycrystalline silicon is selectively formed on the gate insulating film 303, and both ends of the gate electrode 304 extend on the field insulating layer 302. In the element formation area,
A pair of source / drain regions (not shown) is formed so as to sandwich a region immediately below gate electrode 304. A MOS transistor is formed on the semiconductor substrate 301 by the source / drain regions and the gate electrode 304.

On the field insulating layer 302, a first interlayer insulating layer 305 made of silicon oxide is formed. This first interlayer insulating layer 305 covers the source / drain region and the surface of the gate electrode 304. In the first interlayer insulating layer 305, a through hole 306 reaching the surface of the gate electrode 304 is formed. The inside of the through hole 306 is filled with a conductor plug 307 made of tungsten. The bottom of the conductor plug 307 contacts the top of the gate electrode 304, whereby the conductor plug 307 is electrically connected to the gate electrode 304.

On the first interlayer insulating layer 305, a first wiring layer 308 made of a patterned aluminum layer is formed. The first wiring layer 308 includes a short wiring pattern portion 308A and a long wiring pattern portion 308B. The bottom of the wiring pattern portion 308A is in contact with the top of the conductor plug 307. Thereby,
The wiring pattern portion 308A is electrically connected to the conductor plug 307 and further electrically connected to the gate electrode 304.

On the first interlayer insulating layer 305, a second interlayer insulating layer 309 is formed so as to cover the first wiring layer 308. In the second interlayer insulating layer 309, a through hole 310 is formed. Side portions of the first wiring pattern portions 308A and 308B are exposed from the through hole 310. On the second interlayer insulating layer 309, a second wiring layer 311 made of a patterned aluminum layer is formed. The second wiring layer 311 extends inside the through hole 310, and is in contact with the side of the wiring pattern portions 308A and 308B at the bottom. Thus, the wiring pattern portion 208
B indicates the wiring pattern portion 30 via the second wiring layer 311.
8A, and electrically connected to the gate electrode 304.

In the conventional semiconductor device of FIG. 10, similarly to the conventional semiconductor device of FIG. 9, deterioration of the characteristics of the MOS transistor and destruction of the element are suppressed. That is, the wiring pattern portions 308A and 308B are electrically connected via the second wiring layer 311. Therefore, the wiring pattern portion 308 </ b> B is not electrically connected to the gate electrode 304 in the step of forming the first wiring layer 308. Therefore, the first
Even if the step of forming the wiring layer 308 includes a plasma process, and the electric charge is supplied from the plasma to the wiring pattern portion 308B, the electric charge is not supplied to the gate electrode 304. Since the length of the wiring pattern portion 308A electrically connected to the gate electrode 304 is short and the antenna area is small, the amount of charge supplied from the plasma is reduced. As a result, deterioration of the characteristics of the MOS transistor and destruction of the element are suppressed.

[0029]

As described above, in the conventional semiconductor device shown in FIG.
OS transistors have remarkable deterioration and destruction of characteristics. Therefore, there is a problem that the yield and reliability of the semiconductor device are reduced.

In the conventional semiconductor device of FIG. 9, the electrical connection between the wiring pattern portions 208A and 208B of the first wiring layer 208 is made via the second wiring layer 211. For this reason, the second wiring layer 211 includes the wiring pattern portion 208A.
And a wiring pattern portion for connecting the wiring pattern 208B. Since this wiring pattern portion occupies the surface of the second interlayer insulating layer 209, it prevents the arrangement of another wiring pattern portion of the second wiring layer 211. This means that the degree of integration of the wiring is reduced. Therefore, there is a problem that the degree of integration of the semiconductor device is reduced.

In the conventional semiconductor device of FIG. 10, the electrical connection between the wiring pattern portions 308 A and 308 B of the first wiring layer 308 is made via the second wiring layer 311. For this reason, the second wiring layer 311 includes the wiring pattern portion 308
A wiring pattern portion for connecting A and 308B is required. This wiring pattern portion is formed by the second interlayer insulating layer 30.
9 occupies the surface of the second wiring layer, which hinders the arrangement of other wiring pattern portions of the second wiring layer. This means that the degree of integration of the wiring is reduced. Therefore, there is a problem that the degree of integration of the semiconductor device is reduced.

An object of the present invention is to provide a semiconductor device having a MOS transistor capable of suppressing a decrease in yield and reliability due to a plasma process, and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device having a MOS transistor capable of increasing the degree of integration and a method of manufacturing the same.

[0034]

(1) A first semiconductor device according to the present invention comprises a MOS transistor formed on a semiconductor substrate, and a MOS transistor formed on the semiconductor substrate.
A first interlayer insulating layer covering the gate electrode of the OS transistor and having a first through hole exposing the gate electrode; and a first conductive layer formed inside the first through hole and in contact with the gate electrode. Body plug, a first wiring layer formed on the first interlayer insulating layer and spaced apart from a top of the first conductive plug, and a first wiring layer formed on the first interlayer insulating layer and formed on the first interlayer insulating layer. A second interlayer insulating layer having a second through hole exposing a part of the first wiring layer and the first conductor plug, the second interlayer insulating layer covering the first wiring layer and the first conductor plug; A second conductor plug in contact with each of the first wiring layer and the first conductor plug, wherein the first wiring layer is electrically connected to the first conductor plug via the second conductor plug. And the first wiring layer is connected to the gate. Characterized in that it is electrically connected to the gate electrode.

(2) In the first semiconductor device of the present invention,
The first wiring layer is covered with a second interlayer insulating layer, and the second
A second through hole is provided in the interlayer insulating layer to reach each of the first wiring layer and the first conductor plug, and the second conductor plug formed inside the second through hole is connected to the first wiring layer and the first conductor plug. Contact with each of the conductor plugs. Thereby, the first wiring layer is electrically connected to the first conductor plug via the second conductor plug, and further connected to the gate electrode.

Therefore, the first wiring layer can be formed without connecting the first wiring layer to the gate electrode. In that case, even if the first wiring layer is formed by a plasma process,
Electric charges supplied to the first wiring layer from the plasma do not flow into the gate electrode. Therefore, deterioration and destruction of the characteristics of the MOS transistor due to the plasma process can be suppressed, and a decrease in yield and reliability can be suppressed.

Further, by reducing the opening of the second through hole, the area occupied by the second through hole on the surface of the second interlayer insulating layer can be reduced. Therefore, a decrease in the degree of integration when another wiring layer is provided over the second interlayer insulating layer is suppressed, and the degree of integration of the semiconductor device can be increased.

[0038] The second through-hole preferably has a larger internal dimension than the first through-hole. In this case, there is an advantage that the first wiring layer can reliably contact the second conductor plug without contacting the first conductor plug. Alternatively, the second through hole may be provided eccentrically to the first wiring layer side with respect to the first through hole. In this case, there is an advantage similar to the case where the inner size is increased.

The second conductor plug may be filled in the entire inside of the second through hole, or may be formed only in a part including the bottom of the second through hole.

(3) In a preferred example of the first semiconductor device of the present invention, an insulator plug is further formed on the second conductor plug inside the second through hole,
The surface of the second conductor plug is insulated by the insulator plug. In this case, since another wiring layer can be formed immediately above the second through hole, the integration degree of the semiconductor device can be further increased.

(4) The second semiconductor device according to the present invention is characterized in that the MOS transistor formed on the semiconductor substrate and the gate electrode formed on the semiconductor substrate and covering the gate electrode of the MOS transistor A first interlayer insulating layer having a first through hole exposing a first through hole; and a first interlayer insulating layer formed inside the first through hole and in contact with the gate electrode.
A conductor plug, formed on the first interlayer insulating layer;
A first wiring layer including first and second wiring pattern portions; and the first and second wiring patterns formed on the first interlayer insulating layer and covering the first wiring layer. A second interlayer insulating layer having a second through hole exposing each of the portions, and a second conductor formed inside the second through hole and in contact with each of the first and second wiring pattern portions A plug, and an insulator plug formed on the second conductor plug inside the second through hole, wherein the first wiring pattern portion having a surface area smaller than the second wiring pattern portion is The second wiring pattern portion is in contact with a first conductor plug, and the second wiring pattern portion is electrically connected to the first wiring pattern portion via the second conductor plug, so that the second wiring pattern portion is Game It is electrically connected to the electrode, yet the surface of the second conductive plug is characterized in that it is insulated by the insulator plug.

(5) In the second semiconductor device of the present invention,
The first wiring layer is covered with a second interlayer insulating layer, and the second
A second through hole reaching each of the first and second wiring pattern portions of the first wiring layer is provided in the interlayer insulating layer, and the second conductor plug formed inside the second through hole has the first and second conductor plugs. It comes into contact with each of the second wiring pattern portions. Thereby, the second wiring pattern portion is electrically connected to the first wiring pattern portion via the second conductor plug.
On the other hand, the first wiring pattern portion having a surface having a smaller area than the second wiring pattern portion is in contact with the first conductor plug. Thereby, the second wiring pattern portion is connected to the gate electrode. The surface of the second conductor plug is insulated by the insulator plug formed on the second conductor plug inside the second through hole.

Therefore, the first wiring layer can be formed without connecting the second wiring pattern portion having a large surface area to the gate electrode. In this case, even if the first wiring layer is formed by the plasma process, the charge supplied to the second wiring pattern from the plasma does not flow into the gate electrode. Therefore, deterioration and destruction of the characteristics of the MOS transistor due to the plasma process can be suppressed, and a decrease in yield and reliability can be suppressed.

Further, since the surface of the second conductor plug is insulated, another wiring layer can be formed immediately above the second through hole. Therefore, the degree of integration of the semiconductor device can be increased.

(6) In a first method of manufacturing a semiconductor device according to the present invention, there is provided a step of forming a MOS transistor on a semiconductor substrate, and a first through hole reaching the gate electrode, the gate electrode covering the gate electrode of the MOS transistor. Forming a first interlayer insulating layer having a hole on the semiconductor substrate, forming a first conductor plug in contact with the gate electrode inside the first through hole, and forming the first interlayer insulating layer The first through hole does not include a wiring pattern portion in the opening of the first through hole.
Forming a wiring layer, and forming a second interlayer insulating layer covering the first wiring layer and having a second through-hole reaching each of the first wiring layer and the first conductor plug by the first interlayer Forming a second conductor plug in contact with each of the first wiring layer and the first conductor plug inside the second through hole; In the step of forming a conductor plug, the first wiring layer is connected to the first wiring layer via the first conductor plug.
It is electrically connected to a conductor plug, so that the first wiring layer is electrically connected to the gate electrode.

(7) In the first method for manufacturing a semiconductor device according to the present invention, the first wiring layer is covered with the second interlayer insulating layer, as in the first semiconductor device according to the present invention. A second through hole is provided in the interlayer insulating layer to reach a part of the first wiring layer and each of the first conductor plugs, and each of the first wiring layer and the first conductor plug is provided inside the second through hole. A contacting second conductor plug is formed. Further, the first wiring layer is electrically connected to the first conductor plug via the second conductor plug, and further connected to the gate electrode.

Therefore, the first wiring layer can be formed without connecting the first wiring layer to the gate electrode. In that case, even if the first wiring layer is formed by a plasma process,
Electric charges supplied to the first wiring layer from the plasma do not flow into the gate electrode. Therefore, deterioration and destruction of the characteristics of the MOS transistor due to the plasma process can be suppressed, and a decrease in yield and reliability can be suppressed.

Further, by reducing the opening of the second through-hole, the area occupied by the second through-hole on the surface of the second interlayer insulating layer can be reduced. Therefore, a decrease in the degree of integration when another wiring layer is provided over the second interlayer insulating layer is suppressed, and the degree of integration of the semiconductor device can be increased.

(8) In a preferred example of the first method of manufacturing a semiconductor device according to the present invention, the method further comprises a step of forming an insulator plug on the second conductor plug inside the second through hole. The surface of the second conductor plug is insulated by the insulator plug. In this case, since another wiring layer can be formed immediately above the second through hole, there is an advantage that the degree of integration of the semiconductor device can be further increased.

In another preferred example of the first method of manufacturing a semiconductor device according to the present invention, the step of forming the second conductor plug includes the step of forming the second conductive plug so as to cover the inside of the second through hole. Forming a conductor layer on an insulating layer; and etching back the conductor layer to leave the second conductor plug inside the second through-hole. In the forming step, a recess is formed on the conductor layer inside the second through hole.
In this case, there is an advantage that the insulation of the surface of the second conductor plug by the insulator plug is reliably performed.

(9) In a second method of manufacturing a semiconductor device according to the present invention, a step of forming a MOS transistor on a semiconductor substrate and a first through hole reaching the gate electrode, which cover the gate electrode of the MOS transistor, Forming a first interlayer insulating layer having a hole on the semiconductor substrate, forming a first conductor plug in contact with the gate electrode inside the first through hole, and forming the first interlayer insulating layer First on
Forming a first wiring layer including a second wiring pattern portion and a second through hole reaching each of the first and second wiring pattern portions covering the first wiring layer. Forming a second interlayer insulating layer on the first interlayer insulating layer, and forming the first interlayer insulating layer inside the second through hole.
Forming a second conductor plug in contact with each of the second wiring pattern portions, and forming an insulator plug on the second conductor plug inside the second through hole, In the step of forming the first wiring layer, the first wiring pattern portion having a surface having an area smaller than that of the second wiring pattern portion is formed in contact with the first conductor plug, and the second conductor plug is formed. In the step of forming, the second wiring pattern portion is electrically connected to the first wiring pattern portion via the second conductor plug, so that the second wiring pattern portion is electrically connected to the gate electrode. In the step of forming the insulator plug, the surface of the second conductor plug is insulated by the insulator plug.

(10) In the method of manufacturing a second semiconductor device according to the present invention, the first method is the same as in the second semiconductor device of the present invention.
The wiring layer is covered with a second interlayer insulating layer, and the second interlayer insulating layer is provided with a second through hole reaching each of the first and second wiring pattern portions of the first wiring layer. A second conductor plug that is in contact with each of the first and second wiring pattern portions is formed inside the through hole. Thereby, the second wiring pattern portion is electrically connected to the first wiring pattern portion via the second conductor plug. On the other hand, the first wiring pattern portion having a surface having an area smaller than that of the second wiring pattern portion is formed in contact with the first conductor plug. Thereby, the second wiring pattern portion is connected to the gate electrode. Then, an insulator plug is formed on the second conductor plug inside the second through-hole, whereby the surface of the second conductor plug is insulated.

Therefore, the first wiring layer can be formed without connecting the second wiring pattern portion having a large surface area to the gate electrode. In this case, even if the first wiring layer is formed by the plasma process, the charge supplied to the second wiring pattern from the plasma does not flow into the gate electrode. Therefore, deterioration and destruction of the characteristics of the MOS transistor due to the plasma process can be suppressed, and a decrease in yield and reliability can be suppressed.

Since the surface of the second conductor plug is insulated, another wiring layer can be formed immediately above the second through hole. Therefore, the degree of integration of the semiconductor device can be increased.

(11) In a preferred example of the second method for manufacturing a semiconductor device of the present invention, the step of forming the second conductor plug includes forming the first conductor plug so as to cover the inside of the second through hole. Forming a conductor layer on an interlayer insulating layer; and etching back the conductor layer to leave the second conductor plug inside the second through hole. Forming a concave portion on the conductor layer inside the second through hole. In this case, there is an advantage that the insulation of the surface of the second conductor plug by the insulator plug is reliably performed.

[0056]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(First Embodiment) [Configuration] FIGS. 1A and 1B show a semiconductor device according to a first embodiment of the present invention.

The semiconductor device of FIG. 1 includes a semiconductor substrate 1 made of a commonly used semiconductor material such as silicon. A field insulating layer 2 made of silicon oxide is formed in a surface region of the semiconductor substrate 1, and an element forming region 14 having a substantially rectangular planar shape separated by the field insulating layer 2 is formed. On the element formation region 14, a gate insulating film 3 made of silicon oxide and having a substantially rectangular planar shape is selectively formed. A gate electrode 4 made of polycrystalline silicon is selectively formed on the gate insulating film 3, and both ends of the gate electrode 4 extend on the field insulating layer 2. The gate electrode 4 has a substantially rectangular main body portion 4 a formed so as to overlap the gate insulating film 3 in the element forming region 14, and a width larger than the main body portion 4 a formed on the field insulating layer 2. And a contact portion 4b having a wide, substantially square planar shape. A pair of source / drain regions 15 and 16 composed of an n-type diffusion region are formed in the element formation region 14 so as to sandwich a region immediately below the gate electrode 4. A MOS transistor is formed on the semiconductor substrate 1 by the source / drain regions 15 and 16 and the gate electrode 4.

On the field insulating layer 2, a first interlayer insulating layer 5 made of silicon oxide is formed. The first interlayer insulating layer 5 covers the source / drain regions 15 and 16 and the gate electrode 4. A first through hole 6 is formed in the first interlayer insulating layer 5. The opening shape of the first through hole 6 is a substantially square having a side length of 0.4 μm. The first through-hole 6 is disposed immediately above the contact portion 4 b of the gate electrode 4, and the surface of the gate electrode 4 is exposed at the bottom of the first through-hole 6. The inside of the first through hole 6 is filled with a first conductor plug 7 made of tungsten.
The bottom of the first conductor plug 7 contacts the contact portion 4b of the gate electrode 4, so that the first conductor plug 7 is electrically connected to the gate electrode 4.

The opening area of the first through hole 6 is set to a size that allows the first conductor plug 7 to be sufficiently filled.
In addition, the opening size of the first through hole 6 is set such that the area of the top of the conductor plug 6 exposed on the surface of the first interlayer insulating layer 5 is sufficiently small.

On the first interlayer insulating layer 5, a first wiring layer 8 made of a patterned aluminum layer is formed. The wiring pattern portion of the first wiring layer 8 is arranged so as not to be included in the opening of the first through hole 6 so that the first wiring layer 8 is not directly connected to the conductor plug 6. .

On the first interlayer insulating layer 5, a first wiring layer 8
Second interlayer insulating layer 9 made of silicon oxide so as to cover
Are formed. A second through-hole 10 is formed in the second interlayer insulating layer 9 so as to be substantially concentric with the first through-hole 6. The opening shape of the second through hole 10 is such that one side has a length of 0.
It is approximately 8 μm square. Inside the second through hole 10,
The second conductor plug 11 made of tungsten is filled. The bottom of the second conductor plug 11 is
0 is in contact with the exposed top of the conductor plug 6 at the bottom. One side 11a of the second conductor plug 11
Is the first wiring layer 8 exposed from the side wall of the second through hole 10.
Is in contact with one end 8a. Thus, the second conductor plug 11 is electrically connected to the conductor plug 6 and is also electrically connected to the first wiring layer 8.

The end 8a of the first wiring layer 8 is
The opening size of the second through hole 10 is set to be larger than the opening size of the first through hole 6 in order to surely expose the second through hole 10 from the side wall portion. That is, the distance from the central axis of the first through hole 6 to its opening is d ₁ , the distance from the opening of the first through hole 6 to the end 8a of the first wiring layer 8 is d ₂ , Assuming that the distance from the central axis to the opening is d ₃ , d ₃ ≧ d ₁
+ D ₃ so that the relation d ₂ is satisfied is set. In this case, there is an advantage that the design data of the second through-hole 10 can be automatically determined from the design data of the first through-hole 6, and the design becomes easy. In addition, the opening size of the second through hole 10 is set such that the area of the top of the second conductor plug 11 exposed on the surface of the second interlayer insulating layer 9 is sufficiently small.

Instead of increasing the opening size of the second through hole 10, the second through hole 10 may be decentered toward the first wiring layer 8 with respect to the first through hole 6. Also in this case, the end 8a of the first wiring layer 8 can be reliably exposed from the side wall of the second through hole 10.

On the second interlayer insulating layer 9, a second wiring layer 12 made of a patterned aluminum layer is formed. A third interlayer insulating layer 13 made of silicon oxide is formed on the second interlayer insulating layer 9 so as to cover the second wiring layer 12.
Are formed.

In the semiconductor device of the first embodiment having the above configuration, the first wiring layer 8 is connected to the gate electrode 4 via the second conductor plug 11 and the first conductor plug 7. Therefore, the first wiring layer 8 can be formed without connecting the first wiring layer 8 to the gate electrode 4. In this case, even if the first wiring layer 8 is formed by a plasma process, the charge supplied to the first wiring layer 8 from the plasma does not flow into the gate electrode. During the plasma process, the top of the first conductor plug 7 is exposed to the plasma to supply a charge. However, since the opening area of the first through hole 6 is small and the antenna area of the first conductor plug 7 is smaller than that of the first wiring layer 8, the amount of charge flowing into the gate electrode 4 is small. Further, even if the second wiring layer 12 is formed by a plasma process, the opening area of the second through hole 10 is small,
Since the antenna area of the conductor plug 11 is small, the amount of charge flowing into the gate electrode 4 is small. Therefore, deterioration and destruction of the characteristics of the MOS transistor due to the plasma process can be suppressed, and the yield and reliability can be improved.

The surface area of the top of the second conductor plug 11 exposed on the surface of the second interlayer insulating layer 9 is small. Therefore, a decrease in the degree of integration of the second wiring layer 12 is suppressed, and the degree of integration of the semiconductor device can be increased. [Manufacturing Method] FIGS. 2 to 3 are partial cross-sectional views showing steps of a method of manufacturing a semiconductor device according to the first embodiment of the present invention having the above-described structure. Hereinafter, each step will be described.

First, a semiconductor substrate 1 made of p-type silicon
For example, a known LOCOS (LOCal Oxid
The field insulating layer 2 made of a silicon oxide layer is selectively formed by using the method of "Sation of Silicon". An element formation region (not shown) where a MOS transistor is to be formed is defined on semiconductor substrate 1 by field insulating layer 2. Next, a silicon oxide film (not shown) is formed on the element formation region of the semiconductor substrate 1 by a known thermal oxidation method.
Subsequently, a polycrystalline silicon layer (not shown) is deposited on the entire surface of the semiconductor substrate 1 by a known thermal CVD method. Thereafter, a photoresist patterned by photolithography is formed on the polycrystalline silicon layer, and etching is performed using the patterned photoresist as a mask to selectively and simultaneously remove the silicon oxide film and the polycrystalline silicon layer. Thus, the gate insulating film 3 and the gate electrode 4 are formed. Further, an n-type impurity such as arsenic or phosphorus is ion-implanted using a known ion implantation method to form a source / drain region (not shown) including an n-type diffusion region in the element formation region. At this time,
N-type impurities are also ion-implanted into the gate electrode 4 to increase the conductivity of the gate electrode 4.

Next, a silicon oxide layer is deposited on the entire surface of the semiconductor substrate 1 by a known thermal CDV method to form a first interlayer insulating layer 5. Subsequently, after a patterned photoresist is formed on the first interlayer insulating layer 5 by photolithography, the first interlayer insulating layer 5 is selectively removed by a known RIE method using the photoresist as a mask. Thus,
First through holes 6 are formed in first interlayer insulating layer 5.

Subsequently, a tungsten layer (not shown) is deposited on the entire semiconductor substrate 1 by a known CVD method. The thickness of the tungsten layer is set so that the tungsten layer can fill the entire first through hole 6. Thereafter, the tungsten layer is removed by a CMP method until the first interlayer insulating layer 5 is exposed, and the tungsten layer is selectively left only inside the first through hole 6. Thus, the first conductor plug 7 is formed inside the first through hole 6 as shown in FIG. This first conductor plug 7
The bottom contacts the top of the gate electrode 4 and is thereby electrically connected to the gate electrode 4.

Further, the semiconductor substrate 1 is formed by sputtering.
An aluminum layer (not shown) is formed on the entire upper surface. Subsequently, a photoresist patterned by photolithography is formed on the aluminum layer, and the aluminum layer is selectively removed by RIE using the photoresist as a mask. After that, the photoresist is removed, and the first wiring layer 8 is formed on the first interlayer insulating layer 5. The state at this time is shown in FIG.

Next, a silicon oxide layer is deposited on the entire surface of the semiconductor substrate 1 by a thermal CVD method, and a second interlayer insulating layer 9 is formed on the first interlayer insulating film 5. Subsequently, after a patterned photoresist is formed on the second interlayer insulating layer 9 by photolithography, the second interlayer insulating layer 9 is selectively removed by RIE using the photoresist as a mask.
Thus, the second through-hole 10 having a substantially square cross-sectional shape
Is formed on the second interlayer insulating layer 9. The state at this time is shown in FIG.
(B).

Further, as shown in FIG.
The tungsten layer 17 is entirely formed on the semiconductor substrate 1 by the method.
To form The thickness of the tungsten layer 17 is set so that the tungsten layer 17 can fill the entire second through hole 10. Subsequently, the tungsten layer 17 is removed by the CMP method until the second interlayer insulating layer 9 is exposed, and the tungsten layer 17 is selectively left only inside the second through hole 10. Thus, as shown in FIG. 3B, the second conductor plug 11 is formed inside the second through hole 10. The bottom of the second conductor plug 11 is in contact with the top of the first conductor plug 7, and the side is in contact with the end of the first wiring layer 8. Thus, the first wiring layer 8 is electrically connected to the gate electrode 4.

Next, an aluminum layer (not shown) is formed on the entire semiconductor substrate 1 by sputtering. Subsequently, a photoresist patterned by photolithography is formed on the aluminum layer, and the aluminum layer is selectively removed by RIE using the photoresist as a mask. After that, remove the photoresist,
Second wiring layer 12 is formed on second interlayer insulating layer 9.
Further, a silicon oxide layer is deposited on the entire semiconductor substrate 1 by a thermal CVD method, and a third interlayer insulating layer 13 is formed on the second interlayer insulating layer 9.

Through the above steps, the semiconductor device of the first embodiment shown in FIG. 1 is completed.

Next, the effect of the plasma process on the MOS transistor in the method of manufacturing the semiconductor device according to the first embodiment will be described.

In the step of forming the first through hole 6, since the RIE method, which is one of the plasma processes, is used, electric charges are supplied from the plasma to the gate electrode 4. However, in this case, since the opening area of the first through hole 6 is small, the antenna area of the gate electrode 4 is also small. Therefore, the amount of charge supplied to the gate electrode 4 is small.

In the step of forming the first wiring layer 8, RIE
The aluminum layer is etched by the method. In the initial stage of the etching, the aluminum layer formed so as to cover the entire surface of the semiconductor substrate 1 is connected to the semiconductor substrate 1 via a source / drain region or the like at a portion not shown. By this connection, a low-resistance current path is formed between the aluminum layer and the semiconductor substrate 1. For this reason, the electric charge supplied to the aluminum layer from the plasma passes through the low-resistance current path to the semiconductor substrate 1.
Will be released. Therefore, no charge flows from the plasma into the gate electrode 4. In the final stage of the etching, so-called over-etching is performed. At the time of over-etching, charges are supplied to the first conductor plug 7 and the first wiring layer 8 from the plasma. However, since the first wiring layer 8 is not electrically connected to the gate electrode 4, the supplied charge does not flow into the gate electrode 4. Further, since the opening area of the first through hole 6 is small and the antenna area of the first conductor plug 7 is small, the amount of charge flowing into the gate electrode 4 is reduced.

In the step of forming the first wiring layer 8, even when the plasma ashing method is used for removing the photoresist, the amount of charge flowing into the gate electrode 4 is reduced for the same reason as when etching the aluminum layer. Less.

In the step of forming the second through hole 10, the RI
Since the E method is used, electric charges are supplied from the plasma to the conductor plug. However, since the opening area of the second through hole 10 is small and the antenna area of the conductor plug 11 is small, the amount of charge flowing into the gate electrode 4 is small.

In the step of forming the second wiring layer 12, RI
The aluminum layer is etched by the E method. Also in this case, during over-etching, the second
Electric charges are supplied to the conductor plug 11 and the second wiring layer 12. However, since the second wiring layer 12 is not electrically connected to the gate electrode 4, the supplied charge is
Does not flow into Further, since the opening area of the second through hole 10 is small and the antenna area of the second conductor plug 11 is small, the amount of charge flowing into the gate electrode 4 is reduced.

In the step of forming the second wiring layer 12,
When the plasma ashing method is used for removing the photoresist, the amount of charge flowing into the gate electrode 4 is reduced for the same reason as when etching the aluminum layer.

As described above, according to this manufacturing method, the amount of charge flowing into the gate electrode 4 due to the plasma process is reduced. Therefore, MO by plasma process
Deterioration and destruction of the characteristics of the S transistor can be suppressed, and yield and reliability can be improved.

According to this manufacturing method, the surface area of the second conductor plug 11 exposed on the surface of the second interlayer insulating layer 9 is reduced. Therefore, a decrease in the degree of integration of the wiring is suppressed, and the degree of integration of the semiconductor device can be increased.

(Second Embodiment) [Structure] FIG. 4 shows a semiconductor device according to a second embodiment of the present invention.

The semiconductor device of FIG. 4 has a semiconductor substrate 1, a field insulating layer 2, like the semiconductor device of the first embodiment.
A gate insulating film 3, a first interlayer insulating layer 5, a first through hole 6, and a first conductor plug 7 are provided. Since they have the same configuration as the semiconductor device of the first embodiment shown in FIG. 1, the same reference numerals are given to the same or corresponding elements in FIG. 4 as those of the semiconductor device of the first embodiment of FIG. The description is omitted. The semiconductor device according to the first embodiment is the same as the semiconductor device according to the first embodiment in that an element formation region and source / drain regions (both not shown) are provided.

On the first interlayer insulating layer 5, a first wiring layer 28 made of a patterned aluminum layer is formed. The first wiring layer 28 has wiring pattern portions 28A, 28B and 28C separated from each other. A part of the bottom of the wiring pattern portion 28 </ b> A is in contact with the first conductor plug 7. Thereby, the wiring pattern portion 28A is electrically connected to the first conductor plug 7,
Further, it is electrically connected to the gate electrode 4. The end 28Ba of the wiring pattern portion 28B is
It is arranged at a predetermined distance from the end 28Aa of A.

The dimensions of the surface of the wiring pattern portion 28A are:
The size is set to a sufficiently large value so that the electrical connection with the conductor plug is possible. In addition, the dimensions of the surface are set so that the surface area of the wiring pattern portion 28A becomes sufficiently small. In the case of this embodiment, the surface shape of the wiring pattern portion 28A is a substantially rectangular shape having a width of 0.4 μm and a length of 1.0 μm.

On the first interlayer insulating layer 5, the first wiring layer 2
A second interlayer insulating layer 9 made of silicon oxide is formed so as to cover 8. A second through-hole 30 and a third through-hole 40 each having a substantially rectangular cross-sectional shape are formed in the second interlayer insulating layer 9. The second through hole 30 has an end 28Aa.
And 28Ba, and the end portions 28Aa and 28Ba are exposed at the bottom of the second through hole 30. The third through hole 40 is disposed on the wiring pattern portion 28C, and the surface of the wiring pattern portion 28C is
It is exposed from 0.

A second conductor plug 31 made of tungsten is formed at the bottom and the side wall of the second through hole 30. The second conductor plug 31 has ends 28Aa and 28Ba.
And a recess is formed. An insulator plug made of silicon oxide is formed in the recess, and the insulator plug covers the entire surface of the second conductor plug 31. Thus, the inside of the second through hole 50 is filled with the second conductor plug 31 and the insulator plug 34. Second
The conductor plug 31 is connected to the end 28 at the bottom of the second through hole 30.
It is in contact with Aa and 28Ba. Thereby, the second conductor plug 31 is electrically connected to the wiring pattern portion 28A and is also electrically connected to the wiring pattern portion 28B. Thus, the wiring pattern portion 28B is electrically connected to the wiring pattern portion 28A, and is further electrically connected to the gate electrode 4 via the first conductor plug 7.

The inside of the third through hole 40 is filled with a third conductor plug 41 made of tungsten. Third
The bottom of the conductor plug 41 is in contact with the wiring pattern portion 28C, whereby the wiring pattern portion 28C is electrically connected to the third conductor plug 41.

The opening size of the second through hole 30 is set larger than that of the third through hole 40. For example, the second through hole 3
The distance from the central axis of 0 to the opening is the third through hole 40
Is about twice or more the distance from the central axis of the to the opening.
Thereby, when the second conductor plug 31 and the third conductor plug 41 are formed at the same time, a gap for forming the insulator plug 34 is secured inside the second through-hole 30, so that the second conductor plug 31 is formed. The surface of the plug 31 can be reliably covered with the insulator plug 34. In addition, the second conductor plug 31
The opening size of the second through-hole 30 is set such that the area of the surface exposed from the second through-hole 30 becomes sufficiently small. The distance between the end portions 28Aa and 28Ba is
It is set smaller than the distance from the central axis of 0 to its opening. Thus, the electrical connection between the wiring pattern portions 28A and 28B by the second conductor plug 31 is reliably made. In this embodiment, the opening shape of the second through hole 30 is a substantially square having a side length of 0.8 μm, and the opening shape of the third through hole 40 is a substantially square having a side length of 0.4 μm. . The distance between the ends 28Aa and 28Ba is 0.4 μm.

On the second interlayer insulating layer 9, a second wiring layer 12 made of a patterned aluminum layer is formed. The second wiring layer 12 extends directly above the insulating plug. The second wiring layer 1 is formed on the second interlayer insulating layer 9.
A third interlayer insulating layer 13 made of silicon oxide is formed so as to cover 2.

As described above, in the semiconductor device according to the second embodiment of the present invention, the first wiring layer 8 has the wiring pattern portions 28A and 28B. Then, the wiring pattern portion 28B is electrically connected to the wiring pattern portion 28A via the second conductor plug 31. Therefore, the first wiring layer 28 can be formed without connecting the wiring pattern portion 28B having a large surface area to the gate electrode 4. In this case, even if the first wiring layer 28 is formed by the plasma process, the charge supplied to the wiring pattern portion 28B from the plasma does not flow into the gate electrode. During the plasma process, a charge is supplied to the wiring pattern portion 28A exposed to the plasma. However, since the surface area of the wiring pattern portion 28A is small and the antenna area of the wiring pattern portion 28A is small, the amount of charge flowing into the gate electrode 4 is reduced. Even if the second wiring layer 12 is formed by a plasma process, the second conductor plug 31 flows into the gate electrode 4 because the second conductor plug 31 is covered with the insulator plug 34 and is insulated from the second wiring layer 12. Nothing. Therefore, deterioration and destruction of the characteristics of the MOS transistor due to the plasma process can be suppressed, and the yield and reliability can be improved.

Further, since the second conductor plug 31 is covered with the insulator plug 34, it is insulated from the second wiring layer 12. For this reason, since the second wiring layer 12 can be formed on the insulator plug 34, the degree of integration can be further increased as compared with the case of the first embodiment. [Manufacturing Method] FIGS. 5 to 6 are partial sectional views showing steps of a method of manufacturing the semiconductor device according to the first embodiment of the present invention having the above-described structure. Hereinafter, each step will be described.

First, a semiconductor substrate 1 made of p-type silicon
After a field insulating layer 2, a pair of source / drain regions (not shown), a gate electrode 4, and a first interlayer insulating layer 5 are formed thereon, a through hole is formed in the first interlayer insulating layer 5 to form a through hole therein. The first conductor plug 7 is filled. The steps up to this point are the same as those in the case of the semiconductor device of the first embodiment shown in FIG.

Next, an aluminum layer (not shown) is formed on the entire semiconductor substrate 1 by sputtering. Subsequently, a photoresist patterned by photolithography is formed on the aluminum layer, and the aluminum layer is selectively removed by RIE using the photoresist as a mask. After that, remove the photoresist,
The wiring pattern portions 28A, 28B, 2
A first wiring layer 28 having 8C is formed on first interlayer insulating layer 5. The state at this time is shown in FIG.

The wiring pattern portion 28A is formed such that a portion of the bottom thereof is in contact with the top of the first conductor plug 7. The wiring pattern portion 28B is a wiring pattern portion 2
It is arranged at a predetermined distance from 8A.

Next, a silicon oxide layer is deposited on the entire surface of the semiconductor substrate 1 by a thermal CVD method, and a second interlayer insulating layer 9 is formed on the first interlayer insulating film 5. Subsequently, after a patterned photoresist is formed on the second interlayer insulating layer 9 by photolithography, the second interlayer insulating layer 9 is selectively removed by RIE using the photoresist as a mask.
Thus, the second through-hole 30 having a substantially square cross-sectional shape
And a third through hole 40 are formed in the second interlayer insulating layer 9. The second through holes 30 are formed in the wiring pattern portions 28A and 28B.
Are formed so as to expose the respective end portions 28Aa and 28Ba.

Further, a tungsten layer 37 is formed on the entire semiconductor substrate 1 by the CVD method. The thickness of the tungsten layer 37 is such that the third through hole 40
Is set so that the whole can be filled. In this embodiment, since the opening shape of the third through hole 40 is a substantially square having a side length of 0.4 μm, the tungsten layer 37
Is set to 0.3 μm. Since the opening shape of the second through-hole 30 is approximately square with a side length of 0.8 μm, the inside of the second through-hole 30 cannot be completely filled with the tungsten layer 37, and the concave portion 38 is formed. The state at this time is shown in FIG.

Subsequently, the tungsten layer 37 is etched back by RIE until the second interlayer insulating layer 9 is exposed. In this way, as shown in FIG.
0, a second conductor plug 31 is formed on the bottom and side walls,
A third conductor plug 41 filling the third through hole 40 is formed. The recess 38 is formed by this etch back.
Is enlarged, and a concave portion 39 is formed inside the second through hole 30. The second conductor plug 31 is in contact with the ends of the wiring pattern portions 28A and 28B at the bottom of the second through hole 30. Thereby, the wiring pattern portion 28B is electrically connected to the wiring pattern portion 28A, and furthermore, the gate electrode 4
Is electrically connected to The bottom of the third conductor plug 41 is in contact with the top of the wiring pattern portion 28C. Thereby, the third conductor plug 41 is connected to the wiring pattern portion 2.
8C.

Next, a silicon oxide layer (not shown) is deposited on the entire surface of the semiconductor substrate 1 by a thermal CVD method. Thereafter, the silicon oxide layer is etched back by RIE until the second interlayer insulating layer 9 is exposed, thereby forming an insulator plug 34. Thus, as shown in FIG. 6B, the recess 38 inside the second through-hole 30 is filled with the insulator plug 34.

Further, the semiconductor substrate 1 is formed by sputtering.
An aluminum layer (not shown) is formed on the entire upper surface. Subsequently, a photoresist patterned by photolithography is formed on the aluminum layer, and the aluminum layer is selectively removed by RIE using the photoresist as a mask. After that, the photoresist is removed, and the second wiring layer 12 is formed on the second interlayer insulating layer 9. Part of the bottom of the second wiring layer 12 is in contact with the top of the third conductor plug 41. Thereby, the second wiring layer 1
2 is electrically connected to the third conductor plug 41 and further electrically connected to the wiring pattern portion 28C. The second wiring layer 12 is formed to extend over the second through hole 30. Subsequently, a silicon oxide layer is deposited on the entire surface of the semiconductor substrate 1 by a thermal CVD method, and a third interlayer insulating layer 13 is formed on the second interlayer insulating layer 9.

Through the above steps, the semiconductor device of the second embodiment shown in FIG. 4 is completed.

Next, the effect of the plasma process on the MOS transistor in the method of manufacturing the semiconductor device according to the second embodiment will be described.

In the step of forming the first wiring layer 28, RI
The aluminum layer is etched by the E method. In the initial stage of the etching, the aluminum layer formed so as to cover the entire surface of the semiconductor substrate 1 is connected to the semiconductor substrate 1 via a source / drain region or the like at a portion not shown. By this connection, a low-resistance current path is formed between the aluminum layer and the semiconductor substrate 1. For this reason, the electric charge supplied to the aluminum layer from the plasma is discharged to the semiconductor substrate 1 through this low-resistance current path. Therefore, no charge flows from the plasma into the gate electrode 4. In the final stage of etching,
So-called over-etching is performed. At the time of over-etching, the wiring pattern portion 28A,
Electric charges are supplied to 28B and 28C. However, since the wiring pattern portions 28B and 28C are not electrically connected to the gate electrode 4, the supplied charges do not flow into the gate electrode 4. In addition, since the surface area of the wiring pattern portion 28A is small and the antenna area thereof is also small, the amount of charge flowing into the gate electrode 4 is reduced.

In the step of forming the first wiring layer 28,
When the plasma ashing method is used for removing the photoresist, the amount of charge flowing into the gate electrode 4 is reduced for the same reason as when etching the aluminum layer.

In the step of forming the second through hole 30, the RI
Since the E method is used, the wiring pattern portion 28 is removed from the plasma.
Electric charges are supplied to the ends 28Aa and 28Ba of A and 28B. Since the wiring pattern portion 28B is not connected to the gate electrode 4, charges flow into the gate electrode 4 only through the wiring pattern portion 28A. In this case, the end 28Aa
Has a small surface area and a small antenna area, so that the amount of charge flowing into the gate electrode 4 is small.

In the step of forming the second conductor plug 31, the tungsten layer is etched by RIE. Also in this case, at the time of over-etching, electric charges are supplied to the second conductor plug 31 from the plasma. However, since the opening area of the second through hole 30 is small and the antenna area of the second conductor plug 31 is small, the amount of charge flowing into the gate electrode 4 is reduced.

In the step of forming the second wiring layer 12, RI
The aluminum layer is etched by the E method. Also in this case, the charge is supplied to the second wiring layer 12 at the time of over-etching. However, since the second conductor plug 31 and the second wiring layer are insulated by the insulator plug 34, the charge supplied to the second wiring layer 12 does not flow into the gate electrode 4.

In the step of forming the second wiring layer 12,
Even when the plasma ashing method is used for removing the photoresist, no charge flows into the gate electrode 4 for the same reason as when etching the aluminum layer.

As described above, according to this manufacturing method, the amount of charge flowing into the gate electrode 4 due to the plasma process is reduced. Therefore, MO by plasma process
Deterioration and destruction of the characteristics of the S transistor can be suppressed, and reduction in yield and reliability can be suppressed.

Further, since the second conductor plug 31 is covered with the insulator plug 34, it is insulated from the second wiring layer 12. For this reason, since the second wiring layer 12 can be formed on the insulator plug 34, the degree of integration can be further increased as compared with the case of the first embodiment.

(Third Embodiment) FIG. 7 shows a semiconductor device according to a third embodiment of the present invention.

The semiconductor device of FIG. 7 is different from the semiconductor device of the first embodiment in that a second conductor plug and an insulator plug are formed inside the second through-hole, similarly to the semiconductor device of the second embodiment. Except for this, it has the same configuration as the semiconductor device of the first embodiment of FIG. Therefore, in FIG. 7, the same or corresponding elements as those of the semiconductor device of the first embodiment in FIG.

The second interlayer insulating layer 9 is provided with a second through hole 50 which is arranged substantially concentrically with the first through hole 6 and has a substantially rectangular opening shape. At the bottom of the second through hole 50, the end of the first wiring layer 8 and the top of the first conductor plug 7 are exposed.

A second conductor plug 51 made of tungsten is formed on the bottom and the side wall of the second through hole 50. The second conductor plug 51 covers the end of the second wiring layer 8 and the top of the first conductor plug 7, and is curved to form a concave portion. An insulator plug 54 made of silicon oxide is formed in the recess, and the insulator plug 54 covers the entire surface of the second conductor plug 51. Thus, the inside of the second through hole 50 is filled with the second conductor plug 51 and the insulator plug 54. The bottom of the second conductor plug 51 is in contact with the top of the first conductor plug 7 and the side is the first conductor plug 7.
It is in contact with the end of the wiring layer 8. Thereby, the second conductor plug 51 is electrically connected to the first conductor plug 7 and to the first wiring layer 8. Thus, the first wiring layer 8 is electrically connected to the first conductor plug via the second conductor plug 51 and further electrically connected to the gate electrode 4.

In the semiconductor device of the third embodiment having the above configuration, the first wiring layer 8 can be formed without connecting the first wiring layer 8 to the gate electrode 4. In this case, even if the first wiring layer 8 is formed by a plasma process, the charge supplied to the first wiring layer 8 from the plasma does not flow into the gate electrode. Further, the opening area of the first through hole 6 is small, and the antenna area of the first conductor plug 7 is smaller than the first wiring layer 8.
Therefore, the amount of charge flowing into the gate electrode 4 is small. Further, even if the second wiring layer 12 is formed by a plasma process, no charge flows into the gate electrode 4 because the surface of the second conductor plug 51 is insulated by the insulator plug 54. Therefore, plasma
Deterioration or destruction of the characteristics of the MOS transistor due to the process can be suppressed, and reduction in yield and reliability can be suppressed.

Further, since the second conductor plug 31 is covered with the insulator plug 34, it is insulated from the second wiring layer 12. For this reason, as shown in FIG.
4, the second wiring layer 12 can be formed.
The degree of integration can be further increased than in the case of the first embodiment.

The method for manufacturing the semiconductor device according to the third embodiment is easily understood from the method for manufacturing the semiconductor device according to the first and second embodiments, and therefore, the description thereof is omitted here.

[0121]

As described above, according to the semiconductor device and the method for manufacturing the same of the present invention, the yield and reliability due to the plasma process can be suppressed. Further, the degree of integration can be increased.

[Brief description of the drawings]

FIG. 1A is a partial plan view showing a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a partial cross-sectional view taken along the line AA.

FIG. 2 is a partial cross-sectional view taken along line AA of FIG. 1A, illustrating each step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a partial cross-sectional view taken along line AA of FIG. 1A, showing respective steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and is a continuation of the step of FIG.

FIG. 4 is a partial cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a partial sectional view showing each step of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a partial cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, and is a continuation of FIG. 5;

FIG. 7 is a partial cross-sectional view illustrating a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a partial sectional view showing a conventional semiconductor device.

FIG. 9 is a partial sectional view showing another conventional semiconductor device.

FIG. 10 is a partial sectional view showing still another conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 field insulating layer 3 gate insulating film 4 gate electrode 5 first interlayer insulating layer 6 first through hole 7 first conductor plug 8 first wiring layer 8 a end of first wiring layer 9 second interlayer insulating layer DESCRIPTION OF SYMBOLS 10 2nd through-hole 11 2nd conductor plug 11a The side part of 2nd conductor plug 12 2nd wiring layer 13 3rd interlayer insulation layer 14 element formation area 15, 16 source / drain area 17 tungsten layer 28 1st wiring layer 28A Wiring pattern part 28B Wiring pattern part 28C Wiring pattern part 28Aa End part of wiring pattern part 28Ba End part of wiring pattern part 30 Second through hole 31 Second conductor plug 34 Insulator plug 37 Tungsten layer 38, 39 Recess 40 3 through hole 41 third conductor plug 50 second through hole 51 second conductor plug 54 insulator plug

Claims (8)

(57) [Claims] A first transistor formed on a semiconductor substrate and having a first through hole formed on the semiconductor substrate and covering a gate electrode of the MOS transistor, the first through hole exposing the gate electrode; An interlayer insulating layer, a first conductor plug formed inside the first through hole and in contact with the gate electrode, and spaced apart from a top of the first conductor plug on the first interlayer insulating layer A first wiring layer formed; a part of the first wiring layer formed on the first interlayer insulating layer and covering the first wiring layer;
A second interlayer insulating layer having a second through hole exposing each of the conductor plugs; and a second interlayer insulating layer formed inside the second through hole and in contact with the first wiring layer and the first conductor plug, respectively. Second
A conductive plug, wherein the first wiring layer is electrically connected to the first conductive plug via the second conductive plug, and thus the first wiring layer is electrically connected to the gate electrode. A semiconductor device characterized by being performed. 2. The second through hole inside the second through hole.
2. The semiconductor device according to claim 1, wherein an insulator plug is further formed on the conductor plug, and a surface of the second conductor plug is insulated by the insulator plug. 3. 3. A first transistor having a MOS transistor formed on a semiconductor substrate and a first through hole formed on the semiconductor substrate and covering a gate electrode of the MOS transistor, the first through hole exposing the gate electrode. An interlayer insulating layer, a first conductor plug formed inside the first through hole and in contact with the gate electrode, and first and second wiring patterns formed on the first interlayer insulating layer A first wiring layer including a first portion and a second wiring pattern portion formed on the first interlayer insulating layer and exposing each of the first and second wiring pattern portions covering the first wiring layer; A second interlayer insulating layer having a through hole; a second conductor plug formed inside the second through hole and in contact with each of the first and second wiring pattern portions; Inside And an insulator plug formed on the second conductor plug, wherein the first wiring pattern portion having a surface having a smaller area than the second wiring pattern portion is in contact with the first conductor plug. The second wiring pattern portion is electrically connected to the first wiring pattern portion via the second conductor plug, whereby the second wiring pattern portion is electrically connected to the gate electrode; A semiconductor device, wherein a surface of the second conductor plug is insulated by the insulator plug. 4. A step of forming a MOS transistor on a semiconductor substrate, and forming a first interlayer insulating layer covering a gate electrode of the MOS transistor and having a first through hole reaching the gate electrode on the semiconductor substrate. Forming a first contact hole in contact with the gate electrode inside the first through hole;
Forming a conductor plug, forming a first wiring layer on the first interlayer insulating layer without including a wiring pattern portion in an opening of the first through hole, covering the first wiring layer; Forming a second interlayer insulating layer having a second through hole reaching each of the first wiring layer and the first conductor plug on the first interlayer insulating layer; The first wiring layer and the first
Forming a second conductor plug in contact with each of the conductor plugs, wherein the step of forming the second conductor plug includes the step of forming the first wiring layer through the first conductor plug through the first wiring layer. 1. A method of manufacturing a semiconductor device, wherein the method is electrically connected to one conductor plug, and the first wiring layer is electrically connected to the gate electrode. 5. The second through hole inside the second through hole.
The method according to claim 4, further comprising forming an insulator plug on the conductor plug, wherein a surface of the second conductor plug is insulated by the insulator plug. 6. The step of forming the second conductor plug includes forming the first conductor plug so as to cover the inside of the second through hole.
Forming a conductor layer on an interlayer insulating layer; and etching back the conductor layer to leave the second conductor plug inside the second through hole. Forming the second
6. The method of manufacturing a semiconductor device according to claim 5, wherein a recess is formed on the conductor layer inside the through hole. 7. A step of forming a MOS transistor on a semiconductor substrate, and a first interlayer insulating layer covering a gate electrode of the MOS transistor and having a first through hole reaching the gate electrode is formed on the semiconductor substrate. Forming a first contact hole in contact with the gate electrode inside the first through hole;
Forming a conductor plug; forming a first wiring layer including first and second wiring pattern portions on the first interlayer insulating layer; and covering the first wiring layer. Forming a second interlayer insulating layer having a second through hole reaching each of the first and second wiring pattern portions on the first interlayer insulating layer; and forming the first interlayer insulating layer inside the second through hole. Forming a second conductor plug in contact with each of the second wiring pattern portions, and forming an insulator plug on the second conductor plug inside the second through hole, In the step of forming the first wiring layer, the first wiring pattern portion having a surface with a smaller area than the second wiring pattern portion is formed in contact with the first conductor plug, and the second conductor plug is formed. Form In extent, the second wiring pattern portion is electrically connected to the first wiring pattern portion through the second conductive plugs, with,
The semiconductor device, wherein the second wiring pattern portion is electrically connected to the gate electrode, and in the step of forming the insulator plug, a surface of the second conductor plug is insulated by the insulator plug. Device manufacturing method. 8. The step of forming the second conductor plug includes forming the first conductor plug so as to cover the inside of the second through hole.
Forming a conductor layer on an interlayer insulating layer; and etching back the conductor layer to leave the second conductor plug inside the second through hole. Forming the second
The method of manufacturing a semiconductor device according to claim 6, wherein a concave portion is formed on the conductor layer inside the through hole.