CN116190318A

CN116190318A - Method for manufacturing semiconductor structure and semiconductor structure

Info

Publication number: CN116190318A
Application number: CN202210205194.3A
Authority: CN
Inventors: 罗杰; 平延磊
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-03-02
Filing date: 2022-03-02
Publication date: 2023-05-30

Abstract

The disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure, wherein the method for manufacturing the semiconductor structure comprises the following steps: forming a substrate, wherein the substrate comprises an active region and at least one gate structure group, each gate structure group comprises a plurality of spaced gate structures, each gate structure comprises a gate and a first gate dielectric layer covering the side surface of the gate, and a channel region of the active region covers at least part of the side surface of each gate structure in the gate structure group; and forming a source electrode and a drain electrode on the substrate, wherein the source electrode is in contact with a source region of the active region, and the drain electrode is in contact with a drain region of the active region. According to the method, the plurality of spaced grid structures are formed on the substrate, the grid electrode of each grid structure is separated from the active region through the first grid dielectric layer, and then the on-off of current between the same group of source electrodes and the same group of drain electrodes can be controlled through the plurality of grid structures, so that contact points are reduced and the integration level is increased on the basis of logic circuits such as AND, OR and the like.

Description

Method for manufacturing semiconductor structure and semiconductor structure

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure.

Background

At present, a semiconductor used for a logic circuit is simple in structure and single in function, so that more semiconductor devices are needed when logic functions such as AND, OR and the like are realized, and more contact points are needed, so that the manufacturing efficiency of a chip is affected.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a manufacturing method of a semiconductor structure and the semiconductor structure.

In a first aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method for manufacturing a semiconductor structure includes:

forming a substrate comprising an active region and at least one gate structure group, each gate structure group comprising a plurality of spaced gate structures, the gate structures comprising a gate and a first gate dielectric layer covering sides of the gate, a channel region of the active region covering at least a portion of sides of each of the gate structures within the gate structure group;

and forming a source electrode and a drain electrode on the substrate, wherein the source electrode is contacted with a source region of the active region, and the drain electrode is contacted with a drain region of the active region.

In some embodiments, the plurality of gate structures within the group of gate structures are arranged along a first direction, the forming source and drain electrodes on the substrate comprising:

Forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the active region;

removing part of the interlayer dielectric layer in a first area, and forming a first through hole to expose the source region, wherein the first area is positioned at one side of a second direction of the grid electrode structure group, and the second direction is perpendicular to the first direction and parallel to the interlayer dielectric layer;

removing part of the interlayer dielectric layer in a second region, and forming a second through hole to expose the drain region, wherein the second region is positioned at the other side of the grid structure group in the second direction;

and forming the source electrode in the first through hole and the drain electrode in the second through hole to form an OR gate circuit.

removing part of the interlayer dielectric layer in a first area, and forming a first through hole to expose the source region, wherein the first area is positioned at one side of the grid structure group in the first direction;

Removing part of the interlayer dielectric layer in a second region, and forming a second through hole to expose the drain region, wherein the second region is positioned at the other side of the grid structure group in the first direction;

and forming the source electrode in the first through hole and the drain electrode in the second through hole to form an AND gate circuit.

In some embodiments, the forming a substrate comprises:

providing a substrate;

forming a second gate dielectric layer on the substrate;

forming at least one grid structure group on the second grid dielectric layer, wherein a first grid dielectric layer of a grid structure in the grid structure group covers the exposed surface of the second grid dielectric layer;

and forming an active layer on the first gate dielectric layer, wherein the active layer surrounds each gate structure group and fills a spacing space between gate structures in each gate structure group, and the active layer forms the active region.

In some embodiments, the forming at least one gate structure group on the second gate dielectric layer includes:

forming a plurality of spaced grid electrodes on the second grid dielectric layer;

forming a first gate dielectric layer on the second gate dielectric layer for forming the plurality of gates, wherein the first gate dielectric layer also covers the top surface of the gate;

The forming an active layer on the first gate dielectric layer includes:

forming an active material layer on the first gate dielectric layer;

and flattening the active material layer and exposing the top surface of each gate structure, wherein the reserved parts form the active layer.

In some embodiments, the method for manufacturing a semiconductor structure further includes:

removing part of the interlayer dielectric layer and the first gate dielectric layer to form a plurality of third through holes, wherein the third through holes correspond to the gate structures one by one, and the third through holes expose the gates corresponding to the gate structures;

and forming a grid electrode electric connection structure in the third through hole, wherein the grid electrode electric connection structure is contacted with the grid electrode.

In some embodiments, the material of the active layer comprises indium gallium zinc oxide.

In a second aspect of the present disclosure, there is provided a semiconductor structure comprising:

a substrate comprising an active region and at least one gate structure group, each gate structure group comprising a plurality of spaced apart gate structures, the gate structures comprising a gate and a first gate dielectric layer covering sides of the gate, a channel region of the active region covering at least a portion of sides of each of the gate structures within the gate structure group;

The source electrode is arranged on the substrate and is in contact with the source region of the active region;

and the drain electrode is arranged on the substrate and is contacted with the drain region of the active region.

In some embodiments, the plurality of gate structures within the group of gate structures are arranged along a first direction, the semiconductor structure further comprising:

the interlayer dielectric layer is arranged on the substrate and covers the active area;

the first through hole is arranged in a first area of the interlayer dielectric layer, the first area is positioned at one side of the second direction of the grid electrode structure group, the second direction is perpendicular to the first direction and parallel to the interlayer dielectric layer, and the first through hole exposes the source region;

the second through hole is arranged in a second area of the interlayer dielectric layer, the second area is positioned at the other side of the second direction of the grid electrode structure group, and the drain area is exposed by the second through hole;

the source electrode is arranged in the first through hole, and the drain electrode is arranged in the second through hole so as to form an OR gate circuit.

In some embodiments, the gate structure has a dimension in the first direction that is less than a dimension in the second direction.

In some embodiments, the gate structures in one of the gate structure groups include a first gate structure and a second gate structure, the source having a dimension in the first direction that is greater than a distance between the first gate structure and the second gate structure;

the dimension of the drain in the first direction is greater than a distance between the first gate structure and the second gate structure.

the first through hole is arranged in a first area of the interlayer dielectric layer, the first area is positioned at one side of the first direction of the grid electrode structure group, and the source area is exposed by the first through hole;

the second through hole is arranged in a second area of the interlayer dielectric layer, the second area is positioned at the other side of the first direction of the grid electrode structure group, and the drain area is exposed by the second through hole;

the source electrode is arranged in the first through hole, and the drain electrode is arranged in the second through hole to form an AND gate circuit.

In some embodiments, the gate structure has a dimension in the first direction that is greater than a dimension in a second direction that is perpendicular to the first direction and parallel to the interlayer dielectric layer.

In some embodiments, the gate structures in one of the gate structure groups include a first gate structure and a second gate structure, the source electrode having a dimension in a second direction that is greater than a dimension of the first gate structure in the second direction and greater than a dimension of the second gate structure in the second direction, the second direction being perpendicular to the first direction and parallel to the interlayer dielectric layer;

the drain has a dimension in the second direction that is greater than a dimension of the first gate structure in the second direction and greater than a dimension of the second gate structure in the second direction.

In some embodiments, the substrate comprises:

a substrate;

the second gate dielectric layer is arranged on the substrate;

the at least one gate structure group is arranged on the second gate dielectric layer, and a first gate dielectric layer of a gate structure in the gate structure group covers the exposed surface of the second gate dielectric layer;

The first gate dielectric layer is provided with an active layer, the active layer surrounds each gate structure group and fills the interval space between the gate structures in each gate structure group, and the active layer forms the active region.

In some embodiments, the semiconductor structure further includes a plurality of third through holes, the third through holes are in one-to-one correspondence with the plurality of gate structures, the third through holes penetrate through the interlayer dielectric layer and the first gate dielectric layer to expose gates corresponding to the gate structures, and a gate electrical connection structure is disposed in the third through holes and is in contact with the gates.

In the manufacturing method of the semiconductor structure and the semiconductor structure provided by the embodiment of the disclosure, the grid electrode of each grid electrode structure is separated from the active region through the first grid dielectric layer by forming the plurality of spaced grid electrode structures on the substrate, so that the on and off of current between the same group of source electrodes and drain electrodes can be controlled through the plurality of grid electrode structures, contact points are reduced on the basis of logic circuits such as AND, OR and the like, and the integration level is increased.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

Fig. 2 is a schematic diagram of a related art or gate circuit.

Fig. 3 is a schematic diagram of the connection of the semiconductor structure in the or circuit shown in fig. 2.

Fig. 4 is a schematic diagram of an and circuit in the related art.

Fig. 5 is a schematic diagram showing the connection of the semiconductor structure in the and circuit shown in fig. 4.

Fig. 6 is a schematic diagram of a semiconductor structure after forming a substrate, a second gate dielectric layer, and a gate electrode in a method for fabricating the semiconductor structure according to an exemplary embodiment.

Fig. 7 is a schematic diagram of a method for fabricating a semiconductor structure according to an exemplary embodiment after forming a first gate dielectric layer.

FIG. 8 is a schematic cross-sectional view at A-A of FIG. 7.

Fig. 9 is a schematic diagram illustrating a method for fabricating a semiconductor structure after forming an active material layer according to an exemplary embodiment.

Fig. 10 is a schematic cross-sectional view at B-B in fig. 9.

Fig. 11 is a schematic diagram illustrating a method for fabricating a semiconductor structure after forming an active layer according to an exemplary embodiment.

FIG. 12 is a schematic cross-sectional view at C-C of FIG. 11.

Fig. 13 is a schematic diagram illustrating a method for fabricating a semiconductor structure after forming an interlayer dielectric layer according to an exemplary embodiment.

FIG. 14 is a schematic cross-sectional view taken at D-D of FIG. 13.

Fig. 15 is a schematic view of a method for manufacturing a semiconductor structure according to an exemplary embodiment after forming a first via hole, a second via hole, and a third via hole.

FIG. 16 is a schematic cross-sectional view taken at E-E of FIG. 15.

Fig. 17 is a schematic diagram of a semiconductor structure after forming a substrate, a second gate dielectric layer, and a gate in a method for fabricating the semiconductor structure according to an exemplary embodiment.

Fig. 18 is a schematic diagram illustrating formation of a first gate dielectric layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

FIG. 19 is a schematic cross-sectional view at F-F in FIG. 18.

Fig. 20 is a schematic view of an active material layer formed in a method of fabricating a semiconductor structure according to an exemplary embodiment.

FIG. 21 is a schematic cross-sectional view at G-G of FIG. 20.

Fig. 22 is a schematic diagram illustrating formation of an active layer in a method of fabricating a semiconductor structure according to an exemplary embodiment.

FIG. 23 is a schematic cross-sectional view at H-H of FIG. 22.

Fig. 24 is a schematic diagram illustrating formation of an interlayer dielectric layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

FIG. 25 is a schematic cross-sectional view at I-I of FIG. 24.

Fig. 26 is a schematic view of a method for manufacturing a semiconductor structure according to an exemplary embodiment after forming a first via hole, a second via hole, and a third via hole.

FIG. 27 is a schematic cross-sectional view at J-J of FIG. 26.

Reference numerals:

a substrate-1;

a substrate-11;

a second gate dielectric layer-12;

a gate structure-13; a gate electrode 131; a first gate dielectric layer-132;

an active layer-14; a channel region-141; source region-142; a drain region-143; active material layer-14';

interlayer dielectric layer-15;

a first through hole-16;

a second through hole-17;

a third through hole-18; a first segment-181; a second section-182;

MOS tubes-2, 3, 4, 5;

input terminal-A, B;

an output terminal-C;

low potential-Vss.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

In the related art, a semiconductor structure with logic functions of AND, OR and the like consists of a plurality of MOS tubes, and the connection points are too many. In one example, fig. 2 shows an or gate circuit, fig. 3 shows a connection state of a semiconductor structure in the or gate circuit of fig. 2, wherein a circuit of controlling connection of a high-potential MOS transistor by an input terminal a and an input terminal B is omitted in fig. 2, and the MOS transistor 2 and the MOS transistor 3 form a semiconductor structure with an or logic function in fig. 3.

As can be seen from fig. 2, the MOS transistor 2 and the MOS transistor 3 are connected in parallel and the parallel ends are commonly connected to the low potential Vss, wherein the input end a is electrically connected to the gate of the MOS transistor 3, for example, when the input end a is at a high voltage, the MOS transistor 3 is turned on, so that the output end C is connected to the low potential Vss, and the or circuit outputs the low voltage, and the principles of the input end B and the MOS transistor 3 are the same as those of the input end a and the MOS transistor 2, which is not described herein again. It will be appreciated that when either of the input terminals a and B is at a high voltage, the output terminal C is capable of communicating with the low potential Vss to output a low voltage, thereby implementing an or logic function.

Referring to fig. 3, it can be seen that the semiconductor structure formed by the MOS transistor 2 and the MOS transistor 3 has five connection points, specifically, taking the direction shown in fig. 3 as an example, the five connection points are sequentially from left to right: a source connected to the output terminal C, a gate connected to the input terminal A, a drain connected to the low potential Vss, a gate connected to the input terminal B, and a source connected to the output terminal C, it is apparent that the semiconductor structure is not highly integrated

In another example, fig. 4 shows an and circuit, fig. 5 shows a connection state of a semiconductor structure in the and circuit of fig. 4, wherein a circuit of controlling and connecting a high-potential MOS transistor by an input terminal a and an input terminal B is omitted in fig. 4, and the MOS transistor 4 and the MOS transistor 5 form a semiconductor structure having an and logic function in fig. 5.

As can be seen from fig. 4, the MOS transistor 4 and the MOS transistor 5 are connected in series, one end is connected to the low potential Vss, the other end is connected to the output terminal C, for example, when the input terminal a is high voltage and the input terminal B is low voltage, the MOS transistor 4 is turned on but the MOS transistor 5 is not turned on, so that the output terminal C is in an off state with the low potential Vss, and similarly, when the input terminal a is low voltage and the input terminal B is high voltage, the output terminal C is in an off state with the low potential Vss, wherein when the input terminal a and the input terminal B are both high voltage, the MOS transistor 4 and the MOS transistor 5 are both turned on, so that the output terminal C is communicated with the low potential Vss, and the output terminal C outputs the low voltage, thereby realizing the and logic function.

Referring to fig. 5, it can be seen that the semiconductor structure formed by the MOS transistor 4 and the MOS transistor 5 has five connection points, specifically, taking the direction shown in fig. 5 as an example, the five connection points are sequentially from left to right: the integration of the semiconductor structure is not high, as is evident from the drain connected to the low potential Vss, the gate connected to the input terminal a, the connection point of the MOS transistor 4 and the MOS transistor 5, the gate connected to the input terminal B, and the source connected to the output terminal C.

In order to solve the problems in the related art, the manufacturing method provided by the present disclosure forms a plurality of gate structures, and forms a source region and a drain region in different regions of an active region, so that the source region, the drain region and the plurality of gate structures have different arrangements, thereby realizing logic functions such as "and", "or".

In an exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure is provided, fig. 1 illustrates a flowchart of the method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, fig. 6 to 27 are schematic views of respective stages of a method for forming a semiconductor structure, wherein fig. 6 to 16 are a process for forming a semiconductor structure illustrated in an exemplary embodiment, fig. 17 to 27 are a process for forming a semiconductor structure illustrated in another exemplary embodiment, and the method for fabricating a semiconductor structure is described below in connection with fig. 6 to 27.

As shown in fig. 1, a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure includes the following steps:

step S100: a substrate is formed, the substrate including an active region and at least one gate structure group, each gate structure group including a plurality of spaced gate structures, the gate structures including a gate and a first gate dielectric layer covering sides of the gate, a channel region of the active region covering at least a portion of sides of each gate structure within the gate structure group.

Specifically, as shown in fig. 7, 8, 18 and 19, the base 1 includes a substrate 11, an active region and at least one gate structure group, wherein the active region and the gate structure group are formed on the substrate 11. The material of the substrate 11 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. In the present embodiment, a substrate 11 is formedThe material of the active layer 14 may be, for example, indium gallium zinc oxide (indium gallium zinc oxide, IGZO) and the active layer 14 forms the active region, and in other embodiments, the material of the active layer 14 may be ZnO _x 、InO _x 、In ₂ O ₃ 、SnO ₂ 、TiO _x 、Zn _x O _y N _z 、Mg _x Zn _y O _z 、In _x Zn _y O _z 、In _x Ga _y Zn _z O _a 、Zr _x In _y Zn _z O _a 、Hf _x In _y Zn _z O _a 、Sn _x In _y Zn _z O _a 、Al _x Sn _y In _z Zn _a O _d 、Si _x In _y Zn _z O _a 、Zn _x Sn _y O _z 、Al _x Zn _y Sn _z O _a 、Ga _x Zn _y Sn _z O _a 、Zr _x Zn _y Sn _z O _a InGaSiO, and the like. In this embodiment, a second gate dielectric layer 12 is required between the active layer 14 and the substrate 11, the second gate dielectric layer 12 forming an isolation between the active layer 14 and the substrate 11. The material of the second gate dielectric layer 12 may be hafnium oxide (HfO ₂ ) Alumina (Al) ₂ O ₃ ) Silicon dioxide (SiO) ₂ ) The second gate dielectric layer 12 may be one layer or may be multiple layers, and when the second gate dielectric layer 12 is multiple layers, the materials of the second gate dielectric layers 12 may be the same or different.

In other embodiments, the substrate 11 is doped with a certain impurity ion, which may be an N-type impurity ion or a P-type impurity ion, as needed, and the doping includes well region doping and source and drain region doping, for example.

As shown in fig. 7, 8, 18 and 19, the gate structure group formed on the substrate 11 includes a plurality of spaced gate structures 13, the plurality of gate structures 13 being arranged in a first direction (X direction shown in fig. 15), the gate structures 13 including a gate 131 and a first gate dielectric layer 132 covering sides of the gate 131. The material of the gate 131 may be at least one of tungsten (W), copper (Cu), gold (Au), and silver (Ag), and the materials of the first gate dielectric layer 132 and the second gate dielectric layer 12 may be the same, for example, the gate 131 and the first gate dielectric layer 132 may be sequentially formed on the substrate 11 through deposition processes such as an atomic layer deposition process (Atomic layer deposition, abbreviated as ALD), a vapor deposition process (Chemical Vapor Deposition, abbreviated as CVD), and the like, so as to form a plurality of spaced gate structures 13.

As shown in fig. 15, 16, 26 and 27, the active layer 14 between the plurality of gate structures 13 forms a channel region 141, and the active layer 14 at both sides of the channel region 141 forms a source region 142 and a drain region 143, respectively.

Step S200: and forming a source electrode and a drain electrode on the substrate, wherein the source electrode is in contact with a source region of the active region, and the drain electrode is in contact with a drain region of the active region.

Illustratively, the forming the source and the drain on the substrate in step S200 in the above embodiment includes the following steps:

step S210: and forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the active region.

As shown in fig. 13, 14, 24 and 25, an interlayer dielectric layer 15 is formed on the substrate 1, and the interlayer dielectric layer 15 covers the active region. The interlayer dielectric layer 15 may be formed by an atomic layer deposition process (Atomic layer deposition, abbreviated as ALD), a vapor deposition process (Chemical Vapor Deposition, abbreviated as CVD), and the like, and the material of the interlayer dielectric layer 15 may be the same as the material of the first gate dielectric layer 132 and the second gate dielectric layer 12.

Step S220: and removing part of the interlayer dielectric layer of the first region, forming a first through hole to expose the source region, and removing part of the interlayer dielectric layer of the second region to form a second through hole to expose the drain region.

As shown in fig. 15, 16, 26 and 27, after the interlayer dielectric layer 15 is formed, the first via hole 16 and the second via hole 17 penetrating through the interlayer dielectric layer 15 are formed by photolithography (Litho), etching (etc.), that is, the source region 142 and the drain region 143 can be exposed through one process, and the process is simpler.

As an example, as shown in fig. 16, a hard mask (not shown) is disposed over the interlayer dielectric layer 15, a hollowed pattern is disposed on the hard mask, and the hollowed pattern is transferred into the interlayer dielectric layer 15 by etching, thereby forming a through first via hole 16 and a through second via hole 17 in the interlayer dielectric layer 15, such that the first via hole 16 exposes the source region 142, the second via hole 17 exposes the drain region 143 for subsequent formation of a source electrode (not shown) in contact with the source region 142, and formation of a drain electrode (not shown) in contact with the drain region 143. In another embodiment, a patterned photoresist layer may be formed on the interlayer dielectric layer 15, and the pattern in the patterned photoresist layer is transferred into the interlayer dielectric layer 15 by dry etching to form the first via hole 16 and the second via hole 17. The material of the hard mask and photoresist layer may be silicon dioxide (SiO ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), and the like. After the first through hole 16 and the second through hole 17 are formed by etching, an ashing process (asher) is adopted to remove the mask, and impurities in the first through hole 16 and the second through hole 17 are removed by wet cleaning, so that good interface performance and process foundation are provided for the subsequent process, and the quality of the formed semiconductor structure is improved.

Step S230: a source is formed in the first via and a drain is formed in the second via.

Specifically, the source electrode may be a layer, for example, a metal layer filled in the first through hole 16, and a material of the metal layer may be at least one of tungsten (W), copper (Cu), gold (Au), and silver (Ag), for example. The source electrode may be formed in the first via hole 16 by deposition processes such as an atomic layer deposition process (Atomic layer deposition, ALD for short), a vapor deposition process (Chemical Vapor Deposition, CVD for short), and the like. It is understood that the implementation of the drain and the source may be the same, except that the drain is formed in the second through hole 17, which is not described herein.

The technical solutions of the present disclosure will be explained with two embodiments respectively, one exemplary embodiment is for fabricating a semiconductor structure forming an or gate circuit, which includes step S221 and step S231, and another exemplary embodiment is for forming a semiconductor structure of an and gate circuit, which includes step S222 and step S232.

In one exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure forming an or gate circuit specifically includes the steps of:

step S221: removing part of the interlayer dielectric layer of the first region, and forming a first through hole to expose the source region, wherein the first region is positioned at one side of the second direction of the grid electrode structure group, and the second direction is perpendicular to the first direction and parallel to the interlayer dielectric layer; and removing part of the interlayer dielectric layer of the second region, and forming a second through hole to expose the drain region, wherein the second region is positioned at one side of the grid electrode structure group in the second direction.

Referring to fig. 15 and 16, the plurality of gate structures 13 within the gate structure group are arranged in a first direction (X direction shown in fig. 15), a second direction (Y direction shown in fig. 15) is perpendicular to the first direction and parallel to the interlayer dielectric layer 15, and a first region of the interlayer dielectric layer 15 is etched at one side of the second direction of the gate structure group to form a first via hole 16 exposing the source region 142 of the active region. A second region of the interlayer dielectric layer 15 is etched at the other side of the second direction of the gate structure group, and a second via hole 17 is formed to expose the drain region 143 of the active region.

Step S231: a source is formed in the first via and a drain is formed in the second via to form an OR gate.

In this embodiment, referring to fig. 15 and 16, when the plurality of gate structures 13 of the gate structure group are arranged along the first direction (X direction shown in fig. 15), a source is formed on one side of the second direction (Y direction shown in fig. 15) of the gate structure group, and a drain is formed on the other side of the second direction of the gate structure group, that is, the plurality of gate structures 13 are disposed between the source and the drain in a "parallel" manner, so that a preset voltage is applied to any one of the gate structures 13 in the gate structure group, and current conduction between the source and the drain can be achieved, that is, the semiconductor structure manufactured by the manufacturing method provided in this embodiment forms the or gate, so that contact points can be reduced, and integration level can be improved.

In another exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure forming an and gate circuit specifically includes the steps of:

step S222: removing part of the interlayer dielectric layer of the first region, forming a first through hole to expose the source region, wherein the first region is positioned at one side of the grid electrode structure group in the first direction; and removing part of the interlayer dielectric layer of the second region, and forming a second through hole to expose the drain region, wherein the second region is positioned at the other side of the grid electrode structure group in the first direction.

Referring to fig. 26 and 27, a plurality of gate structures 13 within a gate structure group are arranged in a first direction (X direction shown in fig. 26), and a first region of an interlayer dielectric layer 15 is etched at one side of the first direction of the gate structure group to form a first via hole 16 exposing a source region 142 of an active region. On the other side of the gate structure group in the first direction, a second region of the interlayer dielectric layer 15 may be formed, and a second via hole 17 is formed to expose the drain region 143 of the active region.

Step S232: a source is formed in the first via and a drain is formed in the second via to form an AND gate.

In this embodiment, referring to fig. 26 and 27, when the plurality of gate structures 13 of the gate structure group are arranged along the first direction (X direction shown in fig. 26), a source is formed on one side of the first direction of the gate structure group, and a drain is formed on the other side of the first direction of the gate structure group, so that a plurality of gates are disposed between the source and the drain, that is, the source, the drain and the plurality of gates are arranged in a line, so that a preset voltage needs to be applied to all the gate structures 13 of the gate structure group, and then current conduction between the source and the drain can be achieved.

In summary, in the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure, by forming a plurality of gate structures 13 at intervals on the substrate 1, the gate of each gate structure 13 is separated from the active region by the first gate dielectric layer 132, so that the current between the same group of sources and drains can be controlled to be turned on and off by the plurality of gate structures 13, so that on the basis of logic circuits such as "and", "or", etc., contact points are reduced, and the integration level is improved.

Further, the method for manufacturing the semiconductor structure provided by the embodiment of the disclosure further includes:

step S300: and removing part of the interlayer dielectric layer and the first gate dielectric layer to form a plurality of third through holes, wherein the third through holes correspond to the gate structures one by one, and the third through holes expose the gates of the corresponding gate structures.

As an example, as shown in fig. 15 and 16, a hard mask is disposed over the interlayer dielectric layer 15, a hollowed pattern is disposed on the hard mask, and the hollowed pattern is transferred into the interlayer dielectric layer 15 and the first gate dielectric layer 132 by etching, so that a through third via hole 18 is formed in the interlayer dielectric layer and the first gate dielectric layer 132, wherein the third via hole 18 includes a first section 181 penetrating the interlayer dielectric layer 15 and a second section 182 penetrating the first gate dielectric layer 132, and thus the third via hole 18 exposes the gate 131 for subsequent formation of a gate electrical connection structure (not shown) contacting the gate 131. In another embodiment, a photoresist layer may be patterned on the interlayer dielectric layer 15, and the patterns in the patterned photoresist layer may be transferred into the interlayer dielectric layer 15 and the first gate dielectric layer 132 by dry etching to form the plurality of third vias 18. The material of the hard mask and photoresist layer may be silicon dioxide (SiO ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), and the like. After the plurality of third through holes 18 are etched, an ashing process (asher) is used to remove the mask, and impurities in the third through holes 18 are removed by wet cleaning, so that good interface performance and process basis are provided for subsequent processes, and the quality of the formed semiconductor structure is improved.

Step S400: and forming a grid electrode electric connection structure in the third through hole, wherein the grid electrode electric connection structure is contacted with the grid electrode.

Specifically, the gate electrical connection structure may be a layer, for example, a metal layer filled in the third via hole 18, and the material of the metal layer may be at least one of tungsten, copper, gold, and silver, for example. The gate electrical connection structure may be formed in the third via 18 by deposition processes such as an atomic layer deposition process (Atomic layer deposition, ALD for short), a vapor deposition process (Chemical Vapor Deposition, CVD for short), and the like.

It will be appreciated that the process is simpler by adjusting the patterns on the hard mask and the photoresist, that is, forming the first via hole 16, the second via hole 17 and the plurality of third via holes 18 simultaneously, that is, exposing the source region 142, the drain region 143 and the gate electrode 131 in one process.

In an exemplary embodiment of the present disclosure, the forming of the substrate in step S100 specifically includes the steps of:

step S110: a substrate is provided.

As shown in fig. 5, the material of the substrate 11 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide.

Step S120: and forming a second gate dielectric layer on the substrate.

As shown in fig. 5, a second gate dielectric layer 12 may be formed on the upper surface of the substrate 11 by a deposition process, and the second gate dielectric layer 12 completely covers the substrate 11. Wherein the material of the second gate dielectric layer 12 may be hafnium oxide (HfO ₂ ) Alumina (Al) ₂ O ₃ ) Silicon dioxide (SiO) ₂ ) At least one of them. The second gate dielectric layer 12 may be one layer or multiple layers, and when the second gate dielectric layer 12 is multiple layers, the materials of the second gate dielectric layers 12 may be the same or different.

Step S130: and forming at least one grid electrode structure group on the second grid electrode dielectric layer, wherein the first grid electrode dielectric layer of the grid electrode structure in the grid electrode structure group covers the surface of the second grid electrode dielectric layer.

As shown in fig. 6 to 8, the forming of at least one gate structure on the second dielectric layer in step S130 specifically includes the following steps:

Step S131: and forming a plurality of spaced grid electrodes on the second grid dielectric layer.

As shown in fig. 6 and 17, a plurality of gates are formed at a plurality of preset positions spaced apart from the upper surface of the second gate dielectric layer 12, and each gate 131 extends upward in the thickness direction (Z direction shown in fig. 15) of the substrate 11, wherein the gate 131 may be formed by a deposition process. The material of the gate electrode may be at least one of tungsten (W), copper (Cu), gold (Au), and silver (Ag).

Step S132: and forming a first gate dielectric layer on the second gate dielectric layer for forming the plurality of gates, wherein the first gate dielectric layer also covers the top surface of the gates.

In this embodiment, as shown in fig. 7 and 8, the first gate dielectric layer 132 covers the exposed surface of the second gate dielectric layer 12, that is, the first gate dielectric layer 132 is used to isolate the substrate 11 from the source region 142 and the drain region 143 of the active region, and in this embodiment, the first gate dielectric layer 132 may also cover the top surface of the gate 131.

In other embodiments, the first gate dielectric layer 132 is formed around the gate 131, i.e., the first gate dielectric layer 132 is formed only on the side of the gate 131 to cover at least the side of the gate 131, it is understood that the first gate dielectric layer 132 is used to separate the gate 131 from the active region, so long as the side of the gate 131 can be covered to separate the active region from the gate 131.

Step S140: and forming an active layer on the first gate dielectric layer, wherein the active layer surrounds each gate structure group and fills the interval space between the gate structures in each gate structure group, and the active layer forms an active region.

As shown in fig. 9 to 12, the active layer 14 may be formed by a deposition process, the active layer 14 surrounding each gate structure group and filling a space between the gate structures 13 within each gate structure group, the active layer 14 forming an active region, wherein the active region includes a channel region 141 in the gate structure 13, and source and drain regions 143 on both sides of the channel region 141.

Illustratively, the forming the active layer 14 on the first gate dielectric layer 132 in the step S140 in the above embodiment specifically includes the following steps:

step S141: and forming an active material layer on the first gate dielectric layer.

As shown in fig. 9 and 10, after forming the gate structure 13, an active material layer 14 'is formed on the substrate 11, the active material layer 14' being used to form the active layer 14. The active material layer 14' may be formed by a deposition process such as an atomic layer deposition process (Atomic layer deposition, ALD for short), a vapor deposition process (Chemical Vapor Deposition, CVD for short), or the like.

Step S142: the active material layer is planarized and the top surface of each gate structure is exposed, and the remaining portions constitute the active layer.

Wherein, referring to fig. 9 and 10, the active material layer 14' is formed to exceed the gate structure 13 in the thickness direction of the substrate 11, the flatness of the upper layer structure is ensured by planarizing the active material layer 14', and in addition, the top surface of the gate structure 13 is exposed by the step of planarizing the active material layer 14', so that the gate structure 13 is in contact with the gate electrical connection structure for conduction. Illustratively, the active material layer 14 'is planarized by chemical mechanical polishing (Chemical Mechanical Polishing, abbreviated as CMP), and referring to fig. 11 and 12, a remaining portion of the active material layer 14' forms the active layer 14, wherein the active layer 14 between the plurality of gate structures 13 forms a channel region 141, and the active layer 14 at both sides of the channel region 141 forms a source region 142 and a drain region 143, respectively.

Embodiments of the present disclosure also provide a semiconductor structure including a substrate, a source, and a drain.

As shown in fig. 15, 16, 26 and 27, the substrate 1 includes an active region and at least one gate structure group, each gate structure group includes a plurality of spaced gate structures 13, the gate structures 13 include gates 131 and a first gate dielectric layer 132 covering sides of the gates 131, and a channel region 141 of the active region covers at least part of sides of each gate structure 13 in the gate structure group. Wherein a source (not shown) is disposed on the substrate 1, the source is in contact with the source region 142 of the active region, a drain is disposed on the substrate 1, and the drain is in contact with the drain region 143 of the active region. The material of the substrate 11 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. In this embodiment, the active layer 14 is formed on the substrate 11, and the material of the active layer 14 may be, for example, indium gallium zinc oxide (indium gallium zinc oxide, IGZO) formed from the active layer 14 forms the active region, in other embodiments, the material of the active layer 14 may be ZnO _x 、InO _x 、In ₂ O ₃ 、SnO ₂ 、TiO _x 、Zn _x O _y N _z 、Mg _x Zn _y O _z 、In _x Zn _y O _z 、In _x Ga _y Zn _z O _a 、Zr _x In _y Zn _z O _a 、Hf _x In _y Zn _z O _a 、Sn _x In _y Zn _z O _a 、Al _x Sn _y In _z Zn _a O _d 、Si _x In _y Zn _z O _a 、Zn _x Sn _y O _z 、Al _x Zn _y Sn _z O _a 、Ga _x Zn _y Sn _z O _a 、Zr _x Zn _y Sn _z O _a InGaSiO, and the like. In this embodiment, a second gate dielectric layer 12 is required between the active layer 14 and the substrate 11, the second gate dielectric layer 12 forming an isolation between the active layer 14 and the substrate 11. The material of the second gate dielectric layer 12 may be hafnium oxide (HfO ₂ ) Alumina (Al) ₂ O ₃ ) Silicon dioxide (SiO) ₂ ) The second gate dielectric layer 12 may be one layer or may be multiple layers, and when the second gate dielectric layer 12 is multiple layers, the materials of the second gate dielectric layers 12 may be the same or different.

In other embodiments, the substrate 11 is doped with a certain impurity ion, which may be an N-type impurity ion or a P-type impurity ion, as required. In some embodiments, doping includes well region doping and source and drain region doping.

As shown in fig. 15 and 16, the gate structure group includes a plurality of spaced gate structures 13, and the plurality of gate structures 13 are arranged along a first direction (X direction shown in fig. 15), and the gate structures 13 include a gate 131 and a first gate dielectric layer 132 covering at least sides of the gate 131. Wherein the material of the gate electrode 131 may be at least one of tungsten (W), copper (Cu), gold (Au), and silver (Ag), and the material of the first gate dielectric layer 132 Can be hafnium oxide (HfO ₂ ) Alumina (Al) ₂ O ₃ ) Silicon dioxide (SiO) ₂ ) At least one of them.

In this embodiment, a plurality of spaced gate structures 13 are formed on the substrate 1, and the gate 131 of each gate structure 13 is separated from the active region by the first gate dielectric layer 132, so that the on/off of the current between the same set of source and drain can be controlled by the plurality of gate structures 13, so that on the basis of an and or logic circuit, contact points are reduced, and integration is increased.

Further, as shown in fig. 16 and 27, schematic views of two semiconductor structures are shown, respectively, to explain the aspects of the present disclosure.

In one exemplary embodiment, as shown in fig. 15 and 16, fig. 15 and 16 illustrate a semiconductor structure forming an or gate circuit, the semiconductor structure further including an interlayer dielectric layer 15, a first via 16, and a second via 17. Referring to fig. 16, an interlayer dielectric layer 15 is formed on the upper surface of the substrate 1 and covers the active region, a first via hole 16 is disposed in a first region of the interlayer dielectric layer 15, the first region is located at one side of a second direction (Y direction shown in fig. 15) of the gate structure group, the second direction is perpendicular to the first direction and parallel to the interlayer dielectric layer 15, and the first via hole 16 exposes the source region 142. The second through hole 17 is disposed in a second region of the interlayer dielectric layer 15, the second region is located at the other side of the second direction of the gate structure group, and the second through hole 17 exposes the drain region 143. A source (not shown) is disposed in the first via 16 and a drain (not shown) is disposed in the second via 17 to form an or gate.

With reference to fig. 15 and 16, the plurality of gate structures 13 are arranged along the first direction (X direction shown in fig. 15), and the source region 142 and the drain region 143 are arranged along the second direction (Y direction shown in fig. 15), so that when a predetermined voltage is applied to any one of the gate structures 13, both the source region 142 and the drain region 143 can be turned on, that is, an or gate circuit is realized. The semiconductor structure provided in this embodiment is only provided with 4 connection points, and the 4 connection points include a source electrode, a drain electrode and two gate electrode electrical connection structures, so that the connection points are reduced, and the integration level is increased.

In some embodiments, as shown in fig. 15 and 16, the gate structure 13 has a smaller dimension in the first direction (X direction shown in fig. 15) than in the second direction (Y direction shown in fig. 15) in order to conduct the source and drain.

In some embodiments, as shown in fig. 15 and 16, the gate structures 13 in one gate structure group include a first gate structure and a second gate structure, and a dimension of the source electrode in a first direction (X direction shown in fig. 15) is greater than a dimension of the drain electrode in the first direction than a dimension of the distance between the first gate structure and the second gate structure is greater than a distance between the first gate structure and the second gate structure so as to conduct the source electrode and the drain electrode.

It should be noted that, in the above two embodiments, the limitation of the semiconductor structure may be set independently or simultaneously, so as to further improve the conduction degree between the source and the drain.

In another exemplary embodiment, referring to fig. 26 and 27, a semiconductor structure forming an and gate circuit is shown, wherein referring to fig. 27, an interlayer dielectric layer 15 is disposed on an upper surface of a substrate 1 and covers an active region, a first via 16 is disposed in a first region of the interlayer dielectric layer 15, the first region is located at one side of a first direction of a gate structure 13, and the first via 16 exposes the source region 142. The second through hole 17 is disposed in a second region of the interlayer dielectric layer 15, the second region is located at the other side of the first direction of the gate structure group, and the second through hole 17 exposes the drain region 143. The source is disposed in the first via 16, and the drain is disposed in the second via 17 to form an and gate.

With reference to fig. 26 and 27, the plurality of gate structures 13 are arranged along the first direction (X direction shown in fig. 26), and the source region and the drain region 143 are also arranged along the first direction, it is understood that when a preset voltage is applied to the plurality of gate structures 13 between the source region 142 and the drain region 143, the active region between the source region and the drain region 143 can be in a conductive state, thereby implementing an and circuit. The semiconductor structure provided in this embodiment is only provided with 4 connection points, and the 4 connection points include a source electrode, a drain electrode and two gate electrode electrical connection structures, so that the connection points are reduced, and the integration level is increased.

In some embodiments, as shown in fig. 26 and 27, the dimension of the gate structure 13 in the first direction (X direction shown in fig. 26) is greater than the dimension in the second direction (Y direction shown in fig. 26) perpendicular to the first direction and parallel to the interlayer dielectric layer 15 in order to conduct the source and drain electrodes.

In some embodiments, as shown in fig. 26 and 27, the gate structures 13 in one gate structure group include a first gate structure and a second gate structure, a dimension of the source electrode in a second direction (Y direction shown in fig. 26) is greater than a dimension of the first gate structure in the second direction and greater than a dimension of the second gate structure in the second direction, the second direction being perpendicular to the first direction (X direction shown in fig. 26) and parallel to the interlayer dielectric layer 15, and a dimension of the drain electrode in the second direction is greater than a dimension of the first gate structure in the second direction and greater than a dimension of the second gate structure in the second direction so as to conduct the source electrode and the drain electrode.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. The manufacturing method of the semiconductor structure is characterized by comprising the following steps of:

2. The method of fabricating a semiconductor structure of claim 1, wherein the plurality of gate structures in the group of gate structures are arranged along a first direction, the forming source and drain electrodes on the substrate comprising:

3. The method of fabricating a semiconductor structure of claim 1, wherein the plurality of gate structures in the group of gate structures are arranged along a first direction, the forming source and drain electrodes on the substrate comprising:

4. A method of fabricating a semiconductor structure according to claim 2 or 3, wherein the forming a substrate comprises:

providing a substrate;

forming a second gate dielectric layer on the substrate;

5. The method of fabricating a semiconductor structure according to claim 4, wherein forming at least one gate structure group on the second gate dielectric layer comprises:

the forming an active layer on the first gate dielectric layer includes:

forming an active material layer on the first gate dielectric layer;

6. The method of fabricating a semiconductor structure of claim 5, further comprising:

7. The method of claim 4, wherein the material of the active layer comprises indium gallium zinc oxide.

8. A semiconductor structure, the semiconductor structure comprising:

9. The semiconductor structure of claim 8, wherein a plurality of gate structures within the group of gate structures are arranged along a first direction, the semiconductor structure further comprising:

10. The semiconductor structure of claim 9, wherein a dimension of the gate structure in the first direction is smaller than a dimension of the gate structure in the second direction.

11. The semiconductor structure of claim 9, wherein the gate structures in one of the gate structure groups comprise a first gate structure and a second gate structure, the source having a dimension in the first direction that is greater than a distance between the first gate structure and the second gate structure;

12. The semiconductor structure of claim 8, wherein a plurality of gate structures within the group of gate structures are arranged along a first direction, the semiconductor structure further comprising:

13. The semiconductor structure of claim 12, wherein a dimension of the gate structure in the first direction is greater than a dimension in a second direction, the second direction being perpendicular to the first direction and parallel to the interlayer dielectric layer.

14. The semiconductor structure of claim 12, wherein the gate structures in one of the gate structure groups comprise a first gate structure and a second gate structure, the source electrode having a dimension in a second direction that is greater than a dimension of the first gate structure in the second direction and greater than a dimension of the second gate structure in the second direction, the second direction being perpendicular to the first direction and parallel to the interlayer dielectric layer;

15. The semiconductor structure of any one of claims 9 to 14, wherein the substrate comprises:

a substrate;

the second gate dielectric layer is arranged on the substrate;

16. The semiconductor structure of claim 15, further comprising a plurality of third vias in one-to-one correspondence with the plurality of gate structures, the third vias penetrating the interlayer dielectric layer and the first gate dielectric layer to expose gates corresponding to the gate structures, gate electrical connection structures disposed within the third vias, the gate electrical connection structures in contact with the gates.