KR20000035224A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a method for producing thereof are provided to preserve the gate oxide from being defected and to prevent the degeneration of the gate oxide during manufacturing. CONSTITUTION: A semiconductor device and a method for producing thereof include a semiconductor board(1), a gate insulator layer(5), a device isolation layer(8), first and second diffusion regions(4a,17a), first and second conduction layers, first and insulator layers, and a first metal lining layer. The semiconductor board(1) includes a semiconductor region(3a) of a first conduction type. The gate insulator layer(5) is formed on a surface of the semiconductor region(3a) of the first conduction type. The device isolation layer(8) is formed on the surface of the semiconductor region(3a) of the first conduction type and defines a device forming region. The first diffusion region(4a) is formed on the surface of the semiconductor region(3a) of the first conduction type, and is of a second conduction type opposite to the first conduction type. The first conduction type behaves like a preservation diode along with the semiconductor region(3a) of the first conduction type.

Description

Semiconductor device and method of manufacturing the same

The present invention relates generally to semiconductor devices having protective diodes. More specifically, the present invention can prevent the damage of the gate oxide film due to the charge applied to the gate electrode by the protection diode, and the degradation of the gate oxide film generated during the manufacture of the semiconductor device can be prevented. And a method for manufacturing the semiconductor device.

In the semiconductor device field, such as a CMOS semiconductor device, in order to avoid damage to the gate oxide film due to charge applied to the gate electrode during the semiconductor device manufacturing process, that is, damage to the gate oxide or damage by plasma, BACKGROUND OF THE INVENTION A semiconductor device having a protection diode that bypasses a semiconductor substrate is known.

11A and 11B illustrate an example of a semiconductor device disclosed in Japanese Patent Laid-Open No. Hei 6-232360. 11A and 11B are sectional views of this semiconductor device along a line different from each other by 90 degrees.

The semiconductor device of FIGS. 11A and 11B includes, for example, a P-type silicon substrate 101 on which a P-type well region 103a and an N-type well region 103b are formed. Further, the diffusion region 120 is formed as a channel stopper in the region adjacent to the P-type well region 103a and the region adjacent to the N-type well region 103b in the P-type silicon substrate 101. On the P-type silicon substrate 101, a field oxide film 102 defining an active region is formed. N-channel MOS transistors and P-channel MOS transistors are formed in the active regions of the P-type well region 103a and the N-type well region 103b, respectively. The N-channel MOS transistor has an N-type diffusion region 117a and a lightly doped drain (LDD) 115a as a source / drain region. The P-channel MOS transistor includes a P-type diffusion region 117b and a lightly doped drain (LDD) 115b as a source / drain region.

A gate oxide film 105 is formed on the channel region between the source region and the drain region, and a polysilicon film 106 is formed on the gate oxide film 105 as a gate electrode. Sidewall spacers 116 such as an oxide film are formed on both sidewall portions of the gate electrode formed of the polysilicon film 106. In addition, an N-type diffusion layer 121 is formed in the P-type silicon substrate 101. The N-type diffusion layer 121 and the P-type silicon substrate 101 serve as protective diodes. The N-type diffusion layer 121 is electrically connected to the polysilicon film 106 which is a gate electrode.

Further, on the P-type silicon substrate 101, a first insulating film 108, a first metal wiring 110, a second insulating film 111, a second metal wiring 113, and a third insulating film 114 are formed. do. The first metal wiring 110 is electrically connected to the polysilicon film 106, the N-type diffusion layer 117a, the P-type diffusion layer 117b, and the like through the first contact hole 109. The second metal wire 113 is electrically connected to the first metal wire 110 through the second contact hole 112.

12A and 12B to 17A and 17B, a conventional semiconductor device having the above-described structure will be described.

First, referring to FIGS. 12A and 12B, a P-type well region 103a and an N-type well region 103b are formed near the surface of the P-type silicon substrate 101, for example, by ion implantation or the like.

Next, in the vicinity of the surface of the P-type silicon substrate 101, phosphorus (P) or the like is doped in the region adjacent to the P-type well region 103a and the region adjacent to the N-type well region 103b, for example, by ion implantation or the like. A plurality of diffusion regions 120 are formed. The diffusion regions 120 serve as channel stoppers.

Next, a field oxide film 102 is formed on each diffusion region 120 by the LOCOS method.

On the surface of the P-type silicon substrate 101, a thin oxide film, that is, a gate oxide film 105, is formed in each element formation region defined by the field oxide film 102, thereby resulting in the structure shown in Figs. 12A and 12B. Is obtained.

13A and 13B, a resist film 122 is applied to the entire surface of the substrate 101, and the resist film 122 is exposed and patterned. Using the patterned photoresist film 122 as a mask, a portion of the gate oxide film 105 on each region 123 on which the protective diode is formed is selectively removed by etching.

Next, as shown in Figs. 14A and 14B, the resist film 122 is removed. When the resist film 122 is removed, the surface of the P-type silicon substrate 101 is exposed in each region 123 in which the protection diode is formed. Next, a polycrystal silicon (polysilicon) film 106 is deposited on the entire surface of the P-type silicon substrate 101.

Phosphorus, an N-type impurity, is implanted onto the polysilicon film 106. This phosphorus diffuses into the polysilicon film 106 and diffuses into the P-type silicon substrate 101 through the polysilicon film 106. As a result, an N-type diffusion layer 121 is formed in the P-type silicon substrate 101, and a protective diode is formed by the N-type diffusion layer 121 and the P-type substrate 101. The polysilicon film 106 is electrically connected to the protection diode, that is, the N-type diffusion layer 121. 14A and 14B show the structure obtained in this process step.

Next, as shown in Figs. 15A and 15B, the polysilicon film 106 is patterned using photolithography and etching to form each gate electrode.

Next, LDDs 115a and 115b are formed by ion implantation or the like. Next, an oxide film is formed on the entire surface of the substrate 101. This oxide film is etched back to form sidewall spacers 116 constituting oxide films on both sides of each gate electrode.

By ion implantation, the source / drain regions 117a are formed in the P-type well region 103a, and the source / drain regions 117b are formed in the N-type well region 103b. Thus, as shown in Figs. 15A and 15B, N-channel MOS transistors P-channel MOS transistors are formed in the P-type well region 103a and the N-type well region 103b, respectively.

Next, as shown in FIGS. 16A and 16B, a first insulating film 108 is formed on the entire surface of the substrate 101.

The first contact hole 109 is formed in the first insulating film 108 using photolithography, plasma etching, or the like. Next, a metal film is formed on the first insulating film 108 so that the first contact hole 109 is filled with the material of the metal film. The metal film is patterned using photolithography and etching to form the first metal wiring 110. The first metal wire 110 is electrically connected to the polysilicon film 106 through the first contact hole 109.

As shown in FIGS. 17A and 17B, the second insulating layer 111 is formed on the entire surface of the substrate 101. In the second insulating film 111, a second contact hole 112 is formed using photolithography and etching. Next, the metal film is formed so that the second contact hole 112 is filled with the material of the metal film. Rapid film is patterned using photolithography and etching to form second metallization 113. The second metal wire 113 is electrically connected to the first metal wire 110 through the second contact hole 112.

Next, a third insulating film 114 is formed on the second insulating film 111 and the second metal wiring 113.

According to the above-described method, it is possible to suppress the damage of the gate oxide film 105 which occurs frequently during the semiconductor device manufacturing process by using the protection diode. However, the above-mentioned conventional semiconductor device and manufacturing method have the following problems.

In other words, in the above-described method, it is required to manufacture a protective diode including the N-type diffusion region 121 in which the resist film 122 is removed after the resist film 122 is applied on the gate oxide film 105. Problems arise due to the process being followed. In the process of removing the resist film 122, for example, due to the contact between the gate oxide film 105 and the resist stripper, and after the removal of the resist film 122, the substrate surface required before deposition of the polysilicon film 106 is removed. The gate oxide film 105 is eroded or thinned by this, and the gate oxide film 105 is contaminated by impurities. Therefore, these processes damage the gate oxide film 105, thereby deteriorating the characteristics and reliability of the gate oxide film, and as a result, the characteristics and reliability of the semiconductor device deteriorate.

Accordingly, an object of the present invention is to eliminate the problems of the above-described conventional semiconductor device and the conventional semiconductor device manufacturing method.

Still another object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, in which damage to the gate oxide film due to charge applied to the gate electrode can be suppressed and deterioration of the gate oxide film generated during semiconductor device manufacturing can be prevented. To provide.

Still another object of the present invention is that damage to the gate oxide film due to the charge applied to the gate electrode can be suppressed and deterioration of the gate oxide film generated during semiconductor device manufacturing can be prevented, whereby a highly reliable gate oxide film The present invention provides a semiconductor device and a method for manufacturing the semiconductor device, which enable to manufacture a semiconductor device and to implement a semiconductor device having high reliability.

1A and 1B illustrate a structure of a CMOS circuit portion of a semiconductor device according to an embodiment of the present invention, respectively, and are schematic cross-sectional views along lines 90 ° different from each other.

2A and 2B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 1A and 1B, respectively, in a state of being in a manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

3A and 3B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 1A and 1B, respectively, in different states during the manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

4A and 4B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 1A and 1B, respectively, in still another state during the manufacturing process, and are schematic cross-sectional views along lines 90 ° different from each other.

5A and 5B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in FIGS. 1A and 1B, respectively, in still another state during the manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

6A and 6B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in FIGS. 1A and 1B, respectively, in still another state during the manufacturing process, and are schematic cross-sectional views taken along lines different from each other by 90 °.

7A and 7B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 1A and 1B, respectively, in still another state during the manufacturing process, and are schematic cross-sectional views along lines 90 ° different from each other.

8A and 8B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 1A and 1B, respectively, in still another state during the manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

9A and 9B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 1A and 1B, respectively, in still another state during the manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

10A and 10B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 1A and 1B, respectively, in still another state during the manufacturing process, and are schematic cross-sectional views along lines 90 ° different from each other.

11A and 11B illustrate the structure of the CMOS circuit portion of the conventional semiconductor device, respectively, and are schematic cross-sectional views along lines 90 ° different from each other.

12A and 12B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 11A and 11B, respectively, in the state of being in the manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

13A and 13B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in FIGS. 11A and 11B, respectively, under different manufacturing processes, and are schematic cross-sectional views taken along lines 90 ° different from each other.

14A and 14B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 11A and 11B, respectively, in a state of yet another manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

15A and 15B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 11A and 11B, respectively, in another manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

16A and 16B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 11A and 11B, respectively, in a state of being in another manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

17A and 17B illustrate the structure of the CMOS circuit portion of the semiconductor device shown in Figs. 11A and 11B, respectively, in a state of being in another manufacturing process, and are schematic cross-sectional views along lines different from each other by 90 °.

※ Explanation of symbols for main parts of drawing

1: P-type silicon substrate 2: Field oxide film

3a: P type well region 3b: N type well region

4a, 17a: N-type diffusion layer 4b, 17b: P-type diffusion layer

5: gate oxide film 6: polysilicon layer

7: tungsten silicide layer 8: first insulating film

9: first contact hole 10: first metal wiring

11 second insulating film 12 second contact hole

13 second metal wiring 14 third insulating film

15a, 15b: LDD 16: Sidewall

20,21: resist film

According to the present invention, the above problem can be eliminated by using a structure in which the gate electrode is formed of a two-layer electrode and the upper layer of the two-layer gate electrode is directly connected with the protection diode. As a result, damage to the gate oxide film due to electric charges applied to the gate electrode can be controlled, and deterioration of the gate oxide film during the manufacturing process of the semiconductor device can also be prevented.

More specifically, according to one aspect of the invention, a semiconductor substrate having a semiconductor region of the first conductivity type, a gate insulating film formed on the surface of the semiconductor region of the first conductivity type, and the An element isolation film formed on the surface of the semiconductor region and defining an element-type? Region, and a second conductivity type formed in the semiconductor region of the first conductivity type and opposite to the first conductivity type, the first conductivity type A first diffusion region serving as a protection diode together with the semiconductor region of the second diffusion region formed in the semiconductor region of the first conductivity type and having the second conductivity type, each of which serves as a source or a drain. Regions and a first conductive layer are formed on at least a portion of the gate insulating film and the second diffusion layer, and a second conductive layer is formed on the first conductive layer and the first diffusion layer. The first conductive layer and the second conductive layer which are formed and electrically connected to the first conductive layer and the first diffusion layer, wherein the first conductive layer and the second conductive layer constitute a gate electrode having a two-layer structure. A layer, a first insulating film formed on the semiconductor substrate, and covering the second conductive film, and formed on the first insulating film and at least one contact hole formed in the first insulating film; A semiconductor device comprising a first metal wiring layer electrically connected to the second diffusion region, and a second insulating film formed on the first insulating film and the first metal wiring layer.

In this case, the region in which the first diffusion region in the semiconductor region of the first conductivity type is formed and the region in which the second diffusion region in the semiconductor region of the second conductivity type are formed are formed by the device isolation film. It is desirable to be isolated.

The first conductive layer may be a polysilicon film doped with impurities, and the second conductive layer may be a tungsten silicide film.

The semiconductor device has sidewall spacers formed on sidewalls of the first and second conductive layers, and is formed in the semiconductor region of the first conductivity type, has the second conductivity type, and serves as an LDD. It is also possible to further include third diffusion regions.

The semiconductor device further includes a first insulating film formed on the first insulating film and the first metal wiring, and at least one contact hole formed on the second insulating film and formed on the second insulating film. It is also possible to further include a second metal wiring layer electrically connected to the metal wiring layer, and a third insulating film formed on the second insulating film and the second metal wiring layer.

According to still another aspect of the present invention, there is provided a semiconductor substrate having a first semiconductor region of a first conductivity type, and an element isolation layer is formed on a surface of the semiconductor region of the first conductivity type to form an element formation region. Defining, forming a gate insulating film on the surface of the semiconductor region of the first conductivity type, forming a first conductive layer on the semiconductor substrate, and forming the first conductive layer and the gate insulating film. Selectively removing a portion of the semiconductor region of the first conductivity type, and exposing the portion of the semiconductor region of the first conductivity type through the exposed portion of the semiconductor region of the first conductivity type. Forming a first diffusion region of a second conductivity type opposite to the first conductivity type so that the first diffusion region and the semiconductor region of the first conductivity type serve as a protection diode Forming a second conductive layer on the semiconductor substrate, and electrically connecting the second conductive layer to the first conductive layer and the first diffusion region, and the first conductive layer and the second conductive layer. Patterning the conductive layer to form a gate electrode having a two-layer structure including the first conductive layer and the second conductive layer, and forming a second electrode of the second conductive type in the semiconductor region of the first conductive type. Forming diffusion regions, each of the second diffusion regions serving as a source and a drain, forming a first insulating film on the semiconductor substrate, and forming at least one contact hole in the first insulating film And forming a first metal wiring layer on the first insulating film, and electrically connecting the first metal wiring layer to the second conductive layer or the second diffusion region through the contact hole formed in the first insulating film. And a step of forming a second insulating film on said first insulating film and said first metal wiring layer.

In this case, the region in which the first diffusion region in the semiconductor region of the first conductivity type is formed and the region in which the second diffusion region in the semiconductor region of the second conductivity type are formed are formed by the device isolation film. It is desirable to be isolated.

Further, in the forming of the first diffusion region of the second conductivity type opposite to the first conductivity type in the semiconductor region of the first conductivity type through the exposed portion of the semiconductor region of the first conductivity type. And the first diffusion region is formed in the semiconductor region of the first conductivity type by ion implantation onto the exposed portion of the semiconductor region of the first conductivity type.

The first conductive layer may be a polysilicon film doped with N-type impurities, and the second conductive layer may be a tungsten silicide film.

The method may further include forming the second diffusion region of the second conductivity type in the semiconductor region of the first conductivity type after patterning the first conductive layer and the second conductive layer. Forming the third diffusion regions of the second conductivity type in the semiconductor region of the first conductivity type to make the third diffusion region serve as an LDD, and on the sidewalls of the first and second conductive layers. It is preferable to further include the step of forming a sidewall insulating spacer.

The method may further include forming at least one contact hole in the second insulating film after forming the second insulating film on the first insulating film and the first metal wiring layer. Forming a second metal wiring layer, and electrically connecting the second metal wiring layer to the first metal wiring layer through the contact hole formed in the second insulating film, and on the second insulating film and the second metal wiring layer. It is preferable to further comprise forming a third insulating film.

According to another aspect of the present invention, a semiconductor substrate, a P-type well and an N-type well formed on the semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, and a device formed on the surface of the semiconductor substrate An element isolation film defining a formation region, a first N-type diffusion region formed in the P-type well and serving as a protective diode together with the P-type well, formed in the N-type well, A first P-type diffusion region serving as a protective diode together, a second N-type diffusion region formed in the P-type well, each of which serves as a source or a drain, and formed in the N-type well, A second P-type diffusion region serving as a source or a drain, and a first conductive layer formed on at least a portion of the gate insulating film and the device isolation film, and a second conductive layer formed on the first conductive layer A first N-type diffusion layer or the first P-type diffusion layer and is electrically connected to the first conductive layer and to the first N-type diffusion layer or the first P-type diffusion layer, and the first conductive layer and the The first conductive layer and the second conductive layer constituting a gate electrode having a two-layer structure, the first conductive layer formed on the semiconductor substrate and covering the second conductive layer, and the first conductive layer having a second conductive layer. A first metal wiring layer formed on the insulating film and electrically connected to the second conductive layer, the second N-type diffusion region, or the second P-type diffusion region through at least one contact hole formed in the first insulating layer; A second insulating film formed on the first insulating film and the first metal wiring layer, and a second insulating film formed on the second insulating film and electrically connected to the first metal wiring layer through at least one contact hole formed in the second insulating film. A second metal wiring layer to be connected to, and a semiconductor having a third insulating film formed on the second metal wiring layer and the second insulating film is provided.

In this case, a region where the first N-type diffusion region in the P-type well is formed and a region where the second N-type diffusion region in the P-type well are formed are isolated by the device isolation film, and the N-type The region where the first P-type diffusion region in the well is formed and the region where the second P-type diffusion region in the N-type well are formed are preferably isolated by the device isolation film.

The first conductive layer may be a polysilicon film doped with N-type impurities, and the second conductive layer may be a tungsten silicide film.

In addition, the semiconductor device includes sidewall spacers formed on sidewalls of the first and second conductive layers, third N-type diffusion regions formed in the P-type well and serving as LDD, It is preferable to further include third P-type diffusion regions formed in the N-type well and serving as LDD.

According to still another aspect of the present invention, there is provided a semiconductor substrate, a device isolation layer is formed on a surface of the semiconductor substrate to define a device formation region, and a P-type well and an N-type substrate are formed on the semiconductor substrate. Forming a well, forming a gate insulating film on the surface of the semiconductor substrate, forming a first conductive film on the semiconductor substrate, selectively removing the first conductive film and the gate insulating film, and Exposing a portion of the P-type well, and forming a first N-type diffusion region in the P-type well through an exposed portion of the P-type well, so that the first N-type diffusion region and the P-type well Acting as a protective diode, selectively removing the first conductive film and the gate insulating film to expose a portion of the N-type well, and through the exposed portion of the N-type well. Forming a first P-type diffusion region in the N-type well so that the first P-type diffusion region and the N-type well serve as a protection diode, and forming a second conductive film on the semiconductor substrate; Electrically connecting the second conductive film to the first conductive film, the first P-type diffusion region, and the first N-type diffusion region, and patterning the first conductive film and the second conductive film, Forming a gate electrode having a two-layer structure including the first conductive film and the second conductive film, and forming second N-type diffusion regions in the P-type well, so that each of the second N-type diffusion regions Acting as a source or a drain, forming second P-type diffusion regions in the N-type well, so that each of the second P-type diffusion regions acts as a source or a drain, and on the semiconductor substrate 1st Insulation Forming a film, forming at least one contact hole in the first insulating film, forming a first metal wiring layer on the first insulating film, and forming the first metal wiring layer on the first insulating film Electrically connecting the second conductive film with the second P-type diffusion region or the second N-type diffusion region through a contact hole, and a second insulating film on the first insulating film and the first metal wiring layer. Forming at least one contact hole in the second insulating film, forming a second metal wiring layer on the second insulating film, and forming the second metal wiring layer on the second insulating film. Electrically connecting the first metal wiring layer through a contact hole, and forming a third insulating film on the second insulating film and the second metal wiring layer. Is provided.

In this case, a region where the first N-type diffusion region in the P-type well is formed and a region where the second N-type diffusion region in the P-type well are formed are isolated by the device isolation film, and the N-type The region where the first P-type diffusion region in the well is formed and the region where the second P-type diffusion region in the N-type well are formed are preferably isolated by the device isolation film.

Further, in the forming of the first N-type diffusion region in the P-type well through the exposed portion of the P-type well, the first N-type diffusion region is ion implanted into the exposed portion of the P-type well Formed in the P-type well, and forming a first P-type diffusion region in the N-type well through an exposed portion of the N-type well, wherein the first P-type diffusion region is the exposure of the P-type well. It is preferable to form in the N-type well by ion implantation into the portion.

The first conductive layer may be a polysilicon film doped with N-type impurities, and the second conductive layer may be a tungsten silicide film.

The method may further include forming a third N in the P-type well after patterning the first conductive layer and the second conductive layer, and before forming the second P-type diffusion region and the second N-type diffusion region. Forming diffusion regions to form the third N-type diffusion regions as LDDs, and forming third P-type diffusion regions in the N-type wells, so that the third P-type diffusion regions serve as LDDs And forming a sidewall insulating spacer on the sidewalls of the first and second conductive layers.

The above and other features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. In addition, the same parts are designated by the same reference numerals throughout the specification.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described.

1A and 1B show a CMOS portion of a semiconductor device according to one embodiment of the present invention. 1A and 1B are cross-sectional views taken along lines in directions different from each other by 90 °.

The semiconductor device of FIGS. 1A and 1B includes, for example, a P-type silicon substrate 1, in which a P-type well region 3a and an N-type well region 3b are formed. On the P-type silicon substrate 1, a field oxide film 2 defining an active region is formed. N-channel MOS transistors and P-channel MOS transistors are formed in the active regions of the P-type well region 3a and the N-type well region 3b, respectively. The N-channel MOS transistor has an N-type diffusion region 17a and an LDD 15a as source / drain regions. On the other hand, the P-channel MOS transistor has a P-type diffusion region 17b and an LDD 15b as source / drain regions.

On the channel region between the source region and the drain region, a gate oxide film 5, a polysilicon film 6, and a tungsten silicide film 7 are sequentially formed from the bottom to the top. In this embodiment, the gate electrode has a two-layer structure including the polysilicon film 6 and the tungsten silicide film 7. Sidewall spacers 16 formed of an oxide film or the like are formed on both sidewall portions of the gate electrode including the polysilicon film 6 and the tungsten silicide film 7. In addition, an N type diffusion layer 4a and a P type diffusion layer 4b are formed in the P type well region 3a and the N type well region 3b, respectively. The N-type diffusion layer 4a and the P-type diffusion layer 4b serve as protective diodes. In addition, the P-type diffusion layer 4b and the N-type well region 3b also serve as protective diodes. The N-type diffusion layer 4a and the P-type diffusion layer 4b are electrically connected to respective portions of the tungsten silicide film 7 which is the upper layer of the gate electrode having the two-layer structure.

On the P-type silicon substrate 1, a first insulating film 8, a first metal wiring 10, a second insulating film 11, a second metal wiring 13, and a third insulating film 14 are formed. do. The first metal wiring 10 is electrically connected to the tungsten silicide film 7, the N-type diffusion layer 17a, the P-type diffusion layer 17b, and the like through the first contact hole 9. The second metal wire 13 is electrically connected to the first metal wire 10 through the second contact hole 12.

Hereinafter, a method of manufacturing a semiconductor device having the above-described structure will be described with reference to FIGS. 1A and 1B to 10A and 10B.

First, as shown in FIGS. 2A and 2B, the field oxide film 2 is formed on the surface of the P-type silicon substrate 1 by using the LOCOS method.

Next, near the surface of the P-type silicon substrate 1, for example, ion implantation or the like is used to form the P-type well region 3a and the N-type well 3b. In this case, it is also possible to form the above-described field oxide film 2 after the P type well region 3a and the N type well region 3b are formed.

A thin oxide film, that is, a gate oxide film 5, is formed in each of the element formation regions defined by the field oxide film 2 on the surface of the P-type silicon substrate 1.

As shown in Figs. 3A and 3B, on the entire surface of the substrate 1, a doped polysilicon film 6 previously doped with N-type impurities is deposited as the first layer electrode. On the contrary, after depositing a polysilicon film, it is also possible to dope an N type impurity to this polysilicon film.

4A and 4B, a resist film 20 is applied to the entire surface of the substrate 1, and the resist film 20 is exposed and patterned. By using the patterned resist film 20 as an etching mask, a portion of the polysilicon film 6 and the gate oxide film 5 on the region of the P-type well 3a where the protection diode is formed are selectively etched by etching. Remove

Ions are implanted into the P-type well region 3a where the N-type impurities are exposed. As a result, an N-type diffusion region 4a is formed in the P-type well 3a, and a protective diode is formed by the N-type diffusion region 4a and the P-type well 3a.

Next, the resist film 20 is removed.

5A and 5B, a protection diode is formed in the N-type well 3b in a manner similar to that of the protection diode in the P-type well 3a. That is, the resist film 21 is applied to the entire surface of the substrate 1, and the resist film 21 is exposed and patterned. Using the patterned resist film 21 as an etching mask, a part of the polysilicon film 6 and the gate oxide film 5 on the region of the N-type well 3b where the protection diode is formed is selectively etched by etching. Remove

Ion is implanted into the N-type well region 3b in which P-type impurities are exposed. As a result, a P-type diffusion region 4b is formed in the N-type well 3b, and a protective diode is formed by the P-type diffusion region 4b and the N-type well 3b.

Next, the resist film 21 is removed.

6A and 6B, a tungsten silicide film 7 is deposited as the second layer electrode on the entire surface of the substrate 1, for example, using a sputtering method. In this case, the tungsten silicide film 7 is electrically connected to the polysilicon film 6 and the diffusion layers 4a and 4b of the protective diode.

As shown in Figs. 7A and 7B, the polysilicon film 6 and the tungsten silicide film 7 are patterned using photolithography and etching, and two of the polysilicon film 6 and the tungsten silicide film 7 are formed. Each gate electrode 22 having a layer structure is formed.

8A and 8B, LDDs 15a and 15b are formed by ion implantation or the like. Next, an oxide film is formed on the entire surface of the substrate 1. The oxide film is etched back to form a size wall spacer 16 having oxide films on both sides of each gate electrode.

An ion implantation or the like is used to form an N type diffusion region 17a as a source / drain region in the P type well 3a, and a P type diffusion region 17b as a source / drain region in the N type well 3b. Form. Thus, as shown in Figs. 8A and 8B, an N-channel MOS transistor and a P-channel MOS transistor are formed in the P-type well 3a and the N-type well 3b, respectively.

Next, as shown in FIGS. 9A and 9B, the first insulating film 8 is formed on the entire surface of the substrate 1.

In the first insulating film 8, the first contact hole 9 is formed using, for example, photolithography, plasma etching, or the like. If necessary, the first contact hole 9 can be formed on the tungsten silicide film 7, the N-type diffusion region 17a, the P-type diffusion region 17b, or the like, which is the upper layer of the gate electrode.

Next, a metal film of aluminum, for example, is formed on the first insulating film 8 so that the first contact hole 9 is filled with the material of the metal film. This metal film is patterned by photolithography and etching to form the first metal wiring 10. The first metal wiring 10 is electrically connected to the tungsten silicide film 7, the N-type diffusion region 17a, and the P-type diffusion region 17b that are upper layers of the gate electrode through the first contact hole 9. do.

As shown in FIGS. 10A and 10B, a second insulating film 11 is formed on the entire surface of the substrate 1.

The second contact hole 12 is formed in the second insulating film 11 by using photolithography and plasma etching, for example. The second contact hole 12 is provided on the first metal wire 10.

Next, a metal film of aluminum, for example, is formed on the second insulating film 11 so that the second contact hole 12 is filled with the material of the metal film. This metal film is patterned by photolithography and etching to form the second metal wiring 13. The second metal wiring 13 is electrically connected to the first metal wiring 10 through the second contact hole 12.

Next, a third insulating film 14 is formed on the second insulating film 11 and the second metal wiring 13.

In the semiconductor device described above, the gate electrode is directly connected to the N-type diffusion region 4a and the P-type diffusion region 4b of the protection diode. Therefore, charges applied to the gate electrode in the gate electrode patterning process and other processes are transferred to the N-type diffusion region 4a and the P-type well region 3a and the P-type diffusion region 4b and the N-type well region 3b. Through the configured protection diode, it can be removed to the substrate 1.

In the present invention, the gate electrode is formed with a polysilicon film 6 as a lower layer on the gate oxide film 5, and a tungsten silicide film 7 as an upper layer on the polysilicon film 6, and a protective diode. Has a two-layer structure connected to the diffusion regions 4a and 4b. Therefore, a step of forming a resist film directly on the gate oxide film and a step of removing the resist film are not required. Therefore, problems of the semiconductor device of the prior art, that is, erosion and contamination of the gate oxide film can be prevented, and the reliability of the gate oxide film, that is, the reliability of the semiconductor device can be greatly improved.

Damage to the gate oxide film due to electric charges applied to the gate oxide film, that is, charging damage or damage by plasma, may occur in various process steps below. However, according to the present invention, it is possible to protect the butter gate oxide film 5 by charging damage even in the following process steps.

A process of etching a tungsten silicide 7 and a polysilicon film 6 to form a gate electrode.

An ion implantation step of forming the LDD 15a in the P-type well 3a.

An ion implantation step of forming an LDD 15b in an N-type well 3b.

An oxide film etch back process for forming the side wall spacers (16).

An ion implantation step of forming an N type diffusion region 17a in a P type well 3a.

An ion implantation step of forming a P-type diffusion region 17b in an N-type well 3b.

A plasma CVD process for forming a first insulating film (8).

Plasma etching process for forming the first contact hole (9).

Plasma etching process to form a first metal wiring (10) by patterning a metal film.

A plasma CVD process for forming a second insulating film (11).

Plasma etching process for forming the second contact hole (12).

Plasma etching process for forming a second metal wiring (13) by patterning a metal film.

A plasma CVD process for forming a third insulating film (14).

In the foregoing description, the invention has been described with reference to specific embodiments. However, it will be apparent to one skilled in the art that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Accordingly, the foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Accordingly, the invention is intended to embrace all such alterations and modifications as fall within the scope of the appended claims.

According to the present invention, a polysilicon film 6 is formed on the gate oxide film 5 as a lower layer, and a tungsten silicide film 7 is formed on the polysilicon film 6 as an upper layer. It has a two-layer structure connected to the diffusion regions 4a and 4b. Therefore, it is possible to prevent concentration of charge on the gate electrode and to suppress charging damage on the gate oxide film 5, that is, to suppress deterioration of the gate oxide film.

Further, according to the present invention, a process of directly forming a resist film on the gate oxide film 5 and a process of removing the resist film are not required. Therefore, erosion, contamination, etc. of the gate oxide film can be prevented, and the reliability of the gate oxide film is greatly improved. As a result, a stable gate threshold voltage can be obtained in the MOS transistor.

Claims (20)

In a semiconductor device: A semiconductor substrate having a first conductive semiconductor region; A gate insulating film formed on a surface of the semiconductor region of the first conductivity type; An element isolation film formed on a surface of the semiconductor region of the first conductivity type and defining an element type region; A first diffusion region formed in the semiconductor region of the first conductivity type and having a second conductivity type opposite to the first conductivity type, and acting as a protection diode together with the semiconductor region of the first conductivity type; Second diffusion regions formed in the semiconductor region of the first conductivity type and having the second conductivity type, each of which serves as a source or a drain; A first conductive layer is formed on at least a portion of the gate insulating film and the second diffusion layer, and a second conductive layer is formed on the first conductive layer and the first diffusion layer and the first conductive layer and the first diffusion layer. The first conductive layer and the second conductive layer electrically connected to the first conductive layer and the first conductive layer and the second conductive layer forming a gate electrode having a two-layer structure; A first insulating film formed on the semiconductor substrate and covering the second conductive film; A first metal wiring layer formed on the first insulating film and electrically connected to the second conductive layer or the second diffusion region through at least one contact hole formed in the first insulating film; And And a second insulating film formed on said first insulating film and said first metal wiring layer. 2. The device of claim 1, wherein a region in which the first diffusion region in the semiconductor region of the first conductivity type is formed and a region in which the second diffusion region in the semiconductor region of the second conductivity type are formed are formed in the device isolation film. A semiconductor device characterized by being isolated by. The semiconductor device according to claim 1, wherein the first conductive layer is a polysilicon film doped with an impurity, and the second conductive layer is a tungsten silicide film. The method of claim 1 wherein: Sidewall spacers formed on sidewalls of the first and second conductive layers; And And third diffusion regions formed in the semiconductor region of the first conductivity type and having the second conductivity type and serving as LDDs. The method of claim 1 wherein: A second insulating film formed on the first insulating film and the first metal wiring; A second metal wiring layer formed on the second insulating film and electrically connected to the first metal wiring layer through at least one contact hole formed in the second insulating film; And And a third insulating film formed on said second insulating film and said second metal wiring layer. In the semiconductor device manufacturing method: Providing a semiconductor substrate having a first semiconductor region of a first conductivity type; Defining an element formation region by forming an isolation layer on a surface of the semiconductor region of the first conductivity type; Forming a gate insulating film on a surface of the semiconductor region of the first conductivity type; Forming a first conductive layer on the semiconductor substrate; Selectively removing the first conductive layer and the gate insulating layer to expose a portion of the semiconductor region of the first conductivity type; Through the exposed portion of the semiconductor region of the first conductivity type, a first diffusion region of a second conductivity type opposite to the first conductivity type in the semiconductor region of the first conductivity type is formed, so that the first Causing a diffusion region and the semiconductor region of the first conductivity type to serve as a protection diode; Forming a second conductive layer on the semiconductor substrate to electrically connect the second conductive layer with the first conductive layer and the first diffusion region; Patterning the first conductive layer and the second conductive layer to form a gate electrode having a two-layer structure including the first conductive layer and the second conductive layer; Forming second diffusion regions of the second conductivity type in the semiconductor region of the first conductivity type, each second diffusion region serving as a source and a drain; Forming a first insulating film on the semiconductor substrate; Forming at least one contact hole in the first insulating film; Forming a first metal wiring layer on the first insulating film, and electrically connecting the first metal wiring layer to the second conductive layer or the second diffusion region through the contact hole formed in the first insulating film; And And forming a second insulating film on the first insulating film and the first metal wiring layer. 7. The device of claim 6, wherein a region in which the first diffusion region in the semiconductor region of the first conductivity type is formed and a region in which the second diffusion region in the semiconductor region of the second conductivity type are formed are formed in the device isolation film. A semiconductor device manufacturing method characterized by being isolated by. 7. The semiconductor device of claim 6, wherein a first diffusion region of a second conductivity type opposite to the first conductivity type in the semiconductor region of the first conductivity type is exposed through an exposed portion of the semiconductor region of the first conductivity type. In the forming step, the first diffusion region is formed in the semiconductor region of the first conductivity type by ion implantation onto the exposed portion of the semiconductor region of the first conductivity type. Semiconductor device manufacturing method. 7. The method of claim 6, wherein the first conductive layer is a polysilicon film doped with N-type impurities, and the second conductive layer is a tungsten silicide film. The method of claim 6, wherein the method comprises: forming the second diffusion regions of the second conductivity type in the semiconductor region of the first conductivity type after patterning the first conductive layer and the second conductive layer. before: Forming the third diffusion regions of the second conductivity type in the semiconductor region of the first conductivity type such that the third diffusion region serves as an LDD; And And forming sidewall insulating spacers on sidewalls of said first and second conductive layers. The method of claim 6, wherein the method comprises: after forming a second insulating film on the first insulating film and the first metal wiring layer: Forming at least one contact hole in the second insulating film; Forming a second metal wiring layer on the second insulating film, and electrically connecting the second metal wiring layer to the first metal wiring layer through the contact hole formed in the second insulating film; And And forming a third insulating film on the second insulating film and the second metal wiring layer. In a semiconductor device: A semiconductor substrate; A P type well and an N type well formed on the semiconductor substrate; A gate insulating film formed on a surface of the semiconductor substrate; An isolation layer formed on the surface of the semiconductor substrate to define an element formation region; A first N-type diffusion region formed in the P-type well and serving as a protective diode together with the P-type well; A first P-type diffusion region formed in the N-type well and serving as a protective diode together with the N-type well; A second N-type diffusion region formed in the P-type well, each of which serves as a source or a drain; A second P-type diffusion region formed in said N-type well, each of which serves as a source or a drain; A first conductive layer is formed on at least a portion of the gate insulating film and the device isolation film, and a second conductive layer is formed on the first conductive layer and on the first N-type diffusion layer or the first P-type diffusion layer, The first conductivity electrically connected to a first conductive layer and to the first N-type diffusion layer or the first P-type diffusion layer, wherein the first conductive layer and the second conductive layer constitute a gate electrode having a two-layer structure A layer and said second conductive layer; A first insulating film formed on the semiconductor substrate and covering the second conductive film; A first formed on the first insulating film and electrically connected to the second conductive layer, the second N-type diffusion region, or the second P-type diffusion region through at least one contact hole formed in the first insulating layer A metal wiring layer; A second insulating film formed on the first insulating film and the first metal wiring layer; A second metal wiring layer formed on the second insulating film and electrically connected to the first metal wiring layer through at least one contact hole formed in the second insulating film; And And a third insulating film formed on said second insulating film and said second metal wiring layer. The semiconductor device of claim 12, wherein the region in which the first N-type diffusion region is formed in the P-type well and the region in which the second N-type diffusion region is formed in the P-type well are separated by the device isolation film. And the region in which the first P-type diffusion region is formed in the N-type well and the region in which the second P-type diffusion region is formed in the N-type well are separated by the device isolation film. 13. The method of claim 12, wherein the first conductive layer is a polysilicon film doped with N-type impurities, and the second conductive layer is a tungsten silicide film. The method of claim 12 wherein: Sidewall spacers formed on sidewalls of the first and second conductive layers; Third N-type diffusion regions formed in the P-type well and serving as LDDs; And And third P-type diffusion regions formed in the N-type well and serving as LDDs. In the semiconductor device manufacturing method: Providing a semiconductor substrate; Forming a device isolation insulating film on the surface of the semiconductor substrate to define a device formation region; Forming a P-type well and an N-type well on the semiconductor substrate; Forming a gate insulating film on a surface of the semiconductor substrate; Forming a first conductive film on the semiconductor substrate; Selectively removing the first conductive layer and the gate insulating layer to expose a portion of the P-type well; Forming a first N-type diffusion region in the P-type well through an exposed portion of the P-type well, such that the first N-type diffusion region and the P-type well serve as a protection diode; Selectively removing the first conductive layer and the gate insulating layer to expose a portion of the N-type well; Forming a first P-type diffusion region in the N-type well through an exposed portion of the N-type well, such that the first P-type diffusion region and the N-type well serve as a protection diode; Forming a second conductive film on the semiconductor substrate, and electrically connecting the second conductive film to the first conductive film, the first P-type diffusion region, and the first N-type diffusion region; Patterning the first conductive film and the second conductive film to form a gate electrode having a two-layer structure including the first conductive film and the second conductive film; Forming second N-type diffusion regions in the P-type well, so that each of the second N-type diffusion regions serves as a source or a drain; Forming second P-type diffusion regions in the N-type well, so that each of the second P-type diffusion regions serves as a source or a drain; Forming a first insulating film on the semiconductor substrate; Forming at least one contact hole in the first insulating film; A first metal wiring layer is formed on the first insulating film, and the first metal wiring layer is formed through the contact hole formed in the first insulating film. Electrically connecting with the 2N type diffusion region; Forming a second insulating film on the first insulating film and the first metal wiring layer; Forming at least one contact hole in the second insulating film; Forming a second metal wiring layer on the second insulating film, and electrically connecting the second metal wiring layer to the first metal wiring layer through the contact hole formed in the second insulating film; And And forming a third insulating film on the second insulating film and the second metal wiring layer. The method of claim 16, wherein the region in which the first N-type diffusion region in the P-type well is formed, and the region in which the second N-type diffusion region in the P-type well are formed are isolated by the device isolation film. And the region in which the first P-type diffusion region is formed in the N-type well and the region in which the second P-type diffusion region is formed in the N-type well are separated by the device isolation film. 17. The method of claim 16, wherein in forming the first N-type diffusion region in the P-type well through the exposed portion of the P-type well, the first N-type diffusion region is the exposed portion of the P-type well. Implanted into the P-type well, and forming a first P-type diffusion region in the N-type well through an exposed portion of the N-type well, wherein the first P-type diffusion region is the P-type. And implanting ions into the exposed portions of the wells to form within said N-type wells. 17. The method of claim 16, wherein the first conductive layer is a polysilicon film doped with N-type impurities, and the second conductive layer is a tungsten silicide film. The method of claim 16, wherein after the patterning of the first conductive layer and the second conductive layer, prior to forming the second P-type diffusion region and the second N-type diffusion region: Forming third N-type diffusion regions in the P-type well so that the third N-type diffusion region serves as an LDD; Forming third P-type diffusion regions in the N-type well so that the third P-type diffusion region serves as an LDD; And And forming sidewall insulating spacers on sidewalls of said first and second conductive layers.