JP2006351998A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for suppressing any charge damage from being applied to a gate insulating film even when dry etching for wiring formation is advanced. <P>SOLUTION: The method comprises a step for forming gate insulating films 3a and 3b, a step for forming gate wiring 4a and 4b, a step for forming an insulating film 8, a step for forming connection holes 8a, 8b and 8c, a step for embedding conductors 9a, 9b and 9c in the connection holes 8a, 8b and 8c, a step for forming conductive films 11, 12 and 13 on the insulating film 8 and the conductors 9a, 9b and 9c, and a step for forming a plurality of wiring 10a, 10b and 10d and dummy wiring 10c on the insulating film 8 by patterning the conductive films 11, 12 and 13 by using dry etching. An interval between the dummy wiring 10c and the wiring 10b which is the closest to the dummy wiring 10c is set so as to be not more than the mutual intervals of the wiring 10a, 10b and 10d. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device. In particular, the present invention relates to a semiconductor device manufacturing method and a semiconductor device capable of suppressing charge damage to a gate insulating film during dry etching for wiring formation or gate wiring formation.

  Each drawing in FIG. 9 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device. First, as shown in FIG. 9A, two transistors are formed in a well 120 of the silicon substrate 101, and an impurity region 107d for discharge is formed in the silicon substrate 101. The well 120 and the impurity region 107d for discharge are sufficiently separated. The first transistor has the impurity region 107a as a source and the impurity region 107b as a drain. The second transistor has the impurity region 107b as a source and the impurity region 107c as a drain.

  Next, an interlayer insulating film 108 is formed on the entire surface including the two transistors and the discharge impurity region 107d, and tungsten plugs 109a and 109b and a dummy tungsten plug 109c are embedded in the interlayer insulating film 108. The tungsten plugs 109a and 109b are connected to the gate wirings 104a and 104b of the transistors, respectively, and the dummy tungsten plug 109c is connected to the impurity region 107d for discharge.

  Next, the barrier film 111, the Al alloy film 112, and the antireflection film 113 are stacked in this order on the entire surface including the interlayer insulating film 108, the tungsten plugs 109a and 109b, and the dummy tungsten plug 109c. The barrier film 111 is a film in which a TiN film and a Ti film are stacked in this order, and the antireflection film 113 is a film in which a Ti film and a TiN film are stacked in this order. Next, a resist pattern 150 is formed on the antireflection film 113.

Next, as shown in FIG. 9B, dry etching using plasma is performed using the resist pattern 150 as a mask. There is almost no selection ratio between the Ti film and the TiN film with respect to the Al alloy film. For this reason, the Al alloy wirings 110a, 110b, and 110d and the dummy Al alloy wiring 110c are formed by one dry etching. The Al alloy wirings 110a and 110b are located on the tungsten plugs 109a and 109b, respectively, and the dummy Al alloy wiring 110c is located on the dummy tungsten plug 109c (see, for example, Patent Document 1). The dummy Al alloy wiring 110c is sufficiently separated from the wiring group composed of the Al alloy wirings 110a, 110b, and 110d (for example, 1 μm or more).
In this dry etching, plasma charge for the Al alloy film 112 and the like is discharged to the impurity region 107d through the tungsten plug 109c.
Japanese Patent Laid-Open No. 10-154808 (FIG. 1)

  In dry etching when forming the wiring, a portion where the density of the wiring is dense (for example, between the Al alloy wirings 110a, 110b and 110d in FIG. 4) is a portion where the density of the Al alloy wiring is sparse (for example, in FIG. 10). The etching rate is slower than that around the Al alloy wiring 110c. For this reason, as shown in FIG. 10, when dry etching proceeds, the conductive films remain connected to each other in a portion where the wiring is dense, but the conductive films are separated from each other in a portion where the wiring is sparse.

In general, the density of wirings connected to transistors and wirings around them tends to be high. For this reason, when dry etching progresses, the wiring connected to the transistor is connected to the surrounding wiring, but is not connected to the portion where charge is discharged (for example, the impurity region 107d in FIG. 10). Become. If dry etching is continued in such a state, not only the wiring connected to the transistor but also the wiring located around it becomes an antenna, so that charges such as ions and electrons can be easily captured. As a result, a large amount of electric charge is charged in the gate insulating film, and the charged electric charge may flow to the semiconductor substrate through the gate insulating film and damage the gate insulating film.
For this reason, it is desired to develop a technology capable of suppressing charge from being charged in the wiring connected to the gate insulating film even after dry etching has progressed.

  The present invention has been made in consideration of the above-described circumstances, and its purpose is to suppress charge damage to the gate insulating film even when dry etching for wiring formation or gate wiring formation proceeds. An object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a part of a semiconductor substrate,
Forming a gate wiring on the gate insulating film;
Forming an insulating film on the semiconductor substrate and the gate wiring;
Forming a first connection hole located on the gate wiring and a second connection hole located on the semiconductor substrate in the insulating film; and
Embedding a first conductor in the first connection hole and embedding a second conductor in the second connection hole;
Forming a conductive film on the insulating film, on the first conductor, and on the second conductor;
By patterning the conductive film using dry etching, a plurality of wirings partially passing over the first conductor and dummy wirings passing over the second conductor are formed on the insulating film. And a process of
Comprising
The distance between the dummy wiring and the wiring closest to the dummy wiring is equal to or smaller than the minimum value of the mutual distance between the plurality of wirings.

  According to this method for manufacturing a semiconductor device, the distance between the wirings closest to the dummy wiring is not more than the mutual distance between the plurality of wirings. Therefore, even if dry etching proceeds, while the plurality of wirings are connected, the dummy wiring and the wiring closest to the dummy wiring are connected to each other. Note that the gate wiring includes a gate electrode.

Therefore, plasma charge generated in the plurality of wirings during dry etching is discharged to the semiconductor substrate via the dummy wirings and the second conductor. Therefore, even if dry etching for forming the wiring is advanced, it is possible to suppress the charge damage to the gate insulating film.
An interval between the dummy wiring and the wiring closest to the dummy wiring is, for example, 0.3 μm or less.

  In the step of patterning the conductive film, the dummy wiring is preferably formed thicker than the wiring. In the step of forming the first connection hole and the second connection hole in the insulating film, it is preferable that a plurality of the second connection holes are formed. If it does in this way, the plasma charge which arises in these wiring will become easy to be discharged to the semiconductor substrate via the 2nd electric conductor buried in the 2nd above-mentioned connection hole.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an element isolation film on a semiconductor substrate; ,
Forming a gate insulating film on the semiconductor substrate located in the transistor formation region;
Forming a conductive film on the gate insulating film, on the semiconductor substrate located in the discharge region, and on the element isolation film;
By patterning the conductive film using dry etching, a plurality of gate wirings passing over the gate insulating film are formed, and dummy wirings are formed on the semiconductor substrate and the element isolation film located in the discharge region. Forming a step;
Comprising
The distance between the dummy wiring and the gate wiring closest to the dummy wiring is equal to or smaller than the minimum value of the mutual distance between the plurality of gate wirings.

According to this method for manufacturing a semiconductor device, even if dry etching progresses, while the plurality of gate wirings are connected, the gap between the dummy wiring and the gate wiring closest to the dummy wiring is not. Are connected to each other.
For this reason, plasma charges generated in the plurality of gate wirings during dry etching are discharged to the semiconductor substrate through the dummy wirings. Therefore, even if dry etching for forming the gate wiring proceeds, it is possible to suppress charge damage to the gate insulating film.

  After the step of patterning the conductive film, a step of forming an insulating film on the dummy wiring and the gate wiring, a first connection hole located on the gate wiring, and the dummy in the insulating film Forming each of the second connection holes located on the wiring; embedding the first conductor in the first connection hole; and embedding the second conductor in the second connection hole; Forming a second conductive film on the insulating film, the first conductor, and the second conductor; and patterning the second conductive film using dry etching And a step of forming a plurality of wirings partially passing on the first conductor and a second dummy wiring passing on the second conductor on the insulating film. The distance between the second dummy wiring and the wiring closest to the second dummy wiring is equal to or smaller than the minimum value of the mutual distance between the plurality of wirings.

A semiconductor device according to the present invention includes a gate insulating film formed on a part of a semiconductor substrate,
A gate wiring formed on the gate insulating film;
An insulating film formed on the semiconductor substrate and the gate wiring;
A first connection hole formed in the insulating film and located on the gate wiring;
A second connection hole formed in the insulating film and located on the semiconductor substrate;
A first conductor embedded in the first connection hole;
A second conductor embedded in the second connection hole;
A plurality of wirings formed on the insulating film and partially located on the first conductor;
A dummy wiring formed on the insulating film and positioned on the second conductor;
Comprising
The distance between the dummy wiring and the wiring closest to the dummy wiring is equal to or smaller than the minimum value of the mutual distance between the plurality of wirings. The dummy wiring is formed in the same process as the plurality of wirings.

Another semiconductor device according to the present invention is provided on a semiconductor substrate, and an element isolation film that separates a transistor formation region where a transistor is formed and a discharge region where a charge is discharged from each other,
A gate insulating film formed on the semiconductor substrate located in the transistor formation region;
A plurality of gate lines partially passing over the gate insulating film;
Dummy wirings formed on the element isolation film and partially located on the semiconductor substrate in the discharge region;
Comprising
The distance between the dummy wiring and the gate wiring closest to the dummy wiring is equal to or smaller than the minimum value of the mutual distance between the plurality of gate wirings.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. The present embodiment is a method of forming a transistor and a first layer of Al alloy wiring.

  First, as shown in FIG. 1A, an element isolation film 2 is embedded in a silicon substrate 1 on which a well 20a is formed by using a trench isolation method. Thereby, the transistor formation region 1a where the transistor is formed and the discharge region 1b where the plasma charge is discharged are separated from each other. The transistor formation region 1a is located in the well 20a. For example, the discharge region 1b is disposed at a position close to the transistor formation region. The element isolation film 2 may be formed by a LOCOS method.

  Next, the silicon substrate 1 is thermally oxidized. As a result, a thermal oxide film 3 serving as a gate insulating film of the transistor is formed on the silicon substrate 1 located in the transistor formation region 1a. A thermal oxide film is also formed on the silicon substrate 1 located in the discharge region 1b.

  Next, a polysilicon film is formed on the entire surface including the thermal oxide film 3, and this polysilicon film is patterned. As a result, transistor gate wirings 4 a and 4 b are formed on the thermal oxide film 3. The gate lines 4a and 4b are located above the same well 20a and are substantially parallel to each other. Next, impurity ions are implanted into the silicon substrate 1 using the gate wirings 4a and 4b and the element isolation film 2 as a mask. Thereby, low-concentration impurity regions 6a, 6b, 6c, and 6d of the transistor are formed on the silicon substrate 1 located in the transistor formation region 1a. Impurities are also implanted into the silicon substrate 1 located in the discharge region 1b.

  Next, a silicon oxide film or a stacked film of a silicon oxide film and a silicon nitride film is formed on the entire surface including the gate wirings 4a and 4b, and this film is etched back. Thereby, the side walls of the gate wirings 4 a and 4 b are covered with the side walls 5. In this etch-back process, the thermal oxide film 3 is thin except for the gate insulating films 3a and 3b located under the gate wirings 4a and 4b.

  Next, impurity ions are implanted into the silicon substrate 1 using the gate wirings 4a and 4b, the sidewalls 5 and the element isolation film 2 as a mask. Thereby, impurity regions 7a, 7b and 7c are formed in the silicon substrate 1 located in the transistor formation region 1a, and a discharge impurity region 7d is formed in the silicon substrate 1 located in the discharge region 1b.

The impurity region 7a functions as a source of a transistor having the gate wiring 4a. The impurity region 7b functions as the drain of the transistor having the gate wiring 4a and the source of the transistor having the gate wiring 4b. The impurity region 7c functions as the drain of the transistor having the gate wiring 4b.
In this manner, transistors and discharge impurity regions 7d are formed in the silicon substrate 1.

Next, an interlayer insulating film 8 containing silicon oxide as a main component is formed on the entire surface including the transistor and the discharge element by a CVD method. Next, a photoresist film (not shown) is applied on the interlayer insulating film 8, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the interlayer insulating film 8. Next, the interlayer insulating film 8 is etched using this resist pattern as a mask. Thereby, connection holes 8a, 8b, 8c are formed in the interlayer insulating film 8. The connection holes 8a and 8b are located on the gate wirings 4a and 4b, respectively. The connection holes 8c are located on the impurity region 7d, and more than the connection holes 8a and 8b are formed.
Thereafter, the resist pattern is removed.

  Next, a tungsten film is formed in each connection hole and on the interlayer insulating film 8 by a CVD method. Next, the tungsten film located on the interlayer insulating film 8 is removed by etch back or CMP. Thereby, tungsten plugs 9a, 9b, 9c are formed in the connection holes 8a, 8b, 8c, respectively. More tungsten plugs 9c are formed than tungsten plugs 9a and 9b.

  Next, as shown in FIG. 1B, a barrier film 11 in which a TiN film and a Ti film are laminated in this order on the interlayer insulating film 8 and the tungsten plugs 9a, 9b, and 9c is formed by reactive sputtering and sputtering. Form by the method. Next, an Al alloy film 12 is formed on the barrier film 11 by a sputtering method. Next, an antireflection film 13 is formed on the Al alloy film 12. The antireflection film 13 is a film in which a Ti film and a TiN film are laminated in this order, and is formed using a sputtering method and a reactive sputtering method.

  Next, as shown in FIG. 1C, a photoresist film is applied on the antireflection film 13, and this photoresist film is exposed and developed. Thereby, a resist pattern 50 is formed on the antireflection film 13. Next, in order to form the wirings 10a, 10b, 10d and the dummy wiring 10c, dry etching using plasma is performed using the resist pattern 50 as a mask.

  The wirings 10a, 10b, 10d and the dummy wiring 10c are substantially parallel to each other. The wirings 10a and 10b are located on the tungsten plugs 9a and 9b, respectively. The dummy wiring 10c is thicker than the wirings 10a, 10b, and 10d, and is located on the tungsten plug 9c. The wiring 10d is disposed at a position facing the dummy wiring 10c across the wirings 10a and 10b.

  In the initial stage of this dry etching, the antireflection film 13 or the Al alloy film 12 is charged. A plurality of tungsten plugs 9c are formed, and there are more tungsten plugs 9a and 9b. Further, as described above, the dummy wiring 10c is thicker than the wirings 10a, 10b, and 10d. For this reason, the resistance from the tungsten plug 9c to the impurity region 7d is lower than the resistance from the tungsten plugs 9a and 9b to the well 20a located below the gate insulating films 3a and 3b. Therefore, the charged charge is discharged to the impurity region 7d through the plurality of tungsten plugs 9c.

  The mutual spacing between the wirings 10a, 10b, and 10d is the minimum space (for example, 0.3 μm) on the design rule. The mutual interval between the wiring 10b and the dummy wiring 10c is less than the minimum space (for example, 0.3 μm or less) in the design rule.

  For this reason, when dry etching progresses, the wiring group composed of the wirings 10a, 10b, 10d and the dummy wiring 10c is separated from the other and connected to each other. However, the dummy wiring 10c is thicker and has a lower resistance than the wirings 10a, 10b and 10d, and is connected to the discharge impurity region 7d via the tungsten plug 9c. Therefore, in the dry etching after the state of FIG. 1C, the charges charged in the wirings 10a, 10b, and 10d are discharged to the impurity region 7d through the dummy wiring 10c and the plurality of tungsten plugs 9c. Therefore, damage to the gate insulating films 3a and 3b due to charge during dry etching is suppressed.

Thereafter, as shown in FIG. 2A, when the dry etching further proceeds, the wirings 10a, 10b, and 10d and the dummy wiring 10c are separated from each other. When the distance between the dummy wiring 10c and the wiring 10b is less than the minimum space, the wiring 10b and the dummy wiring 10c are separated after the wirings 10a, 10b, and 10d are separated from each other.
Then, as shown in FIG. 2B, the resist pattern 50 is removed.

As described above, according to the first embodiment of the present invention, the dummy wirings 10c are arranged at intervals of not more than the minimum space (for example, 0.3 μm or less) on the design rule next to the wiring group composed of the wirings 10a, 10b, and 10d. It is arranged. For this reason, even in the latter half of the dry etching, the wiring group composed of the wirings 10a, 10b, and 10d is connected to the dummy wiring 10c. Accordingly, the charges charged in the wirings 10a, 10b, and 10d are discharged to the impurity region 7d through the dummy wiring 10c and the tungsten plug 9c. Further, the dummy wiring 10c is thicker than the wirings 10a, 10b and 10d, and the tungsten plug 9c is formed more than the tungsten plugs 9a and 9b. For this reason, the charged electric charge is easy to be discharged.
Therefore, charge damage to the gate insulating films 3a and 3b when the gate wirings 4a and 4b are formed is suppressed.

  3 to 8 are views for explaining a method of manufacturing a semiconductor device according to the second embodiment of the present invention. 3 to 8, (A) is a plan view, (B) is an AA sectional view of (A), and (C) is a BB sectional view of (B). FIG. 8 is a cross-sectional view for explaining the next step of FIG. This embodiment is a method of forming a transistor on a silicon substrate. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in each drawing of FIG. 3, a well 20 a and an element isolation film 2 are formed on a silicon substrate 1. Thereby, the transistor formation region 1a and the discharge region 1c are separated from each other. The discharge region 1c is located on the upper right side of the transistor formation region 1a in the plan view of FIG.

  Thereafter, a thermal oxide film 3 is formed as a gate insulating film of the transistor by using a thermal oxidation method. In this step, a thermal oxide film (not shown) is also formed on the discharge region 1c. This thermal oxide film is the same as the method for removing the thermal oxide film in the discharge region 1b in the first embodiment. It is removed using the method.

  Next, as shown in each drawing of FIG. 4, a polysilicon film 4 is formed on the entire surface including the element isolation film 2, the thermal oxide film 3 located in the transistor formation region 1a, and the silicon substrate 1 located in the discharge region 1c. Is formed by plasma CVD. At this time, the polysilicon film 4 is charged, but the charged charge is discharged to the silicon substrate 1 located in the discharge region 1c. For this reason, charge damage to the thermal oxide film 3 is suppressed.

  Next, as shown in each drawing of FIG. 5, a photoresist film is applied on the polysilicon film 4, and this photoresist film is exposed and developed. As a result, a resist pattern 51 is formed on the polysilicon film 4. Next, dry etching for forming the gate wirings 4a and 4b and the dummy wiring 4c is performed using the resist pattern 51 as a mask. The gate wirings 4 a and 4 b are substantially parallel to each other and pass over the gate insulating films 3 a and 3 b that are part of the thermal oxide film 3. The dummy wiring 4c is substantially parallel to the gate wirings 4a and 4b. Further, the distance between the dummy wiring 4c and the gate wiring 4b is equal to or smaller than the mutual distance (eg, 0.3 μm) between the gate wirings 4a and 4b.

At the beginning of this dry etching, the polysilicon film 4 is charged with charges from the plasma, but the charged charges are discharged to the discharge region 1c.
As dry etching progresses, as shown in FIG. 5B, the gate wirings 4a and 4b and the dummy wiring 4c are not cut from each other, but are separated from each other. Even in such a state, the charges charged in the gate wirings 4a and 4b and the dummy wiring 4c are discharged from the discharge region 1c located under the dummy wiring 4c.
Therefore, charge damage to the gate insulating films 3a and 3b is suppressed.

  Further, as shown in each drawing of FIG. 6, when dry etching proceeds, the gate wirings 4a and 4b and the dummy wiring 4c are separated from each other.

  Thereafter, as shown in each drawing of FIG. 7, the resist pattern 51 is removed. Next, low concentration impurity regions 6a, 6b, 6c, 6d, sidewalls 5, and impurity regions 7a, 7b, 7c are formed. These forming methods are the same as those in the first embodiment.

  Further, as shown in the sectional view of FIG. 8, an interlayer insulating film 8, tungsten plugs 9a, 9b, 9c, wirings 10a, 10b, and dummy wirings 10c are formed. In the present embodiment, the tungsten plug 9c is located on the dummy wiring 4c. These forming methods are the same as those in the first embodiment. For this reason, the charge charged when the wirings 10a and 10b and the dummy wiring 10c are formed is discharged to the discharge region 1c through the dummy wiring 4c.

As described above, according to the second embodiment of the present invention, the dummy wiring 4c is arranged next to the gate wirings 4a and 4b at a distance equal to or smaller than the distance between the gate wirings 4a and 4b. For this reason, even in the second half of the dry etching, the gate wirings 4a and 4b are connected to the dummy wiring 4c. Accordingly, the charges charged in the gate wirings 4a and 4b are discharged to the silicon substrate 1 in the discharge region 1c through the dummy wiring 4c. For this reason, the charge damage to the gate insulating films 3a and 3b is suppressed.
Moreover, the same effect as 1st Embodiment can also be acquired.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

(A) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). Sectional drawing for demonstrating the next process of. (A) is sectional drawing for demonstrating the next process of FIG.1 (C), (B) is sectional drawing for demonstrating the next process of (A). (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment, (B) is AA sectional drawing of (A), (C) is BB cross section of (B). Figure. (A) is a top view for demonstrating the next process of FIG. 3, (B) is AA sectional drawing of (A), (C) is BB sectional drawing of (B). (A) is a top view for demonstrating the next process of FIG. 4, (B) is AA sectional drawing of (A), (C) is BB sectional drawing of (B). (A) is a top view for demonstrating the next process of FIG. 5, (B) is AA sectional drawing of (A), (C) is BB sectional drawing of (B). (A) is a top view for demonstrating the next process of FIG. 6, (B) is AA sectional drawing of (A), (C) is BB sectional drawing of (B). Sectional drawing for demonstrating the next process of FIG. (A) is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device, (B) is sectional drawing for demonstrating the next process of (A). Sectional drawing for demonstrating the conventional subject.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 ... Silicon substrate, 1a ... Transistor formation area, 1b, 1c ... Discharge area, 2 ... Element isolation film, 3 ... Thermal oxide film, 3a, 3b ... Gate insulating film, 4a, 4b, 104a, 104b ... Gate wiring 4c ... dummy wiring, 5 ... sidewall, 6a, 6b, 6c, 6d ... low concentration impurity region, 7a, 7b, 7c, 7d, 107a, 107b, 107c, 107d ... impurity region, 8, 108 ... interlayer insulating film 8a, 8b, 8c ... connection holes, 9a, 9b, 9c, 109a, 109b, 109c ... tungsten plugs, 10a, 10b, 10d ... wiring, 10c ... dummy wiring, 11 ... barrier film, 12, 112 ... Al alloy film , 13, 113 ... antireflection film, 20a, 120 ... well, 50, 51, 150 ... resist pattern, 110a, 110b, 110c, 110 ... Al alloy wiring, 111 ... barrier film

Claims (9)

Forming a gate insulating film on a part of the semiconductor substrate;
Forming a gate wiring on the gate insulating film;
Forming an insulating film on the semiconductor substrate and the gate wiring;
Forming a first connection hole located on the gate wiring and a second connection hole located on the semiconductor substrate in the insulating film; and
Embedding a first conductor in the first connection hole and embedding a second conductor in the second connection hole;
Forming a conductive film on the insulating film, on the first conductor, and on the second conductor;
By patterning the conductive film using dry etching, a plurality of wirings partially passing over the first conductor and dummy wirings passing over the second conductor are formed on the insulating film. And a process of
Comprising
A method of manufacturing a semiconductor device, wherein an interval between the dummy wiring and the wiring closest to the dummy wiring is equal to or less than a minimum value of a mutual interval between the plurality of wirings.   The method of manufacturing a semiconductor device according to claim 1, wherein in the step of patterning the conductive film, the dummy wiring is formed thicker than the wiring.   3. The method of manufacturing a semiconductor device according to claim 2, wherein in the step of forming the first connection hole and the second connection hole in the insulating film, a plurality of the second connection holes are formed.   The method for manufacturing a semiconductor device according to claim 1, wherein an interval between the dummy wiring and the wiring closest to the dummy wiring is 0.3 μm or less. Forming a transistor isolation region on a semiconductor substrate to separate each of a transistor formation region in which a transistor is formed and a discharge region in which charges are discharged;
Forming a gate insulating film on the semiconductor substrate located in the transistor formation region;
Forming a conductive film on the gate insulating film, on the semiconductor substrate located in the discharge region, and on the element isolation film;
The conductive film is patterned by dry etching to form a plurality of gate wirings passing over the gate insulating film, and dummy wirings on the semiconductor substrate and the element isolation film located in the discharge region Forming a step;
Comprising
A method of manufacturing a semiconductor device, wherein an interval between the dummy wiring and the gate wiring closest to the dummy wiring is equal to or smaller than a minimum value of a mutual interval between the plurality of gate wirings. After the step of patterning the conductive film,
Forming an insulating film on the dummy wiring and the gate wiring;
Forming a first connection hole located on the gate wiring and a second connection hole located on the dummy wiring in the insulating film;
Embedding a first conductor in the first connection hole and embedding a second conductor in the second connection hole;
Forming a second conductive film on the insulating film, on the first conductor, and on the second conductor;
By patterning the second conductive film using dry etching, a plurality of wirings partially passing over the first conductor and the second conductor passing over the second conductor are formed on the insulating film. Forming two dummy wirings;
Comprising
6. The method of manufacturing a semiconductor device according to claim 5, wherein an interval between the second dummy wiring and the wiring closest to the second dummy wiring is equal to or smaller than a minimum value of an interval between the plurality of wirings. A gate insulating film formed on a part of the semiconductor substrate;
A gate wiring formed on the gate insulating film;
An insulating film formed on the semiconductor substrate and the gate wiring;
A first connection hole formed in the insulating film and located on the gate wiring;
A second connection hole formed in the insulating film and located on the semiconductor substrate;
A first conductor embedded in the first connection hole;
A second conductor embedded in the second connection hole;
A plurality of wirings formed on the insulating film and partially located on the first conductor;
A dummy wiring formed on the insulating film and positioned on the second conductor;
Comprising
The semiconductor device, wherein an interval between the dummy wiring and the wiring closest to the dummy wiring is equal to or less than a minimum value of a mutual interval between the plurality of wirings.   The semiconductor device according to claim 7, wherein the dummy wiring is formed in the same process as the plurality of wirings. An element isolation film that is provided on a semiconductor substrate and separates each of a transistor formation region in which a transistor is formed and a discharge region in which electric charges are discharged;
A gate insulating film formed on the semiconductor substrate located in the transistor formation region;
A plurality of gate lines partially passing over the gate insulating film;
Dummy wirings formed on the element isolation film and partially located on the semiconductor substrate in the discharge region;
Comprising
The semiconductor device, wherein an interval between the dummy wiring and the gate wiring closest to the dummy wiring is equal to or smaller than a minimum value of a mutual interval between the plurality of gate wirings.

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