JPH0581181B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device and a method for manufacturing the same.

(Prior Art) In semiconductor integrated circuits, metallization technology for forming wiring occupies a very important position. In particular, with the high density integration of device components in recent years, the wiring width is also shifting from the micron order to the submicron order. Furthermore, in order to improve the degree of freedom in pattern design, wiring layers are also stacked in two, three or more layers.

Regarding conventional semiconductor devices and their manufacturing methods,
This will be explained using FIG. 3, which is a sectional view of each process. First, as shown in FIG. 3a, an n ⁺ -type diffusion layer 2 is formed at a predetermined position on the surface of a p-type semiconductor substrate 1, and then a silicon oxide film 3 is deposited on the entire surface thereof by CVD. A BPSG film 4 is deposited on the entire surface of this silicon oxide film 3.

Then, a contact hole 5 is formed on the n-type diffusion layer 2 using lithography technology and reactive ion etching (RIE) technology.

Next, as shown in FIG. 3b, aluminum is first deposited over the entire surface by sputtering, and then patterned by lithography according to the first wiring pattern to form the first aluminum wiring 21. Form.

As shown in FIG. 3c, after a silicon oxide film 22 is deposited over the entire surface by plasma CVD, it is planarized by, for example, etching back, and a through hole 23 for connection to the first aluminum wiring 21 is formed. Form.

Then, as shown in FIG. 3d, aluminum is deposited on the entire surface and patterned according to the second wiring pattern to form the second aluminum wiring 2.
form 6. Then, the entire surface is covered with a PSG passivation film 27.

However, semiconductor devices manufactured by such conventional methods have the following problems.

Here, the deposition of aluminum, which is the wiring material, is
This is done by sputtering method. Therefore, the range direction of aluminum atoms is unidirectional, and only a small amount is deposited on the side walls of concave portions such as the contact hole 5, and the thickness may be only 10% of the thickness of the aluminum film on the flat portion. Such a phenomenon becomes more prominent as device components become smaller and the ratio (aspect ratio) of the sum of the thicknesses of the BPSG film 4 and the silicon oxide film 3 to the diameter of the contact hole 5 increases. If the film thickness of the first aluminum wiring 5 on the side wall portion of the contact hole 5 becomes thin, electromigration, stress migration, etc. will occur, and the reliability of the wiring will decrease.

Furthermore, aluminum wiring needs to be made finer as semiconductor devices become more highly integrated, but it has been extremely difficult to form fine wiring patterns using conventional manufacturing methods. Even if a fine resist pattern could be achieved through advances in lithography technology, it would not be possible to perform etching faithfully to the resist pattern. This is because the cross-sectional shape of the resist pattern is trapezoidal, so the bottom portion of the resist pattern is removed during etching, and the aluminum is also etched in the lateral direction, resulting in a narrow pattern width.

Generally, silicon oxide films 22 and 27 are deposited by plasma CVD as interlayer insulating films when forming aluminum interconnects. However, in the conventional deposition method, the deposited shape becomes an overhang as shown in the silicon oxide film 22 shown in FIGS. 4a and 4b. Therefore, if the film is deposited over a certain thickness, the third
As shown in FIGS. c and d and FIGS. 4a and 4b, a cavity 24, generally called a "cavity", is formed above the space of the aluminum wiring 21 and above the contact hole 5. Inside this cavity 24, the reactive gas used in the step of depositing the silicon oxide film 22 is sealed, and this reactive gas seeps out over time, thereby reducing the long-term reliability of the semiconductor device. descend.

(Problems to be Solved by the Invention) As described above, in the conventional case, there are problems such as a decrease in film thickness in contact holes of aluminum wiring, difficulty in forming fine patterns, and the existence of cavities in the silicon oxide film. As a result, the reliability of semiconductor devices has deteriorated. Such problems have become increasingly serious as semiconductor devices have become smaller and more complex in recent years.

The present invention has been developed in view of the above circumstances, and it is possible to form fine wiring patterns with good controllability, to ensure the necessary film thickness for the wiring, to improve step coverage, and to eliminate the presence of cavities in the interlayer insulating film. An object of the present invention is to provide a semiconductor device with improved reliability and a manufacturing method thereof.

[Structure of the invention]

(Means for Solving the Problems) A semiconductor device of the present invention includes a first interlayer insulating film formed on a conductive region and further provided with a contact hole corresponding to the conductive region;
a base film made of a material that serves as a growth nuclide for a wiring material, which is deposited on an interlayer insulating film and further patterned according to a wiring pattern; and a base film formed by selectively growing the wiring material only on the base film. The device is characterized in that it includes a second interlayer insulating film buried between the wires, and a second interlayer insulating film buried between the wires.

Such a semiconductor device includes a step of forming a diffusion layer on the surface of a semiconductor substrate, a step of forming a first interlayer insulating film on the entire surface of the semiconductor substrate, and a step of forming a contact hole corresponding to the diffusion layer in the first layer. a step of forming a base film made of a material that will become a growth nuclide for wiring material over the entire surface; a step of patterning the base film according to the wiring pattern; and a step of forming a second interlayer insulation film over the entire surface. forming a film; patterning the second interlayer insulating film according to the wiring pattern to expose the surface of the base film; and selectively growing the wiring material only on the exposed base film. The semiconductor device can be manufactured by a method for manufacturing a semiconductor device, which is characterized by comprising the steps of: forming a first wiring;

Polycrystalline silicon may be used as the base film, and in this case, tungsten, aluminum, molybdenum, or tungsten silicide may be used as the wiring material. Further, as the base film, any one of tungsten, aluminum, and titanium can also be used.

Further, after forming the first interlayer insulating film, the first base film, the second interlayer insulating film, and the first wiring on the semiconductor substrate by the manufacturing method described above, a third layer is further formed on the entire surface.
forming a contact hole corresponding to the first wiring in the third interlayer insulating film; forming a second base film on the entire surface; a step of patterning the base film of No. 2 according to the second wiring pattern, a step of forming a fourth interlayer insulating film on the entire surface, and a step of patterning the fourth interlayer insulating film according to the second wiring pattern, Two or more layers of wiring may be provided by exposing the surface of the second base film and selectively growing the wiring material only on the exposed second base film.

(Function) Since the second interlayer insulating film formed before the wiring patterning is deposited between the wirings on the first interlayer insulating film, no cavities are formed.

In addition, since the wiring material forming the wiring pattern is deposited in the contact hole provided in the first interlayer insulating film to connect the diffusion layer and the wiring pattern, the contact hole also has a film thickness that is required for the wiring. is ensured.

(Example) An example of the present invention will be described below with reference to FIG. 1, which is a sheet showing the steps. As shown in FIG. 1a, n ⁺
After forming the type diffusion layer 2, a silicon oxide film 3 is deposited to a thickness of, for example, 3000 Å using the CVD method, and a BPSG film 3 is further deposited thereon to a thickness of, for example, 7000 Å. Next, a contact hole 5 for connection with the n ⁺ type diffusion layer 2 is opened. Furthermore, an undoped polycrystalline silicon film 6 containing no impurities on the entire surface
For example, deposit 500 Å. In order to obtain good ohmic contact with the n ⁺ type diffusion layer 2, for example, arsenic ions are
Undoped polycrystalline silicon film 6 under the condition of 10 ¹⁵ /cm ²
Ion implantation is performed to mix ions into the material.

Next, the undoped polycrystalline silicon film 6 is patterned according to the wiring pattern of the first layer so that wiring portions remain, forming an arsenic-doped polycrystalline silicon film 6a shown in FIG. 1B. Then, a silicon nitride film 7 is deposited on the entire surface using the plasma CVD method, e.g.
Å Deposit.

Next, the silicon nitride film 7 is etched by photolithography and reactive ion etching using a mask that is inverted from the mask used when patterning the polycrystalline silicon film 6 so that the wiring portion is removed. do. As a result, the polycrystalline silicon film 6 which becomes the wiring pattern area is formed.
Expose a. At this time, it is difficult to perfectly match the patterns of the polycrystalline silicon film 6a and silicon nitride film 7a, which are patterned separately, so it is common for them to be slightly misaligned as shown in FIG. 1c. be.

Next, using a selective growth technique, for example, an undoped layer with exposed tungsten is grown on the polycrystalline silicon film 6a to form a first tungsten interconnect 8 as shown in FIG. 1d.

Further, in order to obtain good ohmic contact between the n ⁺ type diffusion layer 2 and the arsenic-doped polycrystalline silicon film 6a into which arsenic ions are implanted,
Heat treatment is performed in nitrogen at ℃ for 30 minutes. As a result, arsenic ions in arsenic-doped polycrystalline silicon film 6a are electrically activated. The first tungsten wiring 8 formed in this way has good flatness, and since tungsten is deposited entirely in the contact hole 5, the necessary film thickness for the wiring is secured and step coverage is improved. Ru. Further, since the silicon nitride film 7a is completely buried between the first tungsten interconnections 8 on the BPSG film 4, no cavities exist.

Next, as shown in Figure 1e, the plasma
For example, silicon oxide film 9 is coated on the entire surface by CVD method.
A thickness of 5000 Å is deposited, and a through hole 23 for connection to the first tungsten wiring 8 is provided. As the material for the second wiring pattern, for example, aluminum is deposited to a thickness of 1.0 μm and patterned according to the second wiring pattern to form the second aluminum wiring 10.

The semiconductor device manufactured as described above has
It has the following effects.

First, since the arsenic-doped polycrystalline silicon film 6a can be formed relatively thin, it can be finely patterned on the BPSG film 4 in which the contact hole 5 is provided according to the first wiring pattern. Therefore, it is easy to miniaturize the first tungsten wiring formed by growing tungsten using the arsenic-doped polycrystalline silicon film 6a as the first base film. Furthermore, in this step of growing tungsten, the film is grown until it becomes flat, so that the flatness of the film of the first tungsten wiring 8 is improved. Therefore, the second aluminum wiring 10 formed above the planarized first tungsten wiring 8 with the silicon oxide film 9 interposed therebetween is similar to the second aluminum wiring 10 shown in FIG.
It is clearly planarized compared to the aluminum wiring 25 shown in FIG. 2, and the reliability is improved.

Since the silicon nitride film 7a formed before the arsenic-doped polycrystalline silicon film 6a is patterned is buried in the region on the BPSG film 4 where the first tungsten wiring 8 does not exist.
The cavity 24 present in the conventional case shown in FIG. 3d and FIGS. 4a and 4b is not formed. Therefore, as a matter of course, when depositing the silicon oxide film 9 by the plasma CVD method, the reaction gas will not be trapped inside.

In addition, since tungsten is embedded in the contact hole 5, the film thickness necessary for wiring is ensured in the contact hole 5 as well.
Routing step coverage has been improved.

The fine wiring pattern as described above is formed flat with good controllability, and furthermore, since there is no cavity in the interlayer insulating film, it is possible to obtain a semiconductor device that maintains high reliability over a long period of time.

The above embodiments are examples in which the present invention is applied to a semiconductor device with a two-layer wiring structure, but the invention can also be applied to a semiconductor device with a three-layer or more wiring structure. Another embodiment having a three-layer wiring structure is shown in FIG.

Here, the steps up to forming the first tungsten wiring 8 are as follows:
The steps are the same as those up to Figure d. then plasma
For example, silicon oxide film 9 is coated on the entire surface by CVD method.
A through hole 15 for connecting to the first tungsten wiring 8 is formed by depositing 5000 Å. After an undoped polycrystalline silicon film is deposited to a thickness of, for example, 500 Å as a base film for selectively growing the second wiring material, arsenic ions are implanted and ion mixing is performed.

Next, the undoped polycrystalline silicon film is patterned according to the second layer wiring pattern to form an undoped polycrystalline silicon film 16 as shown in FIG.
Let it be a. Then, for example, apply a silicon nitride film to the entire surface.
After depositing 8000 Å, etching is performed to expose the undoped polycrystalline silicon film 16a, and tungsten is grown on this exposed portion to form a second tungsten interconnect 18. Then, as in the case of the first dungsten wiring 8, heat treatment is performed in nitrogen at 700° C. for 30 minutes to electrically activate arsenic ions in the polycrystalline silicon film 16a.

The same process as above is further repeated to form a silicon oxide film 19, an undoped polycrystalline silicon film 26a as a base film, and a silicon nitride film 27a, and then tungsten is grown on the polycrystalline silicon film 26a to form a third tungsten film. Wiring 28 is formed.

In this embodiment, as in the embodiment shown in FIG. 1, the first, second, and third wiring patterns can be formed flat with good controllability, and the step coverage of the wiring is improved. Furthermore, since there is no cavity in each interlayer insulating film, a highly reliable semiconductor device can be obtained.

The embodiments described above are all examples of the semiconductor device of the present invention and its manufacturing method, and do not limit the present invention. For example, a polycrystalline silicon film was used as the base film for selectively growing the wiring material.
Other materials such as tungsten, aluminum, titanium, etc. can be used. In addition, when a polycrystalline silicon film is used as the base film, the wiring material can be aluminum, molybdenum, etc. in addition to tungsten.
Tungsten side or the like may also be used.

Furthermore, the BPSG film 4 corresponding to the first interlayer insulating film shown in FIG. 1B and the silicon nitride film 7 corresponding to the second interlayer insulating film are made of different materials. Although it is not always necessary to change the material, the following effects can be obtained by changing the material in this way. As shown in FIG. 1c, the patterns of the patterned silicon nitride film 7a and the polycrystalline silicon film 6a often deviate slightly, and a portion of the surface of the BPSG film 4 is exposed. In such cases, since the materials are different, the etching conditions are different, and the exposed portion of the BPSG film 4 is not removed when the silicon nitride film 7 is etched.

〔Effect of the invention〕

As explained above, in the method for manufacturing a semiconductor device of the present invention, wiring is formed on the surface of a base film patterned on an interlayer insulating film according to a wiring pattern, by selectively growing a wiring material using this base film as a nucleus. Therefore, fine and flat pattern wiring can be formed with good controllability.

Further, since the interlayer insulating film is formed between the wirings without creating any cavities, the semiconductor device according to the present invention can maintain high reliability over a long period of time.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of each step showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of each step showing a method of manufacturing a semiconductor device according to a second example of the present invention, FIG. 3 is a cross-sectional view showing each step of a conventional semiconductor device manufacturing method, and FIG. 4 is a cross-sectional view of a semiconductor device manufactured by the conventional manufacturing method. 1...Silicon substrate, 2...n ⁺ type diffusion layer, 3
...Silicon oxide film, 4...BPSG film, 5...Contact hole, 6,...Undoped polycrystalline silicon film, 6a, 16a, 26a...Arsenic-doped polycrystalline silicon film, 7, 7a, 17a, 27a... …
Silicon nitride film, 8...first tungsten wiring, 9, 19...silicon oxide film, 10...second
aluminum wiring, 15, 25... through hole, 18... second tungsten wiring, 21...
First aluminum wiring, 22...Silicon oxide film, 23...Through hole, 24...Cavity, 26
...Second aluminum wiring, 27...PSG passivation film, 28...Third tungsten wiring.

Claims (1)

[Scope of Claims] 1. A first interlayer insulating film formed on a conductive region and provided with a contact hole corresponding to the conductive region, and a line pattern deposited on the first interlayer insulating film. A base film made of a material that is a growth nuclide for a wiring material and patterned according to the method, a wiring formed by selectively growing the wiring material only on the base film, and a wire buried between the wirings. A semiconductor device comprising: a second interlayer insulating film. 2. A step of forming a diffusion layer on the surface of the semiconductor substrate, a step of forming a first interlayer insulation film on the entire surface of the semiconductor substrate, and a step of opening a contact hole corresponding to the diffusion layer in the first interlayer insulation. a step of forming a base film made of a material that will become a growth nuclide for a wiring material over the entire surface; a step of patterning the base film according to a wiring pattern; a step of forming a second interlayer insulating film over the entire surface; patterning the second interlayer insulating film according to the wiring pattern to expose the surface of the base film; and forming a wiring by selectively growing the wiring material only on the exposed base film. A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 2, wherein the base layer is made of polycrystalline silicon. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the base film is polycrystalline silicon, and the wiring material is made of any one of tungsten, aluminum, molybdenum, and tungsten silicide. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the base film is made of one of tungsten, aluminum, and titanium. 6. Forming a diffusion layer on the surface of the semiconductor substrate, forming a first interlayer insulating film on the entire surface of the semiconductor substrate, and opening a contact hole corresponding to the diffusion layer in the first interlayer insulating film. The first step consists of a hole forming process and a material that becomes a growth nuclide for the wiring material.
a step of forming a base film on the entire surface, a step of patterning the first base film according to the first wiring pattern, a step of forming a second interlayer insulating film on the entire surface, and a step of patterning the first base film according to the first wiring pattern. patterning the second interlayer insulating film to expose the surface of the first base film; and selectively growing the wiring material only on the exposed first base film to form a first wiring. forming a third interlayer insulating film on the entire surface; forming a contact hole in the third interlayer insulating film corresponding to the first wiring; and forming a second interlayer insulating film on the entire surface. forming a base film, patterning the second base film according to the second wiring pattern, forming a fourth interlayer insulating film on the entire surface, and patterning the fourth base film according to the second wiring pattern. It is characterized by comprising the steps of patterning the interlayer insulating film to expose the surface of the second base film, and selectively growing the wiring material only on the exposed second base film. A method for manufacturing a semiconductor device.