TWI555122B - Interconnection of semiconductor device and fabrication method thereof - Google Patents

Description

Method for preparing interconnect structure of semiconductor component

The present invention relates to the field of interconnect structure of a semiconductor element, and more particularly to an interconnect structure in which a trench overlap is not over-etched and a method of fabricating the same.

As the integration of integrated circuits (ICs) continues to increase and the feature size continues to decrease, the interconnect line width and geometry of semiconductor components are becoming smaller and smaller. In general, the individual semiconductor elements in the integrated circuit are electrically connected to each other by the contact plug and the interconnect structure. Therefore, the plug structure and its process are becoming more and more important in the next generation of semiconductor manufacturing.

Due to the current process capability of the semiconductor back end of the line (BEOL), the current technology still cannot meet the requirements of high aspect ratio (HAR) contact hole etching process and related process integration technology. In order to overcome these process obstacles, the industry is gradually making the required component patterns by means of double patterning (developing-etching-developing-etching, 2P2E). However, when the trenches are formed by the double patterning technique to form the first direction and the second direction, the bottom of the intersection of the first direction trench and the second direction trench is usually over-etched, and with the area Differently (for example, at the center of the wafer or at the edge of the wafer), the etching profile and the degree of overetching at the intersection will also vary, which is not conducive to the stability of the process.

Accordingly, there is a need for an improved interconnect structure and method of making the same to overcome the above disadvantages.

It is an object of the present invention to provide an interconnect structure of a semiconductor device and a method of fabricating the same, which can solve the problem of excessive etching of the bottom of a trench interface in the prior art.

According to a preferred embodiment of the present invention, there is provided a method of fabricating an interconnect structure of a semiconductor device, comprising the following steps. First, a substrate is provided on which an insulating layer is formed. After forming at least one first trench extending along the first direction in the insulating layer, a first conductive material is filled into the first trench. A patterned mask is formed to expose a portion of the first conductive material. Finally, at least one second trench extending along the second direction is formed in the insulating layer, wherein the second trench is overlapped with the first trench portion.

According to another preferred embodiment of the present invention, there is provided a method of fabricating an interconnect structure of a semiconductor device, comprising: providing a substrate on which an insulating layer is formed. Then, at least one first mask process is performed to form at least one first trench extending along the first direction in the insulating layer. A first conductive material is then filled into the first trench. And performing at least one second mask process to form at least one second trench extending along the second direction in the insulating layer, wherein the second trench overlaps with the first trench portion. Finally, a second conductive material is filled into the second trench.

According to still another preferred embodiment of the present invention, there is provided an interconnect structure of a semiconductor element comprising the following composition. A substrate having an insulating layer disposed thereon. At least one first wire disposed in the insulating layer and extending along a first direction. At least one second wire disposed in the insulating layer and extending along a second direction, wherein the second wire is interlaced with the first wire. And a first conductive layer between the first wire and the second wire, wherein the first conductive layer is disposed on the sidewall of the first wire and directly contacts the first wire.

Therefore, the present invention first forms a first wire extending along the first direction and uses the first wire as an etch mask to form a second trench. Finally, the second conductive material is filled in the second trench to form a second wire extending along the second direction, so that the target layer where the first trench overlaps with the second trench is not over-etched, so that The yield of the connection structure can be greatly improved.

The present invention will be described in detail with reference to the preferred embodiments of the invention,

1 to 8 are schematic views showing the structure of a wiring structure for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention. First, please refer to FIG. 1 and FIG. 2, which is a plan view of a preferred embodiment of the present invention; and FIG. 2 is a cross-sectional view taken along line 2-2' of FIG. As shown in FIGS. 1 and 2, the target layer 3, the insulating layer 7, and the first patterned mask layer 8 are formed on the substrate 1. Wherein, the substrate 1 may comprise a semiconductor substrate, such as a germanium substrate, a germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, etc.; the target layer 3 may have a plurality of components to be electrically connected 6 a dielectric layer, wherein the dielectric layer can be an interlayer dielectric layer (ILD) or an inter-metal dielectric layer (IMD), and the electrical connection element 6 can be a source/drain, a gate structure, a doped region , conductive plugs or wires, etc. Therefore, the material of the electrical connection element 6 may comprise a single crystal germanium layer, a poly germanium layer, an amorphous germanium layer, a metal germanide layer or a metal layer, etc.; the insulating layer 7 may comprise germanium dioxide or a low dielectric constant material, etc. The dielectric material can be obtained, for example, by a thermal oxidation method, a high density plasma chemical vapor deposition (HDPCVD) or a sub-atmospheric chemical vapor deposition (SACVD) process. In this embodiment, the target layer 3 and the insulating layer 7 are preferably provided with a cap layer 5, which can be used as an etch stop layer in the subsequent process to protect the to-be-connected component 6.

According to the invention, the first patterned mask layer 8 corresponds to a first mask pattern A which exposes a portion of the insulating layer 7 and extends it along the first direction x. Therefore, in the subsequent process, the first patterned mask layer 8 can be utilized as an etch mask to define a first trench (not shown). The first patterned mask layer 8 may be, for example, a patterned photoresist layer, but is not limited thereto.

Next, please refer to FIG. 3 and FIG. 4, FIG. 3 is a plan view showing the subsequent steps of the preferred embodiment of the present invention; and FIG. 4 is a cross-sectional view taken along line 4-4' of FIG. As shown in FIGS. 3 and 4, after the patterned mask layer 8 is formed on the substrate 1, at least one etching process can be performed, and a plurality of first trenches 9a are formed in the insulating layer 7.

Then, a second patterned mask layer 11 is used as an etch mask to form another first trench 9b by etching. For example, a photoresist coating process may be used to coat the photoresist on the substrate 1 and fill the first trenches 9a, and then perform an exposure, development, baking and curing process to form a second. The mask layer 11 is patterned. The second patterned mask layer 11 corresponds to a first mask pattern B, and a portion of the insulating layer 7 may be exposed and the exposed insulating layer 7 is also extended along the first direction x. Subsequently, the second patterned mask layer 11 is used as an etch mask to define a plurality of first trenches 9b in the insulating layer 7. So far, by the first patterned mask layer 8 and the second patterned mask layer 11, a plurality of first trenches 9 (including the first trenches 9a, 9b) extending along the first direction x can be defined. In other words, the above embodiment utilizes a first mask process (including the first mask pattern A and the first mask pattern B) by means of a double patterning process (developing-etching-developing-etching, 2P2E). And a plurality of first trenches 9 are defined in the first direction x, but are not limited thereto. That is, the present invention may also form the first trenches 9 (including the first trenches 9a, 9b) extending along the first direction x by using only one-time development, etching or 2P1E.

In addition, in the present embodiment, when forming the first trenches 9a, 9b, it is preferable to separately perform a dry etching process to etch the insulating layer 7 to stop on the surface of the cap layer 5, and then adjust the etching parameters or use a wet etching to At the same time, the cover layer 5 is etched through and the underlying electrical connection element 6 is exposed. But no restrictions.

After the second patterned mask layer 11 is removed, a plurality of first trenches 9 (including the first trenches 9a, 9b) extending along the first direction x are formed in the insulating layer 7 and the cap layer 5, and each The first trench 9 exposes a portion of the target layer 3 and the corresponding electrical connection component 6. Next, as shown in FIG. 5, FIG. 5 is a schematic cross-sectional view showing the first trench 9 filled with the first conductive material 13. For example, the first conductive material 13 is filled in the first trench 9 and electrically connected to the corresponding to-be-connected component 6 in the target layer 3 by a planarization process such as deposition and chemical mechanical polishing. The composition of the first conductive material 13 may include tungsten, copper, aluminum or gold, and the conductive layer may be selectively formed on the surface of each of the first trenches 9 before being filled in the first conductive material 13 (Fig. Not shown) to improve the growth rate or adhesion of the first conductive material 13. For example, when the first conductive material 13 is selected from tungsten metal, the conductive layer may be selected from the group consisting of titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). In addition, as the barrier layer; in addition, if the first conductive material 13 is selected from copper metal, the conductive layer may further comprise a copper seed seed (not shown) which promotes copper growth. So far, the substrate 1 has a plurality of first wires 17 extending along the first direction x, and the surface of each of the first wires 17 is substantially aligned with the surface of the insulating layer 7. In addition, according to another embodiment of the present invention, a cap layer (not shown), such as an insulating layer such as tantalum oxide or tantalum nitride, may be selectively formed to cover the surfaces of the first conductive line 17 and the insulating layer 7. The surface of the first wire 17 is not over-etched or diffused in subsequent processes.

After the completion of the first wire 17, the manner in which the second wire is prepared will be described below. As shown in FIGS. 6 to 8, FIG. 6 to FIG. 8 are schematic plan views showing the preparation of the second wire. First, as shown in FIGS. 6 and 7, a second mask process is sequentially performed to form a plurality of second trenches 25 extending in the second direction y in the insulating layer 7. The detailed steps are described as follows: First, a third patterned mask layer 23, such as a patterned photoresist layer, is formed to expose portions of each of the first wires 17 and the insulating layer 7. Next, the third patterned mask layer 23 and the first conductive line 17 are used as an etch mask, and the insulating layer 7 and the cap layer 5 not covered by the third patterned mask layer 23 are etched by one or more etching processes. Until a portion of the target layer 3 is exposed. At this point, a plurality of second trenches 25 extending along the second direction y are formed, and the second direction y is not parallel to the first direction x. Thus, each of the second trenches 25 partially overlaps with each of the first trenches 9 (in which case the first trenches 9 are filled with the first conductive material 13).

According to the above, one of the features of the present invention is that the first trench 9 and the second trench 25 are formed in a temporal difference, that is, the present invention is formed after the first trench 9 is formed and the first conductive material 13 is filled. Then, the second trench 25 is etched, so that the target layer 3 at the interface between the first trench 9 and the second trench 25 is not over-etched. It should be noted that, for convenience of description, the above embodiment for forming the second trench 25 is a one-time development and etching method, but it is preferable to use a double patterning process (developing-etching-developing-etching). The method of 2P2E) forms the second trenches 25 extending along the second direction y. This can be known by a person skilled in the art by referring to the processes of the first trenches 9a and 9b, and therefore will not be described again.

After completing the second trench 25 described above, and referring to FIG. 8, a schematic diagram of the second trench 25 filled with the second conductive material 30 is illustrated. For example, a deposition process such as deposition and chemical mechanical polishing may be performed, and the second conductive material 30 is filled in each of the second trenches 25 to form a plurality of second wires 27. The material and formation of the second wire 27 are similar to those of the first wire 17. For example, the composition of the second electrically conductive material 30 can comprise tungsten, copper, aluminum or gold. Before the second conductive material 30 is filled, a conductive layer (not shown) may be selectively formed on the surface of each of the second trenches 25 to improve the initial growth rate or adhesion of the second conductive material 30. For example, when the second conductive material 30 is selected from tungsten metal, the conductive layer may be selected from the group consisting of titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). In addition, as the barrier layer; in addition, if the second conductive material 30 is selected from copper metal, the conductive layer may further comprise a copper seed layer (not shown) that initiates copper growth. So far, the substrate 1 has a plurality of first wires 17 and second wires 27 extending along the first direction x and the second direction y, respectively, and the top surface of each of the first wires 17 and the top surface of the second wire 27 They are substantially flush with each other and are coplanar with the top surface of the insulating layer 7. Thus far, the interconnect structure 50 of the semiconductor element of one embodiment of the present invention is completed.

It is to be noted that, since the present invention is formed after the first trench 9 is formed and filled with the first conductive material 13, the second trench 25 is etched and filled with the second conductive material 30, and the first conductive material 13 is formed. Before the second conductive material 30, a conductive layer 33, 35 is formed as a barrier layer, an adhesion layer or a seed layer or a combination thereof. Therefore, the first trench 9 extending along the first direction x and the second trench 25 extending along the second direction y are staggered and partially overlapped, and the first wire 17 and the second wire 27 are located in the directions x and y. On the plane, and in direct contact by the conductive layers 33, 35 therebetween for electrical connection. Next, please refer to Fig. 9, which is a schematic cross-sectional view taken along line 9-9' of Fig. 8 according to an embodiment of the present invention. In FIG. 9, the lower side and the side wall of the first wire 17 are covered by the conductive layer 33, and the lower side of the second wire 27 and the side wall are covered by the conductive layer 35, so that the first wire 17 and the second wire 27 are in the lateral direction. The upper layer is directly contacted and electrically connected by the conductive layer 33 and the conductive layer 35. According to an embodiment of the present invention, if the first conductive line 17 and the second conductive line 27 are both formed by a tungsten metal deposition and polishing process, the first conductive material 13 and the second conductive material 30 are made of tungsten metal, and The conductive layer 33 and the conductive layer 35 may preferably include a barrier layer such as titanium/titanium nitride or tantalum/tantalum nitride, but are not limited thereto. Further, according to other embodiments, the compositions of the first conductive material 13 and the second conductive material 30 are not necessarily the same. For example, when the composition of the first conductive material 13 is tungsten metal, the composition of the second conductive material 30 may include a metal such as aluminum, gold or copper, and vice versa. Furthermore, the compositions of the conductive layer 33 and the conductive layer 35 are not necessarily the same.

Referring to Figure 10, which is another preferred embodiment of the present invention, it is still a schematic cross-sectional view taken along line 9-9' of Figure 8. The main difference between the wiring structures in FIG. 10 and FIG. 9 is that at least one of the first wire 17 and the second wire 27 of FIG. 10 is obtained by a damascene process, preferably, the two For a double inlay process. Therefore, only the main differences will be described below, and other similar steps can be referred to the embodiments described above. First, a first mask process is performed, and a plurality of first trenches 9 are etched in the insulating layer 7 and the cap layer 5 along the first direction x to expose the corresponding electrical connection elements 6 in the target layer 3, and then The conductive layer 33 and the first conductive material 13 are filled to form the conductive plugs 26. Then, the second mask process is performed, and only a plurality of second trenches 25 extending in the second direction y are etched in the insulating layer 7, and then the conductive layer 35 and the second conductive material 30 are filled to form the wires 29. Thus, the dual damascene structure as shown in Fig. 10 is completed. Similarly, in another preferred embodiment, after the first trench 9 is formed and the conductive layer 33 and the first conductive material 13 are sequentially filled, the second trench 25 is etched and sequentially filled with the conductive layer 35. And the second conductive material 30, so that the first trench 9 extending along the first direction x and the second trench 25 extending along the second direction y are staggered and partially overlapped, and the conductive layer 33 and the conductive layer therebetween 35 and direct contact for electrical connection. Wherein, the conductive plug 26 and the wire 29 are located on a plane formed by the directions x, y (the surface of the parallel substrate 1). If integrated into the copper dual damascene process, the first conductive material 13 and the second conductive material 30 are composed of copper metal, and the conductive layer 33 and the conductive layer 35 preferably include titanium/titanium nitride or tantalum/tantalum nitride. The barrier layer and the copper seed layer are, but are not limited to. In addition, the compositions of the first conductive material 13 and the second conductive material 30 are not necessarily the same, and the compositions of the conductive layer 33 and the conductive layer 35 are not necessarily the same.

It should be noted that each of the first wires 17 or the second wires 27 of the above embodiments can be used as a contact plug or slot contact to directly contact and electrically connect the to-be-connected in the target layer 3. In addition to the component 6 (eg, source/drain or gate structure), each of the first wires 17 or the second wires 27 may also serve as a 0th metal layer (M0) to directly contact a conductive plug 6 by The conductive plug 6 is electrically connected to other regions in or below the target layer 3. In addition, the interconnect structure 50 can also serve as one of the interconnect layers (or referred to as the first metal layer (M1), the second metal layer (M2), etc.) and utilize the via The plug 6 is electrically connected to other interconnect layers. Therefore, the interconnect structure 50 of the present invention can be applied to electrically connect NMOS, PMOS, resistor, diode element, photosensitive device or Bipolar Junction Transistor (BJT). Type of semiconductor component.

In summary, the present invention provides an interconnect structure and a method for fabricating the same, the main feature of which is that the first mask process is performed first, at least one first trench is etched in the first direction x, and then in the first trench. After filling the first conductive material to form the first conductive line, the second mask process is further performed, at least one second trench is etched in the second direction y, and finally the second conductive material is filled to form the second conductive line. Therefore, the first trench extending along the first direction x and the second trench extending along the second direction y are staggered and partially overlapped, and the first wire and the second wire are in a plane formed by the directions x, y (parallel substrate The surface is directly contacted to be electrically connected by a conductive layer each serving as a barrier layer, an adhesion layer, or a seed layer. In other words, while the second trench is formed, the first trench is filled with the first conductive material, so that the target layer at the junction of the first trench and the second trench is not over-etched, so that the interconnect structure The yield can be greatly improved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1. . . Base

3. . . Target layer

5. . . Cover

6. . . Electrical connection component

7. . . Insulation

8. . . First patterned mask layer

9. . . First ditches

9a. . . First ditches

9b. . . First ditches

11. . . Second patterned mask layer

13. . . First conductive material

17. . . First wire

twenty three. . . Third patterned mask layer

25. . . Second ditches

26. . . Conductive plug

27. . . Second wire

29. . . wire

30. . . Second conductive material

33. . . Conductive layer

35. . . Conductive layer

50. . . Inline structure

2-2’. . . Section line

4-4’. . . Section line

9-9’. . . Section line

A. . . First mask pattern

B. . . First mask pattern

x. . . First direction

y. . . Second direction

1 to 8 are schematic views showing an internal wiring structure for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention, wherein:

1 and 2 are respectively a plan view and a cross-sectional view showing a target layer, an insulating layer and a patterned mask layer formed on a substrate;

3 and 4 are respectively a plan view and a cross-sectional view showing a plurality of first trenches formed on a substrate;

Figure 5 is a schematic cross-sectional view showing the first trench filled with the first conductive material;

6 to 8 are schematic plan views showing the preparation of the second wire.

FIG. 9 is a cross-sectional view showing the junction of a first wire and a second wire of an interconnect structure according to a preferred embodiment of the present invention;

FIG. 10 is a cross-sectional view showing the junction of a first wire and a second wire of an interconnect structure obtained by a dual damascene process according to a preferred embodiment of the present invention.

1. . . Base

3. . . Target layer

6. . . Electrical connection component

13. . . First conductive material

17. . . First wire

27. . . Second wire

30. . . Second conductive material

33. . . Conductive layer

35. . . Conductive layer

Claims (20)

A method for fabricating an interconnect structure of a semiconductor device, comprising: forming an insulating layer on a substrate; forming at least one first trench extending along a first direction in the insulating layer; filling a first conductive material Inserting into the first trench; forming a patterned mask layer exposing a portion of the insulating layer and a portion of the first conductive material; forming at least one second trench extending along a second direction in the insulating layer The at least one second trench intersects with the at least one first trench portion. The manufacturing method of claim 1, wherein after forming the second trench, further comprising the step of filling a second conductive material into the second trench. The manufacturing method of claim 2, wherein the second conductive material in the second trench and the first conductive material in the first trench form a dual damascene structure. The manufacturing method of claim 2, wherein the composition of the second conductive material is different from the composition of the first conductive material. The manufacturing method of claim 2, wherein the composition of the first conductive material and the second conductive material comprises tungsten, copper, aluminum or gold. The manufacturing method of claim 1, wherein the filling of the first conductive material into the first trench further comprises the step of filling a conductive layer into the first trench. The manufacturing method of claim 1, wherein the filling of the second conductive material into the second trench further comprises the step of filling a conductive layer into the second trench. A method for fabricating an interconnect structure of a semiconductor device, comprising: forming an insulating layer on a substrate; performing a first mask process to form at least one first extending along a first direction in the insulating layer a trench; a first conductive material is filled into the at least one first trench; a second mask process is performed, and at least one second trench extending along a second direction is formed in the insulating layer, wherein the at least one The second trench is interleaved with the at least one first trench portion; and a second conductive material is filled into the second trench. The manufacturing method of claim 8, wherein at least one of the first mask process and the second mask process is a double patterning process. The manufacturing method of claim 8, wherein the composition of the second conductive material is different from the composition of the first conductive material. The manufacturing method of claim 8, wherein the filling of the first conductive material into the first trench further comprises the step of filling a conductive layer into the first trench. The manufacturing method of claim 8, wherein the filling of the second conductive material into the second trench further comprises the step of filling a conductive layer into the second trench. The manufacturing method of claim 8, wherein the second conductive material in the second trench and the first conductive material in the first trench form a dual damascene structure. The manufacturing method of claim 8, wherein the composition of the first conductive material and the second conductive material comprises tungsten, copper, aluminum or gold. The manufacturing method of claim 8, wherein the first direction and the second direction are not parallel to each other. An interconnect structure of a semiconductor device, comprising: a substrate on which an insulating layer is disposed; at least one first wire disposed in the insulating layer and extending along a first direction; at least one disposed on the insulating layer a second wire extending inside and in a second direction, The second wire is interlaced with the first wire, and a top surface of the first wire and a top surface of the second wire are substantially aligned; and a first space between the first wire and the second wire a conductive layer, wherein the first conductive layer is disposed on and directly contacts a sidewall of the first wire. The structure of claim 16, further comprising a second conductive layer between the first wire and the second wire, wherein the second conductive layer is disposed on a sidewall of the second wire and directly contacts the The first conductive layer. The structure of claim 16, wherein the top surface of the first wire or the top surface of the second wire is substantially flush with the top surface of the insulating layer to be coplanar. The structure of claim 16, wherein the composition of the first wire is different from the composition of the second wire. The structure of claim 16, wherein the conductive layer is selected from the group consisting of a copper seed, titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). ) the group consisting of.