TW200707646A - Semiconductor device and a method of manufacturing the same - Google Patents
Semiconductor device and a method of manufacturing the sameInfo
- Publication number
- TW200707646A TW200707646A TW095122398A TW95122398A TW200707646A TW 200707646 A TW200707646 A TW 200707646A TW 095122398 A TW095122398 A TW 095122398A TW 95122398 A TW95122398 A TW 95122398A TW 200707646 A TW200707646 A TW 200707646A
- Authority
- TW
- Taiwan
- Prior art keywords
- insulating film
- fuse
- barrier insulating
- semiconductor device
- manufacturing
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
Abstract
In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005197939A JP2007019188A (en) | 2005-07-06 | 2005-07-06 | Semiconductor integrated circuit device and its manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200707646A true TW200707646A (en) | 2007-02-16 |
TWI380404B TWI380404B (en) | 2012-12-21 |
Family
ID=37597735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095122398A TW200707646A (en) | 2005-07-06 | 2006-06-22 | Semiconductor device and a method of manufacturing the same |
Country Status (4)
Country | Link |
---|---|
US (5) | US7419901B2 (en) |
JP (1) | JP2007019188A (en) |
CN (1) | CN100573871C (en) |
TW (1) | TW200707646A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI555122B (en) * | 2012-05-11 | 2016-10-21 | 聯華電子股份有限公司 | Interconnection of semiconductor device and fabrication method thereof |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007019188A (en) * | 2005-07-06 | 2007-01-25 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
US7586132B2 (en) * | 2007-06-06 | 2009-09-08 | Micrel, Inc. | Power FET with low on-resistance using merged metal layers |
US7956466B2 (en) | 2008-05-09 | 2011-06-07 | International Business Machines Corporation | Structure for interconnect structure containing various capping materials for electrical fuse and other related applications |
US8772156B2 (en) * | 2008-05-09 | 2014-07-08 | International Business Machines Corporation | Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications |
US7893520B2 (en) * | 2008-05-12 | 2011-02-22 | International Business Machines Corporation | Efficient interconnect structure for electrical fuse applications |
KR101198758B1 (en) * | 2009-11-25 | 2012-11-12 | 엘지이노텍 주식회사 | Vertical structured semiconductor light emitting device and method for producing thereof |
US8530320B2 (en) * | 2011-06-08 | 2013-09-10 | International Business Machines Corporation | High-nitrogen content metal resistor and method of forming same |
US20130299993A1 (en) * | 2012-05-11 | 2013-11-14 | Hsin-Yu Chen | Interconnection of semiconductor device and fabrication method thereof |
US9087841B2 (en) * | 2013-10-29 | 2015-07-21 | International Business Machines Corporation | Self-correcting power grid for semiconductor structures method |
JP6448424B2 (en) * | 2015-03-17 | 2019-01-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US9455261B1 (en) | 2015-07-10 | 2016-09-27 | Micron Technology, Inc. | Integrated structures |
TWI590350B (en) * | 2016-06-30 | 2017-07-01 | 欣興電子股份有限公司 | Method for manufacturing circuit redistribution structure and circuit redistribution structure unit |
KR102616489B1 (en) | 2016-10-11 | 2023-12-20 | 삼성전자주식회사 | Method for fabricating semiconductor device |
US20190169837A1 (en) * | 2017-12-02 | 2019-06-06 | M-Fire Suppression, Inc. | Wild-fire protected shed for storage and protection of personal property during wild-fires |
US20190169841A1 (en) * | 2017-12-02 | 2019-06-06 | M-Fire Suppression, Inc. | Wild-fire protected shed for storage and protection of personal property during wild-fires |
JP7055109B2 (en) * | 2019-01-17 | 2022-04-15 | 三菱電機株式会社 | Semiconductor device |
CN110047799A (en) * | 2019-04-28 | 2019-07-23 | 上海华虹宏力半导体制造有限公司 | The manufacturing method and semiconductor devices of semiconductor devices |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6291891B1 (en) * | 1998-01-13 | 2001-09-18 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and semiconductor device |
US6111301A (en) * | 1998-04-24 | 2000-08-29 | International Business Machines Corporation | Interconnection with integrated corrosion stop |
JP2001085526A (en) * | 1999-09-10 | 2001-03-30 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JP3670552B2 (en) * | 2000-03-27 | 2005-07-13 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US6440833B1 (en) * | 2000-07-19 | 2002-08-27 | Taiwan Semiconductor Manufacturing Company | Method of protecting a copper pad structure during a fuse opening procedure |
JP2002164428A (en) * | 2000-11-29 | 2002-06-07 | Hitachi Ltd | Semiconductor device and its manufacturing method |
JP4523194B2 (en) * | 2001-04-13 | 2010-08-11 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
JP2003017570A (en) | 2001-07-02 | 2003-01-17 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
JP2003124307A (en) | 2001-10-15 | 2003-04-25 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
JP2003142485A (en) * | 2001-11-01 | 2003-05-16 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
US7067897B2 (en) * | 2002-02-19 | 2006-06-27 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP3588612B2 (en) | 2002-02-19 | 2004-11-17 | 株式会社東芝 | Semiconductor device |
US7042095B2 (en) * | 2002-03-29 | 2006-05-09 | Renesas Technology Corp. | Semiconductor device including an interconnect having copper as a main component |
JP4250006B2 (en) * | 2002-06-06 | 2009-04-08 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP3779243B2 (en) * | 2002-07-31 | 2006-05-24 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
JP3898133B2 (en) * | 2003-01-14 | 2007-03-28 | Necエレクトロニクス株式会社 | A method of forming a SiCHN film. |
US7094683B2 (en) * | 2003-08-04 | 2006-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual damascene method for ultra low K dielectrics |
US7018917B2 (en) * | 2003-11-20 | 2006-03-28 | Asm International N.V. | Multilayer metallization |
JP4673557B2 (en) * | 2004-01-19 | 2011-04-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP2007019188A (en) * | 2005-07-06 | 2007-01-25 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
-
2005
- 2005-07-06 JP JP2005197939A patent/JP2007019188A/en active Pending
-
2006
- 2006-06-16 US US11/453,897 patent/US7419901B2/en active Active
- 2006-06-22 TW TW095122398A patent/TW200707646A/en not_active IP Right Cessation
- 2006-07-04 CN CNB2006100957511A patent/CN100573871C/en active Active
-
2008
- 2008-04-14 US US12/102,532 patent/US7602040B2/en active Active
-
2009
- 2009-09-21 US US12/564,043 patent/US7968966B2/en active Active
-
2011
- 2011-03-25 US US13/071,546 patent/US8269309B2/en not_active Expired - Fee Related
-
2012
- 2012-08-28 US US13/597,129 patent/US8686538B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI555122B (en) * | 2012-05-11 | 2016-10-21 | 聯華電子股份有限公司 | Interconnection of semiconductor device and fabrication method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN100573871C (en) | 2009-12-23 |
US7419901B2 (en) | 2008-09-02 |
US20100013046A1 (en) | 2010-01-21 |
US8269309B2 (en) | 2012-09-18 |
CN1893076A (en) | 2007-01-10 |
US7968966B2 (en) | 2011-06-28 |
TWI380404B (en) | 2012-12-21 |
US20110169128A1 (en) | 2011-07-14 |
US20120319235A1 (en) | 2012-12-20 |
US8686538B2 (en) | 2014-04-01 |
JP2007019188A (en) | 2007-01-25 |
US20070026664A1 (en) | 2007-02-01 |
US20080211103A1 (en) | 2008-09-04 |
US7602040B2 (en) | 2009-10-13 |
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Legal Events
Date | Code | Title | Description |
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MM4A | Annulment or lapse of patent due to non-payment of fees |