KR100268911B1 - Capacitor of semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A capacitor of a semiconductor and a method for making the same are provided to make a high-integration degree by increasing a charging capacitance of a capacitor and a reliability of a device. CONSTITUTION: A plug(23) is connected to either a source or a drain formed on a semiconductor substrate(21). A lower electrode is connected to the plug, a lower end surface is widely patterned as compared to the plug. A high dielectric layer(29) encloses the lower electrode of the capacitor. A capacitor upper electrode(30) is formed on the high dielectric layer(29), and encloses the lower electrode of the capacitor. Both surfaces of the capacitor lower electrode have a predetermined slope. Thereby, a charging capacitance of a capacitor and a reliability of a device are increased.

Description

Capacitor of semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a capacitor and a method for manufacturing the semiconductor device suitable for increasing the charging capacity of the capacitor and improving the reliability of the device.

In general, in accordance with the trend of integration of semiconductor devices, studies have been made to increase the dielectric constant of a capacitor dielectric layer in order to increase the charging capacity of a capacitor in a memory cell, and to improve the surface area of the charging electrode by three-dimensionally improving the structure of the charging electrode. Is actively underway.

As a memory cell proposed as a double three-dimensional capacitor, a stacked capacitor is a structure that is easy to manufacture and suitable for mass production, while increasing charge capacity and confusion of charge information caused by alpha particles. It is advantageous because it can have immunity against.

However, if the density increases to more than 1G bit, it becomes difficult to maintain the area of the charging electrode of the capacitor any more.

Therefore, studies on (BaSr) TiO ₃ have a dielectric constant 10 times higher than that of NO or Ta ₂ O ₅ .

In order to integrate this, it is important to select an appropriate electrode material and barrier metal to prevent contamination of impurities and oxidation of the electrode.

For example, when Pt is used as an electrode, it is possible to reduce the liquid current, while making anisotropic dry etching difficult.

If RuO ₂ is applied to solve this difficulty, the etching current may be easily increased, but the liquid current is increased.

In any case, a barrier metal layer is needed to protect against the reaction of the electrode with the polysilicon plug.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.

The first oxide film 12 is deposited to a thickness of 5000 kV on the semiconductor substrate 11 on which the n ⁺ conductive source and drain diffusion layers are formed.

The first oxide layer 12 may be selectively removed to form contact holes to expose the surface of the semiconductor substrate 11 on which the source and drain diffusion layers are formed.

A p-doped polysilicon film is deposited on the entire surface including the contact hole to a thickness of 3000 Å, and then polished by CMP (Chemical Mechanical Polishing) to form a plug 13 embedded in the contact hole.

Subsequently, as shown in FIG. 1B, TiSi ₂ and TiN are sequentially formed as the low resistance barrier layer 14 on the entire surface including the plug 13.

Subsequently, as shown in FIG. 1C, a first Pt film 15 for capacitor lower electrodes is formed on the low resistance barrier layer 14 to a thickness of 1000 to 2000 kV by a method such as sputtering. As a hard mask thereon, a second oxide film 16 is deposited.

After the second oxide film 16 is selectively removed, the O ₂ / Cl ₂ / Ar gas chemistry is used as shown in FIG. 1D by MERIE (Magnetically Enhanced Reactive Ion Etching) method. The first Pt film 15 and the low resistance barrier layer 14 are selectively removed.

In this case, the low resistance barrier layer 14 is over-etched so that the semiconductor substrate 11 is etched to a predetermined depth.

Subsequently, after the second oxide film 16 is removed, an insulating material is formed on the entire surface of the substrate including the first Pt film 15, as shown in FIG. 1E, and then the low resistance barrier layer 14 is removed. The insulating side wall 17 is formed in the lower end of both sides.

Subsequently, as shown in FIG. 1F, the BST (BaSrTiO ₃ ) is RF sputtered at a temperature of 400 to 500 ° C. as the capacitor dielectric film 18 on the entire surface including the first Pt film 15 and the insulating side wall 17. It is formed to a thickness of 400Å by the method.

Thereafter, as the capacitor upper electrode, the second Pt film 19 is formed to a thickness of 1000 Å.

And heat treatment is performed for 10 minutes at 550 ℃ temperature in N ₂ atmosphere to improve the electrical properties.

Subsequently, although not shown in the drawings, a hard mask oxide film is deposited on the second Pt film 19 and then patterned, and the second Pt film 19 is selectively removed by an etching process using the oxide film as a mask. Then, the capacitor manufacturing process according to the prior art is completed.

However, in the conventional method of manufacturing a capacitor of a semiconductor device, two hard masks must be used to pattern a Pt film, which is a capacitor electrode material, and it is difficult to maintain a constant side slope of the electrode.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a capacitor of a semiconductor device and a method of manufacturing the same, which are advantageous for high integration by increasing charge capacity and improving reliability in a manufacturing process.

Figure 1a to 1f is a cross-sectional view for explaining a capacitor manufacturing method according to the prior art

2 is a structural cross-sectional view for explaining the structure of a semiconductor device capacitor according to the present invention;

3A to 3E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

Explanation of symbols for main parts of the drawings

11,21: semiconductor substrate 13,23: plug

17,25a: insulation side wall 14,26: low resistance barrier layer

18,29: dielectric film 19,30: capacitor upper electrode

The structure of the capacitor of the semiconductor device according to the present invention for achieving the above object is a plug connected to any one of a source and a drain electrode formed on a semiconductor substrate, the plug is connected, the bottom surface is patterned wider than the plug And a capacitor lower electrode of the capacitor, a high dielectric film formed surrounding the capacitor lower electrode, and a capacitor upper electrode formed on the high dielectric film and surrounding the capacitor lower electrode. Forming a contact hole such that any one of the source and drain diffusion layers is exposed after forming a first insulating film on the semiconductor substrate on which the source and drain diffusion layers are formed, and forming a plug in the contact hole; After forming a second insulating film on the front surface including a patterned plug Exposing a sidewall of the patterned second insulating film, forming a cylindrical capacitor lower electrode to be connected to the plug, removing the insulating sidewall, and then forming a high dielectric film; And forming a capacitor upper electrode on the high dielectric film.

Hereinafter, a capacitor of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a capacitor structure of a semiconductor device according to the present invention.

As shown in FIG. 2, a capacitor of a semiconductor device according to the present invention includes a plug 23 connected to a source or drain electrode of a transistor, a cylindrical capacitor lower electrode 28 connected to the plug 23, A dielectric film 29 formed on the capacitor lower electrode 28 and a capacitor upper electrode 30 formed to surround the capacitor lower electrode 28 on the dielectric film 29. .

Here, the bottom surface of the capacitor lower electrode 28 connected to the plug 23 is patterned to be wider than the width of the plug 23.

Referring to the capacitor manufacturing method of the present invention configured as described above are as follows.

3A to 3D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

First, as shown in FIG. 3A, the first insulating film 22 is formed on the semiconductor substrate 21 on which the diffusion layers of the source and the drain of the transistor are formed.

A photoresist (not shown) is applied onto the first insulating film 22, and then patterned by exposure and development processes.

The first insulating layer 22 is selectively removed by an etching process using the patterned photoresist as a mask to form contact holes to expose the surface of the semiconductor substrate 21 of the diffusion layer.

Subsequently, the polysilicon layer is formed on the entire surface of the substrate 21 including the contact hole, and then polished with CMP, or the plug 23 embedded in the contact hole is subjected to an etch back process using plasma such as Cl ₂ or SF ₆ . Form.

As shown in FIG. 3B, the second insulating film 24 is deposited to a thickness of 5000 kPa or less on the entire surface of the substrate 21 including the plug 23.

Thereafter, the second insulating film 24 is selectively removed so that the plug 23 is sufficiently exposed, and then the third insulating film 25 is deposited on the entire surface of the substrate 21 including the second insulating film 24.

Here, the first and second insulating films 22 and 24 are silicon oxide films, and the third insulating film 25 is a silicon nitride film.

The third insulating film 25 is etched back to form insulating side walls 25a on both sides of the second insulating film 24, as shown in Fig. 3C.

The low resistance barrier layer 26 and the capacitor electrode material 27 are sequentially formed on the entire surface of the substrate 21 including the insulating side wall 25a.

Subsequently, when the low resistance barrier layer 26 and the capacitor electrode material 27 are polished by a CMP process, as shown in FIG. 3D, a lower portion of the capacitor including the low resistance barrier layer 26 and the capacitor electrode material 27 is shown. An electrode 28 is formed.

Here, the capacitor electrode material 27 includes Pt.

Subsequently, as shown in FIG. 3E, after the insulating side wall 25a is selectively removed, a dielectric film 29 having a high dielectric constant is deposited on the entire surface of the substrate 21 including the capacitor lower electrode 28.

At this time, as the dielectric film 29, BST (BaSrTiO ₃ ) is used, and is formed to have a thickness of 400 kV using an RF sputtering method at a temperature of 400 to 500 ° C.

When the capacitor electrode material is deposited on the dielectric layer 29 and polished by the CMP process, the capacitor upper electrode 30 is formed to sufficiently surround the capacitor lower electrode 28.

At this time, as the insulating side wall 25a is removed, the capacitor lower electrode 28 is inclined by the inclination of the insulating side wall 25a.

As described above, the capacitor of the semiconductor device and the manufacturing method thereof according to the present invention have the following effects.

First, as a plug material connected to a source or a drain of a transistor, a capacitor electrode can be easily patterned even when an electrode material having low chemical reactivity, such as a Pt film, and a low volatility of a reaction product due to a low volatility, even if a reaction is adopted. Can be.

Second, the storage capacity can be maximized by allowing the dielectric film having a high dielectric constant to surround the lower electrode.

Claims (10)

A plug connected to any one of a source and a drain electrode formed on the semiconductor substrate, A cylindrical capacitor lower electrode connected to the plug and having a lower surface patterned wider than the plug; A high dielectric film surrounding the capacitor lower electrode; And a capacitor upper electrode formed on the high dielectric film and surrounding the capacitor lower electrode. The method of claim 1, Capacitor of a semiconductor device, characterized in that both sides of the capacitor lower electrode has a slope. The method of claim 1, The high dielectric film is a BST (BaSrTiO ₃ ) capacitor of the semiconductor device, characterized in that. The method of claim 1, The capacitor lower electrode is a capacitor of the semiconductor device, characterized in that the laminated structure of the low resistance barrier layer and the capacitor electrode material. Forming a contact hole on the semiconductor substrate on which the source and drain diffusion layers are formed, and then forming a contact hole to expose any one of the source and drain diffusion layers; Forming a plug in the contact hole; Forming a second insulating film on the entire surface including the plug and then patterning the plug to expose the plug; Forming an insulating side wall on a side surface of the patterned second insulating film, and then forming a cylindrical capacitor lower electrode to be connected to the plug; Removing the insulating side wall and forming a high dielectric film; And forming a capacitor upper electrode on the high dielectric film. The method of claim 5, The material of the plug is a method of manufacturing a capacitor of a semiconductor device, characterized in that it comprises polysilicon. The method of claim 5, The first and second insulating films are oxide films, and the insulating side walls are nitride films. The method of claim 5, And the insulating side wall is formed by depositing an insulating material on the entire surface including the patterned second insulating layer and then etching back. The method of claim 5, The capacitor lower electrode is a capacitor manufacturing method of a semiconductor device, characterized in that by depositing the low resistance barrier layer and the capacitor electrode material in sequence and then polished with CMP. The method of claim 5, The capacitor upper electrode is a capacitor manufacturing method of the semiconductor device, characterized in that by depositing a capacitor electrode material by CMP.

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