A7 B7 35l2twfl.doc/002 —404005 五、發明說明（I ) 本發明是有關於一種隔離結構的結構及其製造方法’ 且特別是有關於一種結合區域氧化法（LOCOS)以及淺溝渠 隔離法（Shallow Trench Isolation, STI)之隔離結構與其製 造方法。 元件隔離區係用以防止載子通過基底而在相鄰之元件 間移動，傳統上，元件隔離區形成於稠密的半導體電路中 相鄰的場效電晶體（Field Effect Transistor，FET)間，藉以減 少由場效電晶體產生的電荷洩露（leakage)，此種稠密的半 導體電路例如是動態隨機存取記憶體(DRAMs)。元件隔離 區時常以厚場氧化層的形式延伸形成在半導體基底表面 下，其中最傳統普遍的技術爲矽局部氧化技術(LOCOS)， 其結果如第1圖所示。請參照第1圖，一矽基底100具有 一場氧化物區域102，此場氧化物區域102隔離場效電晶 體1〇1 2及106，各場效電晶體104、106皆具有一源極、汲 極、通道、及在通道上之閘極。此元件係記憶元件之一部 分，而此記憶元件尙包括另外的電路單元，例如，電荷儲 存電容器、場氧化區域102上之導線（wiring lines)及場氧 化層上其他各種導線、接觸窗及電路等。 在形成LOCOS場氧化物區域方面，首先在基底1〇〇表 面上沈積一氮化矽層，再選擇性地蝕刻部份的氮化矽層， 而定義基底100以形成場氧化物區102。場氧化物區102 的形成，在經光罩定義後之基底100置於氧化環境下，而 藉由光罩定義的區域則形成一厚砂氧化物層，此氧化物層 延伸至基底表面的上方與下方。氮化砂的罩幕幾乎不受氧 (請先閱讀背面之注意事項再填寫本頁) I 丨 I I I I 訂!11111_ 轉 經濟部智慧財產局員工消費合作社印製 1 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 3 5 1 2twfl .doc/002 Α7 3 5 1 2twfl .doc/002 Α7 經濟部智慧財產局員工消費合作社印製 Β7 五、發明說明（7 ) 化環境影響’因此場氧化區102的側邊範圍可藉由罩幕決 定，其中，成長的氧化物102削去矽氮化物罩幕的邊緣， 而氧化物遂延著氮化矽的邊緣’延伸至基底100的側邊或 上方。因此，在場氧化區1〇2的邊緣形成鳥嘴(bird，s beak) 區108，如第1圖所示之鳥嘴區108，係爲主要的場氧化 物區102延著基底1〇〇表面延伸的較薄氧化區。 在以LOCOS法生長的場氧化物區102中，鳥嘴區1〇8 將使記憶胞(memory cell)的尺寸與空間減少，故其爲不良 的場氧化物區。而鳥嘴區1〇8厚度較薄，對元件無法提供 足夠的隔離效果，限制了場氧化物區1〇2在元件的可隔離 程度，卻依然佔據了基底的表面區域。因之，爲了提供元 件更高的集積度，使用不同的元件隔離結構是必要的。 而淺溝渠隔離（shallow trench isolation, STI)爲除 LOCOS場氧化法外之另一種隔離結構，第2A圖至第2G 圖係說明一淺溝渠隔離區之製造流程剖面圖。在此製程 中’一熱氧化物層202作爲一墊氧化物層(pad oxide layer) 塗佈在矽基底200上，此墊氧化物層2〇2保護基底的表 面’而在最終閘極氧化物層(gate oxide layer)形成前移去。 再以化學氣相沈積法(CVD)形成一氮化矽層2〇4,接著利用 經定義之光阻層206，以形成在氮化矽層204表面之一植 入罩幕層206，續在此步驟中將離子植入基底，以形成如 隔離井之隔離元件，而其具p/n連接電性。接著移去植入 罩幕206，然後，如第2B圖所示，在氮化矽層204上沈積 一光阻層’接著曝光並選擇性地移除光阻層以形成罩幕 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---Γ —— — — — — — — — I I I I I I I 訂—---I I I I i (請先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 35 12twfl .doc/002 -404005--bz_ 五、發明說明（,） 208 ’再依序蝕刻氮化矽層2〇4、墊氧化物層2〇2、及矽基 底2〇〇,則在基底2〇〇上形成一溝渠210,如第2C圖所示， 之後再移除蝕刻罩幕208。 然後’溝渠210塡滿一矽氧化物層212,而沈積於溝渠 時’使其溢出溝渠，如第2D圖所示。之後，以化學機械 硏磨法（chemical mechanical polishing,CMP)去除氮化矽層 204表面之氧化物層，而以氮化矽層204爲硏磨終點，留 下渠溝區中一氧化物層212a，如第2E圖所示。在化學機 械硏磨法進行時，由於氧化物層212a材質較氮化矽層204 爲軟’因此氧化插塞212a會有輕微的凹入（dishing)現象 214。接著再移去氮化矽層204，留下氧化物層214(第2F 圖）’並再以一氫氟酸溶液浸蝕移去墊氧化物層，如第2G 圖所示。氧化物層212a蝕刻步驟的進行常常引起其過度蝕 刻’而使氧化物層212a表面凹入而低於基底200的表面， 過度蝕刻往往發生在氧化物層2 12a鄰接著基底200表面的 邊緣，造成基底200與溝槽側牆一“肩狀物”（shoulder) 的產生。在後續製程中，在肩狀物區216形成的不良品質 閘極氧化層，將會減低電晶體“打開”的臨限電壓，而引 起頸結效應（kink effect)中不正常的次臨限電流 (subthreshold current)。 而化學機械硏磨法除了在氧化物層212a造成凹入的現 象外，更發現在硏磨後，氧化物層212a上會有微刮痕 (microscratch)的產生，而此亦可能引起隨後元件在操作上 產生許多問題。 5 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 一 (請先閱讀背面之注意事項再填寫本頁) I 裝------ 111111. A7 35 1 2twfl .doc/002 -刪斯- 五、發明說明（¥ ) 有鑑於此，本發明的主要目的之一，就是在解決以 LOCOS形成場氧化層所引起的鳥嘴效應所產生的不良影 響，並增進隔離效果。 本發明之另一目的，就是在解決淺溝渠隔離結構製程 上可能引起的凹入、頸結效應以及微刮痕等問題。 爲達上述之目的，本發明提供一種結合區域氧化法與 淺溝渠隔離法之隔離結構的製造方法，首先在一具有定定 義的硬材料層上形成一第一襯氧化物層，接著在硬材料層 側邊形成硬材料間隙壁。之後再對基底進行一第一熱製 程’續去除硬材料間隙壁，而暴露出基底。在暴露出的基 底形成溝渠’並在溝渠表面形成一第二襯氧化物層。接著 在溝渠中形成一複晶矽層，且複晶矽層表面不低於基底表 面’再對基底進行一第二熱製程，並去除硬材料層，而完 成本發明之隔離結構。 爲達上述之目的，本發明提供一種隔離結構，其包括 一基底；形成在基底表面之一場氧化層；形成在場氧化層 側邊基底之一複晶矽溝渠隔離；以及一絕緣層，包圍複晶 矽溝渠隔離，用以隔離基底與複晶矽溝渠隔離。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係顯示一種習知以局部氧化法形成之場氧化層 隔離結構剖面圖； 第2A圖至第2G圖一種習知淺溝渠隔離結構之製造流 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝----I--—訂---------姨 經濟部智慧財產局員工消費合作社印製 35 1 2twf 1 .doc/002 A7 35 1 2twf 1 .doc/002 A7 經濟部智慧財產局員工消費合作社印製 _4Q4〇ns_E_ 五、發明說明（f) 程剖面圖；以及 第3A圖至第3H圖係顯示根據本發明較佳實施例結合 區域氧化法與淺溝渠隔離法之隔離結構之製造流程剖面 圖。 其中，各圖標號之簡單說明如下： 100、200、300 :基底 102、310a、310b、318a、318b、318c :場氧化層 104、106 :場效電晶體 108 :鳥嘴區 202 :墊氧化物層 204 :氮化矽層 206、208 :光阻層 212、212a、214 :矽氧化物層 302 :硬材料層 308a、308b、308c :硬材料間隙壁 306、314 :襯氧化物層 316 :複晶砂層 實施例 習知技藝中，以區域氧化法形成場氧化物層作爲隔離 結構，易因鳥嘴區而破壞隔離效果，然淺溝渠隔離結構的 形成則可能有氧化物層凹入或微刮痕等現象，而降低元件 可靠度。因此本發明提出一種結合區域氧化法及溝渠隔離 製程的隔離結構，除可避免上述二種隔離結構的問題外， 亦可適用於〇.25μιη以下的半導體製程。如第3A圖至第 3G圖所示，爲一較佳實施例之製程流程剖面圖。 7 ------ I---II — — I I I I ^^ 1111 I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 35 12twfl .doc/〇〇2 404005 A7 ----- 五、發明說明（& ) 請參照第3A圖，在一基底30〇上形成一硬材料層 3〇2 ’例_如以化學氣相沉積法沉積一氮化矽層，而硬材料 層=3〇2經微影蝕刻製程定義後形成開口 3〇4a、3〇4b 、304c ， 暴露出基底300，而開口 3〇4大小決定於隔離結構所需大 小或電路佈局之設計而定。接著，在硬材料層3〇2表面與 暴露出的基底300上形成一襯氧化物層（liner 〇xide layer)306，例如以化學氣相沉積法形成。 如第3B圖所示’再對基底3〇〇沉積一硬材料層，之後， 以硬材料層302上覆蓋之襯氧化物層3〇6爲蝕刻終點，回 蝕刻硬材料層，而在硬材料層3〇2覆有襯氧化物層3〇6的 側壁上形成一硬材料間隙壁3〇8a、3〇8b、3〇8c。回蝕刻硬 材料層3胃0^例如以乾蝕刻之電漿法進行，調整蝕刻氣體成 分，以提高襯氧化物層3〇6與硬材料層之蝕刻選擇率，使 硬材料間隙壁308a、308b、308c得以順利形成。其中，若 因硬材料層302定義的開口 3〇4b、3〇4c較大，如第3八圖 所示，則在硬材料層沉積且進行回蝕刻而形成硬材料間隙 壁308b、308c後’部分的基底3〇〇將暴露出，若因第3A 圖之開口 304a較小時，則形成之硬材料間隙壁3〇8a則如 第3B圖所示，將不會暴露出基底3〇〇。 之後’在暴露出的基底300上形成場氧化層31〇a、 3 10b ’如第3C圖所示，例如將基底300送入氧化爐管中， 在曰水氣的環境下，進行場氧化物層310a、3l〇b的成長。 其中，在第3C圖示中之硬材料間隙壁3〇8a未暴露出基底 3〇〇，故在此未能提供作爲反應物之矽材，故場氧化物層 未能成長於此。 8 本紙張尺度適用中國國豕標準（CNS〉A4規格（21〇 X 297公楚） ^----^--1! i I — I I--^--11------M (請先閱讀背面之注意事項再填寫本頁) A7 35 1 2twfl doc/002 --104005_§z__ 五、發明說明（^) 再如第3D圖所示，去除硬材料間隙壁3〇8a、3〇8b、 308c ’例如以濕蝕刻法去除，其中硬材料間隙壁3〇8a、 308b、308c材料爲氮化矽時，則以熱磷酸（hot Η3Ρ04)作爲 去除硬材料間隙壁308a、3〇8b、3〇8c之蝕刻劑。在去除硬 材料間隙壁308a、308b、308c後，暴露出原本被硬材料間 隙壁308a、308b、308c覆蓋的襯氧化物層306，包括暴露 出場氧化層310a、310b側邊基底300上之襯氧化物層 306 〇 續以硬材料層302與場氧化層310a、310b爲罩幕，以 非等向性蝕刻法蝕刻基底300，而在基底300形成溝渠 312a、312b、312c，如第3E圖所示，即在場氧化層310a、 310b側邊形成溝渠3 12b、3 12c。之後，在溝渠3 12a、312b、 3 lk的基底300表面形成一襯氧化物層314，例如以熱氧 化法形成。接著，對基底300形成一複晶矽層316，複晶 矽層316塡入溝渠312a、312b、312c後，再以場氧化層 312a、3 12b爲蝕刻終點，對複晶矽層3 16進行回蝕刻，使 複晶矽層316之表面至少與基底300之表面同高，如第3F 圖所示。 接著，請參照第3G圖，再以塡入溝渠的複晶矽層316 爲反應物，進行一熱氧化製程，使複晶矽層316上形成一 場氧化物層318a、318b、318c，覆蓋住複晶矽層316。而 如第3G圖所示，此步驟形成的場氧化層318b、318c將與 第3C圖形成之場氧化層310a、310b結合而形成。若在第 3C圖中未形成場氧化層，則在此步驟中仍在複晶矽層316 上形成一場氧化層318a，覆蓋住複晶矽層316。 9 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------1----I I 裝！---—訂！---線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 3 5 1 2twf 1 . doc/002 4Ω4〇η^ Α7 Β7 五、發明說明（$ ) 再去除硬材料層302,例如以濕蝕刻法進行，而暴露出 基底300，完成本發明之隔離結構，如第3H圖所示。 本發明之隔離結構包括，在基底中形成一複晶矽溝渠 隔離，而複晶矽溝渠隔離以襯氧化物層包圍而將複晶矽溝 渠隔離與基底隔開。 另外，本發明之隔離結構更包括在基底上形成一場氧 化層，而在場氧化層側邊基底上形成複晶矽溝渠隔離，其 中複晶矽溝渠隔離以一襯氧化物層包圍，而將基底與複晶 矽溝渠隔離隔開。 本發明溝渠隔離結構之形成未使用化學機械硏磨法， 故可避免習知淺溝渠隔離結構凹入與微刮痕的問題，但仍 可具有溝渠隔離結構所具有的隔離效果以達元件隔離的 功效，且可適用於0.25μιη以下的半導體製程。 本發明同時結合場氧化層與溝渠隔離的形成方式，以 溝渠隔離補足場氧化層隔離效果較差的缺點，且在場氧化 層側邊形成溝渠隔離，而避免場氧化層產生鳥嘴區的情 況。 經濟部智慧財產局員工消費合作社印製 i (請先閱讀背面之注意事項再填寫本頁) 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）A7 B7 35l2twfl.doc / 002 —404005 V. Description of the Invention (I) The present invention relates to a structure of an isolation structure and a method for manufacturing the same ', and more particularly to a combined area oxidation method (LOCOS) and a shallow trench isolation method ( Shallow Trench Isolation (STI) isolation structure and its manufacturing method. The element isolation region is used to prevent carriers from moving between adjacent elements through the substrate. Traditionally, the element isolation region is formed between adjacent field effect transistors (FETs) in dense semiconductor circuits. To reduce charge leakage caused by field effect transistors, such dense semiconductor circuits are, for example, dynamic random access memories (DRAMs). The element isolation area is often formed under the surface of the semiconductor substrate in the form of a thick field oxide layer. The most traditional and popular technology is the silicon local oxidation technology (LOCOS). The results are shown in Figure 1. Please refer to FIG. 1. A silicon substrate 100 has a field oxide region 102. This field oxide region 102 isolates the field effect transistors 102 and 106. Each field effect transistor 104 and 106 has a source and a sink. Pole, channel, and gate on the channel. This element is a part of a memory element, and this memory element does not include other circuit units, such as a charge storage capacitor, wiring lines on the field oxide region 102 and various other wires on the field oxide layer, contact windows and circuits, etc. . In forming a LOCOS field oxide region, a silicon nitride layer is first deposited on the surface of the substrate 100, and then a portion of the silicon nitride layer is selectively etched to define the substrate 100 to form the field oxide region 102. The field oxide region 102 is formed after the substrate 100 defined by the photomask is placed in an oxidizing environment, and the area defined by the photomask forms a thick sand oxide layer that extends above the surface of the substrate. With below. The screen of nitrided sand is almost free of oxygen (please read the precautions on the back before filling this page) I 丨 IIII Order! 11111_ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 2 This paper size applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 3 5 1 2twfl .doc / 002 Α7 3 5 1 2twfl .doc / 002 Α7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Description of the invention (7) Environmental impact 'Therefore, the side range of the field oxide region 102 can be determined by the mask, wherein the grown oxide 102 cuts off the edge of the silicon nitride mask, and the oxide extends along the edge of the silicon nitride' and extends to the substrate 100. Side or above. Therefore, a bird's beak region 108 is formed at the edge of the field oxide region 102. The bird's beak region 108 shown in FIG. 1 is a main field oxide region 102 extending along the substrate 100. Surface extends thinner oxidized area. In the field oxide region 102 grown by the LOCOS method, the bird's beak region 108 will reduce the size and space of the memory cell, so it is a bad field oxide region. The bird's beak region 10 is thinner and cannot provide a sufficient isolation effect for the element, which limits the degree of isolation of the field oxide region 102 in the element, but still occupies the surface area of the substrate. Therefore, in order to provide higher integration of components, it is necessary to use different component isolation structures. Shallow trench isolation (STI) is another isolation structure in addition to the LOCOS field oxidation method. Figures 2A to 2G are cross-sectional views illustrating the manufacturing process of a shallow trench isolation area. In this process, 'a thermal oxide layer 202 is coated on the silicon substrate 200 as a pad oxide layer, and this pad oxide layer 202 protects the surface of the substrate' and finally the gate oxide The gate oxide layer is removed before formation. Then, a silicon nitride layer 204 is formed by a chemical vapor deposition (CVD) method, and then a defined photoresist layer 206 is used to form an implantation mask layer 206 on one of the surfaces of the silicon nitride layer 204. In this step, ions are implanted into the substrate to form an isolation element such as an isolation well, which has p / n connection electrical properties. Then remove the implant mask 206, and then, as shown in FIG. 2B, deposit a photoresist layer on the silicon nitride layer 204, and then expose and selectively remove the photoresist layer to form the mask. 4 paper sizes Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) --- Γ —— — — — — — — — — IIIIIII Order —- IIII i (Please read the precautions on the back before filling this page ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 35 12twfl .doc / 002 -404005--bz_ V. Description of the Invention (,) 208 'Sequentially etch the silicon nitride layer 204 and the pad oxide layer 202 And silicon substrate 200, a trench 210 is formed on the substrate 200, as shown in FIG. 2C, and then the etching mask 208 is removed. The trench 210 is then filled with a silicon oxide layer 212, and when deposited in the trench, it is caused to overflow the trench, as shown in FIG. 2D. After that, the chemical oxide polishing (CMP) method is used to remove the oxide layer on the surface of the silicon nitride layer 204, and the silicon nitride layer 204 is used as the finishing point, leaving an oxide layer 212a in the trench area. As shown in Figure 2E. When the chemical mechanical honing method is performed, since the material of the oxide layer 212a is softer than that of the silicon nitride layer 204, the oxide plug 212a may have a slight dishing phenomenon 214. Then the silicon nitride layer 204 is removed, leaving the oxide layer 214 (Figure 2F) 'and the pad oxide layer is removed by etching with a hydrofluoric acid solution, as shown in Figure 2G. The etching step of the oxide layer 212a often causes its over-etching, which causes the surface of the oxide layer 212a to be recessed and lower than the surface of the substrate 200. Over-etching often occurs at the edge of the oxide layer 212a adjacent to the surface of the substrate 200, causing The generation of a "shoulder" between the substrate 200 and the trench side wall. In subsequent processes, the poor-quality gate oxide layer formed in the shoulder region 216 will reduce the threshold voltage at which the transistor “opens” and cause an abnormal secondary threshold current in the kink effect. (subthreshold current). In addition to the chemical mechanical honing method, in addition to the phenomenon of causing depression in the oxide layer 212a, it is also found that after honing, microscratch will be generated on the oxide layer 212a, which may also cause subsequent components to There are many problems in operation. 5 ^ The paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) I (Please read the precautions on the back before filling this page) I Loading --- 111111. A7 35 1 2twfl .doc / 002-deleted-5. Description of the invention (¥) In view of this, one of the main objectives of the present invention is to solve the adverse effects caused by the bird's beak effect caused by the field oxide layer formed by LOCOS and improve the isolation effect. . Another object of the present invention is to solve the problems of recession, neck knot effect, and micro-scratch that may be caused during the manufacturing process of the shallow trench isolation structure. In order to achieve the above object, the present invention provides a manufacturing method of an isolation structure combining a region oxidation method and a shallow trench isolation method. First, a first lining oxide layer is formed on a hard material layer with a defined definition, and then on the hard material The side of the layer forms a hard material barrier. After that, the substrate is subjected to a first thermal process' to continue to remove the hard material spacers and expose the substrate. A trench is formed on the exposed substrate and a second lining oxide layer is formed on the surface of the trench. Next, a polycrystalline silicon layer is formed in the trench, and the surface of the polycrystalline silicon layer is not lower than the surface of the substrate. Then, a second thermal process is performed on the substrate, and the hard material layer is removed to complete the isolation structure of the invention. To achieve the above object, the present invention provides an isolation structure including a substrate; a field oxide layer formed on the surface of the substrate; a polycrystalline silicon trench isolation formed on the side of the field oxide layer; and an insulating layer surrounding the compound Crystal silicon trench isolation is used to isolate the substrate from the polycrystalline silicon trench. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 It is a cross-sectional view showing a conventional field oxide layer isolation structure formed by a local oxidation method. Figures 2A to 2G show a manufacturing flow of a conventional shallow trench isolation structure. 6 This paper is applicable to China National Standard (CNS) A4 specifications ( 210 X 297 mm) (Please read the precautions on the back before filling out this page) Packing ---- I ---- Order --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 35 1 2twf 1 .doc / 002 A7 35 1 2twf 1 .doc / 002 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs_4Q4〇ns_E_ V. Description of the invention (f) Process sectional views; and Figures 3A to 3H It is a sectional view showing a manufacturing process of an isolation structure combining a region oxidation method and a shallow trench isolation method according to a preferred embodiment of the present invention. The description of each icon number is as follows: 100, 200, 300: substrate 102, 310a, 310b, 318a, 318b, 318c: field oxide layer 104, 106: field effect transistor 108: bird's beak region 202: pad oxide Layer 204: silicon nitride layers 206, 208: photoresist layers 212, 212a, 214: silicon oxide layer 302: hard material layers 308a, 308b, 308c: hard material spacers 306, 314: liner oxide layer 316: complex In the conventional technique of the example of the crystal sand layer, the field oxide layer is formed by the regional oxidation method as the isolation structure, and the isolation effect is easily destroyed by the bird's beak area. However, the formation of the shallow trench isolation structure may have the oxide layer recessed or slightly scratched. Marks, etc., which reduces component reliability. Therefore, the present invention proposes an isolation structure combining a region oxidation method and a trench isolation process. In addition to avoiding the problems of the above two isolation structures, it can also be applied to semiconductor processes below 0.25 μm. As shown in FIG. 3A to FIG. 3G, it is a sectional view of a process flow of a preferred embodiment. 7 ------ I --- II — — IIII ^^ 1111 I (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 35 12twfl .doc / 〇〇2 404005 A7 ----- 5. Description of the Invention & Please refer to Figure 3A to form a hard material on a substrate 30 Layer 302 'Example_ If a silicon nitride layer is deposited by chemical vapor deposition, and the hard material layer = 302 is defined by the lithographic etching process, openings 304a, 304b, and 304c are formed and exposed. The size of the substrate 300 and the opening 304 depends on the required size of the isolation structure or the design of the circuit layout. Next, a liner oxide layer 306 is formed on the surface of the hard material layer 30 and the exposed substrate 300, for example, by a chemical vapor deposition method. As shown in FIG. 3B, 'a hard material layer is deposited on the substrate 300, and then the lining oxide layer 300 covered on the hard material layer 302 is used as the end point of the etching, and the hard material layer is etched back, A hard material partition wall 3008a, 3008b, 3008c is formed on the side wall of the layer 3002 covered with the lining oxide layer 306. The back etching of the hard material layer 3 is performed by, for example, a plasma method of dry etching, and the etching gas composition is adjusted to increase the etching selectivity of the lining oxide layer 306 and the hard material layer, so that the hard material partition walls 308a, 308b , 308c was successfully formed. Among them, if the openings 304b and 304c defined by the hard material layer 302 are large, as shown in FIG. 38, after the hard material layer is deposited and etched back to form the hard material spacers 308b and 308c ' Part of the substrate 300 will be exposed. If the opening 304a in FIG. 3A is small, the hard material partition wall 3008a formed will be as shown in FIG. 3B, and the substrate 300 will not be exposed. Thereafter, 'field oxide layers 31oa, 3 10b are formed on the exposed substrate 300', as shown in FIG. 3C, for example, the substrate 300 is sent into an oxidation furnace tube, and the field oxide is carried out in an environment of water vapor. Growth of layers 310a, 310b. Among them, the hard material spacer 308a shown in the 3C diagram does not expose the substrate 300, so a silicon material as a reactant cannot be provided here, so the field oxide layer cannot grow here. 8 This paper size applies to China's national standard (CNS> A4 specification (21〇X 297)) ^ ---- ^-1! I I — I I-^-11 ------ M (Please read the precautions on the back before filling in this page) A7 35 1 2twfl doc / 002 --104005_§z__ V. Description of the invention (^) Then as shown in Figure 3D, remove the hard material barriers 3 08a, 3 〇8b, 308c 'For example, by a wet etching method, in which the hard material spacers 308a, 308b, and 308c are made of silicon nitride, hot phosphoric acid (hot Η3Ρ04) is used to remove the hard material spacers 308a, 308b. And 3008c. After removing the hard material spacers 308a, 308b, and 308c, the lining oxide layer 306 that was originally covered by the hard material spacers 308a, 308b, and 308c is exposed, including the exposed field oxide layers 310a, 310b. The lining oxide layer 306 on the side substrate 300 continues to use the hard material layer 302 and the field oxide layers 310a and 310b as a mask. The substrate 300 is etched by anisotropic etching to form trenches 312a, 312b, 312c, as shown in FIG. 3E, that is, trenches 3 12b, 3 12c are formed on the sides of the field oxide layers 310a, 310b. After that, in the trenches 3 12a, 312b, 3 lk, A lining oxide layer 314 is formed on the surface of the bottom 300, for example, by a thermal oxidation method. Next, a polycrystalline silicon layer 316 is formed on the substrate 300, and the polycrystalline silicon layer 316 penetrates into the trenches 312a, 312b, and 312c, and is field-oxidized. The layers 312a, 3 12b are the end points of the etching, and the polycrystalline silicon layer 3 16 is etched back so that the surface of the polycrystalline silicon layer 316 is at least as high as the surface of the substrate 300, as shown in FIG. 3F. Next, please refer to 3G As shown in the figure, the polycrystalline silicon layer 316 penetrating the trench is used as a reactant to perform a thermal oxidation process, so that a field of oxide layers 318a, 318b, and 318c is formed on the polycrystalline silicon layer 316, and the polycrystalline silicon layer 316 is covered. As shown in FIG. 3G, the field oxide layers 318b and 318c formed in this step will be formed by combining with the field oxide layers 310a and 310b formed in FIG. 3C. If the field oxide layer is not formed in FIG. 3C, then in this step An oxide layer 318a is still formed on the polycrystalline silicon layer 316, covering the polycrystalline silicon layer 316. 9 ^ The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------- 1 ---- II installed! ----- Order! --- line (Please read the precautions on the back before filling this page) Printed by the Consumer Property Cooperative of the Intellectual Property Bureau 3 5 1 2twf 1 .doc / 002 4Ω4〇η ^ Α7 B7 V. Description of the invention ($) The hard material layer 302 is removed, for example, by wet etching, and the substrate 300 is exposed, The isolation structure of the present invention is completed, as shown in FIG. 3H. The isolation structure of the present invention includes forming a polycrystalline silicon trench isolation in a substrate, and the polycrystalline silicon trench isolation is surrounded by a liner oxide layer to isolate the polycrystalline silicon trench isolation from the substrate. In addition, the isolation structure of the present invention further includes forming a field oxide layer on the substrate, and forming a polycrystalline silicon trench isolation on the substrate on the side of the field oxide layer, wherein the polycrystalline silicon trench isolation is surrounded by a liner oxide layer, and the substrate is Isolated from the polycrystalline silicon trench. The formation of the trench isolation structure of the present invention does not use a chemical mechanical honing method, so the problems of recession and micro-scratching of the shallow trench isolation structure can be avoided, but it can still have the isolation effect of the trench isolation structure to achieve component isolation. Efficiency, and can be applied to semiconductor processes below 0.25μιη. The invention simultaneously combines the formation method of the field oxide layer and the trench isolation to supplement the shortcomings of the poor isolation effect of the field oxide layer with the trench isolation, and forms the trench isolation on the side of the field oxide layer to prevent the field oxide layer from generating a bird's beak. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling out this page) Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. In addition, without departing from the spirit and scope of the present invention, various modifications and retouching can be made. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)