TW434865B - Etching process for reducing the contact resistance in the multi-layer structure - Google Patents
Etching process for reducing the contact resistance in the multi-layer structure Download PDFInfo
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五、發明說明(1) 5 -1發明領域: 本發明係有關於一種減少接觸窗阻值的方法,特別是 有關於在多層結構(mu 11 i - 1 ay er )中減少接觸窗阻值與漏 電流的方法。 發明背景: 在積體電路的製成中各種領域裡,接觸窗蝕刻是—必 備的步驟。例如’以場氧區(f i e 1 d ox i da t i on )分開的金 ( 屬氧化物半導體電晶體(MOS transistor)的多晶石夕閘極 ’上面覆蓋一平坦化的絕緣層或是内介電潛,如蝴磷梦玻 璃(BPSG ),磷矽玻璃(PSG ),旋塗矽玻璃(S0G ),四 氧乙基矽等(TE0S)。為了有效地連接元件中主動區域的 多晶硬閘極,需要在選擇的位置上穿過内連接層。開啟的 接觸窗將由圖案轉移後的金屬來連接。 〇 2 5微米技術要求有低接窗阻值與低漏電流的多層接 =窗製程^由於低氧化物對鈦矽化合物選擇度,目前在磁 %力強型/舌性離子钱刻reactive ic*n etcher; MERIE)氧化物的蝕刻機顯示高的接觸窗阻值 。在接觸窗i虫刻中如果有鈦矽化合物殘留物,會造成較高 的漏電流’一種解決方法是要求額外的栓塞植入(p 1 ug implant )步驟來補償矽接合(juncti〇n )損失,如第一V. Description of the invention (1) 5 -1 Field of the invention: The present invention relates to a method for reducing the resistance value of a contact window, and in particular, to reducing the resistance value of a contact window in a multilayer structure (mu 11 i-1 ay er). Method of leakage current. BACKGROUND OF THE INVENTION In various fields in the fabrication of integrated circuits, contact window etching is a necessary step. For example, "a gold (polycrystalline oxide gate of MOS transistor) separated by a field oxygen region (fie 1 d ox i da ti on)" is covered with a planarized insulating layer or an interposer Electric submersible, such as Butterfly Phosphor Dream Glass (BPSG), Phosphor-Silicon Glass (PSG), Spin-Coated Silica Glass (S0G), Tetraoxyethyl Silicon, etc. (TE0S). In order to effectively connect the polycrystalline hard brake in the active area of the component It is necessary to pass through the interconnecting layer at the selected position. The opened contact window will be connected by the pattern-transferred metal. 〇2 5 micron technology requires a multilayer connection with low window resistance and low leakage current = window process ^ Due to the low selectivity of titanium oxides to silicon compounds, the current etching machines for reactive ic * n etcher (MERIE) oxides exhibit high contact window resistance values. If there is a titanium silicon compound residue in the contact window, a high leakage current will be caused. One solution is to require an additional p 1 ug implant step to compensate for silicon junction loss. As first
五、發明說明(2) 圖所示。 參考第一 A圖,提供—底材1 〇,其中一金屬氧化物 半導體(MOS ) ,形成兩層金 形成一覆蓋廣 物半導體電晶 物半導體電晶 的介電層1 2 contact hole 2 0以形成接 示。然而,由 全钱刻。一種 ,然後使用額 示。因為需要 並且造成較高 再者,這個方 電晶體在底材1 〇的裡面與上面形成。接著 屬石夕化層1 1 2A與1 1 2B,並且在上面 〇 114。114層與112A層是金屬氧化 體的閘極的頂部,而1 1 2 B層是金屬氧化 體的主動區域的頂部。接著,形成一平坦化 0與一光阻層1 4 0 ,並且定義接觸窗洞( )。一種傳統的氧化物的蝕刻機蝕刻介電層 觸窗洞1 3 0A與1 30B ,如第一 B圓所 於較低的選擇比,金屬矽化層1 1 2 B被完 解決方式,钱刻時穿過金屬;ε夕化層1 1 2 B 外的植入來補償石夕接合損失,如第一 C圖所 對N+及P+分別植入,這個步驟需要兩次光阻 的漏電流,然後,形成一層附著層1 5 0。 式的步驟較複雜。 發明目的及概述: 馨於上.述之發明背景中,傳統的接觸窗钱刻技術所產 生的諸多缺點本發明中,提供減少接觸窗阻值與漏電流的 钱刻技術。V. Description of the invention (2) Figure. Referring to FIG. 1A, a substrate is provided, in which a metal oxide semiconductor (MOS) is formed into two layers of gold to form a dielectric layer covering a semiconductor transistor and a semiconductor layer. Formation of instructions. However, carved by full money. One and then use the credit. Because of the need and the high cost, this crystal is formed inside and above the substrate 10. It is next to the oxidized layer 1 1 2A and 1 1 2B, and above 114. The 114 and 112A layers are the top of the gate of the metal oxide, and the 1 1 2 B layer is the top of the active region of the metal oxide. . Next, a planarization 0 and a photoresist layer 14 0 are formed, and a contact window hole () is defined. A conventional oxide etching machine etches the dielectric layer contact holes 1 30A and 1 30B. As the first B circle has a lower selection ratio, the metal silicide layer 1 1 2 B is finished. The solution is worn when the money is carved. Over-metal; implanted outside the epsilon layer 1 1 2 B to compensate for the loss of stone joints, as shown in the first C figure, N + and P + are implanted separately. This step requires two photoresistor leakage currents, and then forms A layer of adhesion 1 50. The procedure is more complicated. Objectives and Summary of the Invention: In the background of the invention described above, many disadvantages caused by the traditional contact window engraving technique are provided in the present invention, which provide the engraving technique for reducing the contact window resistance and leakage current.
第5頁 434865 五、發明說明(3) 本發明的另一目的在係減少 製程成本與化簡步驟。 兩個離子植人步驟來降低 根據以 技術。首先 ’其中一钦 體的閘極上 阻層。在電 在光阻層上 動區域的鈦 而形成接觸 化石夕層也被 conformal) 上所述之目的’本發明提供了 ,提供具有一金屬氧化物半導 化矽層覆蓋在電晶體上而氮化 。然後在底材上形成—氧化石夕 晶體的閘極上與主動區域上, β接著,蝕刻未被光阻層覆蓋 化矽層,同時蝕刻透過閘極上 窗洞。在蝕刻氧化物時,未被 姓刻到閘極上的欽化梦層。最 附著層在接觸窗洞上面形成, 種接觸窗蝕刻 體的底材 體電晶 矽層覆 層’接 將接觸 的氧化 的氮化 光阻層 後’一 蓋在電晶 著是一光 窗洞定義 發層到主 砂層,因 覆蓋的氮 保角( 5-4圖式簡單說明: 第Α圖到第一 C圖顯示一傳統的蝕刻接 ,各步驟的示意圓; ⑷接觸自製種中 圖為本發明各步驟的流程圖的流程圖; f二A圖到第三D圖顯示以本發明蝕 ,各步驟的示意圖。 條蜩固製程中 主要部分之代表符號 1〇 底材 第6頁 五、發明說明(4) 2 0 介 電 層 3 0 金 屬 石夕化 物 層 4 0 光 阻 層 5 0 附 著 層 1 0 0 底 材 1 2 0 介 電 層 1 2 2 絕 緣 層 1 3 0 金 屬 石夕化 物 層 1 4 0 光 阻 層 1 5 0 附 著 層 5-5發明詳細說明: 接下來描述本發明的詳細實施例。但是,應該理解到 本發明可以用其他明顯的實施例來達成。而本發明並不受 限於特殊的實施例。 ^ π ^ —圖係根據本實施例中,一種形成接觸窗的方法的 坦化過程2〇ΐ :ί上形成一内介電屠’並且經過平 問極被一氮化矽層;:—電晶體在底材上形成。電晶體的 步驟,在高密度電▲蝕列=來作為一終止層。接著關鍵的 接蝕刻介電層形成接觸二歲中’用高選擇比的蝕刻劍以直 蝕刻氧化矽與氮化 =^ 0 2。這個蝕刻步驟包含同時 因為餘刻的過程具有高選擇比,沒 $ 7頁Page 5 434865 V. Description of the invention (3) Another object of the present invention is to reduce the process cost and simplify the steps. Two ion implantation steps to lower according to this technique. First, ’one of the barriers on the gate. The contact between the titanium in the moving region of the photoresist layer and the formation of the fossil layer is also described above. The present invention provides a method of providing a metal oxide semiconductive silicon layer overlying a transistor and nitrogen. Into. Then formed on the substrate-on the gate and active area of the stone oxide crystal. Β, then, the silicon layer is not etched by the photoresist layer and etched through the window hole on the gate. When etching the oxide, the Qinhua dream layer that was not engraved on the gate was not etched. The most adherent layer is formed above the contact window hole. The substrate of the contact window etched body is a silicon silicon layer coating which is connected to the oxidized nitrided photoresist layer that is in contact with the contact lens. It is a light window hole that defines the hair Layer to main sand layer, because of the covered nitrogen conformation (5-4) A simple explanation: Figures A to C show a traditional etching connection, the schematic circle of each step; ⑷ contact self-made species Flow chart of each step; Figures 2A to 3D show the schematic diagrams of the steps of etching according to the present invention. Representative symbols of the main part in the strip solidification process 10 substrates page 6 5. Description of the invention (4) 2 0 dielectric layer 3 0 metal oxide layer 4 0 photoresist layer 5 0 adhesion layer 1 0 0 substrate 1 2 0 dielectric layer 1 2 2 insulating layer 1 3 0 metal oxide layer 1 4 0 Photoresist layer 1 5 0 Adhesive layer 5-5 Detailed description of the invention: The detailed embodiments of the invention are described next. However, it should be understood that the invention can be achieved with other obvious embodiments. The invention is not limited Special implementation ^ Π ^ —The diagram is a frank process of a method for forming a contact window according to the present embodiment. Ϊ́: an internal dielectric layer is formed on it and a silicon nitride layer is passed through the planar electrode; The transistor is formed on the substrate. The step of the transistor is to use a high-density electrode as a termination layer. Then the key dielectric layer is formed to contact the two-year-old 'with an etching sword with a high selectivity to straighten Etching silicon oxide and nitride = ^ 0 2. This etching step includes both because the remaining process has a high selection ratio, not $ 7 pages
有過度餘刻的發生,因而少了 後’形成接觸窗的附著層2 〇 中’不同的步驟的適當的條件 D圖解說。 化物半導體場效電晶體,的 或是沉積法或是兩種混合的 0。這層氧化層的最佳厚度 30000埃而最薄為15000埃。 沉積的四氧乙基矽,高密度 石夕’棚碟石夕破璃,常壓化學 化矽,或是其任何習知的形 主要的功能是提供在多層結 以任何傳統的方法形成 B ’都是金屬氧化物半導體 化物層12A與12B的材 例中,金屬矽化物.層1 2 A 场效電晶體的閉極的頂部區 用來作為主動區域的頂部。 二A圖中的底材1〇裡面是 本發明並不重要,並不會因 解本發明。 後續的栓塞植入的步驟。然 3。在第二圖所提到的步驟 將在下面的第三A圖到第三 含有積體電路結構,如金屬氧 底層1 0 0,在上面以氧化法 方式形成一平坦的氧化層1 2 約為2 2 0 0 0埃,但是最厚約為 同時,氧化層12〇也可為用 電槳增益法(HDP )形成的氧化 氣相沉積法(APCVD)形成的氧 成氧化層的方法。這層氧化層 構中的内介電層。 的金屬石夕化物層1 2A與1 2 場效電晶體的一部份。金屬石夕 質基本上為鈦化石夕。在本實施 是用來作為金屬氧化物半導體 域,而金屬石夕化物層1 2 B是 在這裡必須簡略地提到,在第 有元件的結構形成,而這些對 為沒有詳細描速細節而無法理There is an excessive amount of time, so there are fewer conditions suitable for the different steps in 'the formation of the contact layer of the contact window 2'. Semiconductor field-effect transistors, either deposition or mixed 0. The optimal thickness of this oxide layer is 30,000 angstroms and the thinnest is 15,000 angstroms. Deposited tetraoxosilicone, high-density Shi Xi 'Shed Shi Xi broken glass, atmospheric pressure chemical silicon, or any of its known shapes The main function is to provide the multilayer junction to form B' by any conventional method In the material examples of the metal oxide semiconductor layer 12A and 12B, the closed top region of the metal silicide layer 12A field-effect transistor is used as the top of the active region. It is not important that the present invention is contained in the substrate 10 in the second A picture, and the present invention is not understood. Subsequent embolic implantation steps. Ran 3. The steps mentioned in the second figure will be in the following third A to third containing integrated circuit structures, such as a metal oxide bottom layer 1 0 0, and a flat oxide layer 1 2 is formed on it by an oxidation method. 2 2 0 0 Angstroms, but the maximum thickness is about the same time. The oxide layer 120 may also be an oxygen-oxidized layer formed by an oxidative vapor deposition (APCVD) method formed by an electric paddle gain method (HDP). The inner dielectric layer in this oxide structure. A part of the 12F and 12 field-effect transistors of the metal lithotripsy layer. The metal stone is basically a titanium fossil. In the present embodiment, it is used as a metal oxide semiconductor field, and the metal oxide layer 1 2 B must be mentioned briefly here. The structure of the first element is formed, and these pairs cannot be described without detailed tracing details. Reason
第8頁Page 8
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a ^ ^86Sit'a ^ ^ 86Sit '
、一覆蓋層(cap layer ) 1 4在金屬矽化層1 2八上 成,係用以作為蝕刻中止層。以傳統的化學氣相沉積法形 成的覆蓋層,主要為氮化矽或是氮氧化矽的堆疊。之後, ,任何適當的方法形成光阻層,並且在接觸窗洞的位 接觸窗圖案轉移到光阻層4 〇。 接 電層2 聚合物 過度蝕 非氧化 等。對 聚合物 些不同 示選擇 物。 者參考第三B圖與 0。在 來達到 刻的過 層,如 於蝕刻 β在發 的含氫 姓刻氮 高密度電漿 氧化物對底 程中會蝕刻 石夕,欽石夕化 氮化矽或是 展這個製裎 氧體,如C {J2 化矽/氮氧 第三C圖’以乾#刻方式飯刻个' 氧化物餃刻機中,藉由富含碳纪 材的蝕刻比。富含碳的聚合物名 氧化物而停在包含底材在内的纪 合物’氮化矽,氮化鈦,鋁,筹 氮氧化石夕時,關鍵在於含氫類纪 上’以C4 F8 / C 0 / A r化合物加上一 F2,CH3F ’ chf3,c2H2F4 等,會顯 化矽層而不會同時银刻鈦石夕化合A cap layer 14 is formed on the metal silicide layer 128, and is used as an etching stop layer. The cover layer formed by the conventional chemical vapor deposition method is mainly a stack of silicon nitride or silicon oxynitride. After that, the photoresist layer is formed by any appropriate method, and the contact window pattern is transferred to the photoresist layer 40 at the position where the window hole is contacted. Electrical layer 2 Polymer over-etched Non-oxidized etc. Some alternatives are shown for polymers. Refer to the third figure B and 0. In order to achieve the etched layer, such as etching β in the hydrogen-containing high-density plasma-etched high-density plasma oxide pair, it will etch Shi Xi, Qin Shi Xi, silicon nitride, or develop this oxide, such as C {J2 Silicone / Nitrogen and Oxygen The third C picture 'in a dry #engraving method to engrav a rice' in an oxide dumpling engraving machine, with an etching ratio rich in carbon materials. Carbon-rich polymer oxides stop at the base compounds including silicon substrates, such as silicon nitride, titanium nitride, aluminum, and oxynitride. The key lies in the hydrogen-containing phase, with C4 F8. / C 0 / A r compound plus one F2, CH3F 'chf3, c2H2F4, etc., will manifest the silicon layer without silver titanate
,而;,熱反2壁與α化合物產生 。氧化物/欽石夕人2 2氣體在局後度電藥中的分解產生 調整製程參數來ί ^物與氧化物/氮化矽的選擇比是藉由 度蝕刻中不4被=1二因為製程具有高選擇比,底層在過 植入步驟·5Γ …t 統製程中用以補償接合損失的栓塞, And ;, thermally reversing the 2 walls with alpha compounds. The decomposition of the oxide / Qin Shixiren 2 2 gas in the post-electrochemical process produces adjustment process parameters to select the ratio of the material to the oxide / silicon nitride through the degree of etching. The process has a high selection ratio. The bottom layer is used in the over-implantation step.
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US9520477B2 (en) | 2015-03-16 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company | Semiconductor device and fabricating method thereof |
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