TW465035B - Manufacture method of extremely narrow bit line without sidewall spacer - Google Patents

Abstract

This invention provides the manufacture method of extremely narrow bit line without sidewall spacer, which include the formation of gate structure on the substrate. The aforementioned gate structure consists of gate oxide layer, gate and the mask layer on top of the gate. Oxide is formed on the surface of gate using thermal oxidation process to eliminate the need of the formation of sidewall spacer. Then, source and drain are formed adjacent to the gate structure. The first oxide layer is patterned on the gate structure to expose the source. Subsequently, capacitor is formed on the abovementioned structure and is connected to the source. The second oxide layer is then formed and the drain is exposed by etching the second oxide layer, which create opening in the oxide layer. Finally, bit line contact is formed in the contact opening.

Description

465035 V. Description of the invention (1) Field of the invention: The present invention relates to the second method of the semi-conductive skeleton, the method of forming the quasi-contact window A, and in particular, the process of the self-access random access memory system must: Dynamic armor is used as a method for extremely sharp contact. Background of the Invention: After the density of integrated electricity and the challenge of size, the smaller the role of the semiconductor, the more random the state is, the larger the capacitance is. There is a significant tendency for the circuit. It will be more and more difficult due to the need to maintain random storage & increase small electrons. With the continuous development of the dimensional tolerance of the same components of the same process, the health of the same components § Ji Yi cell (1C) has also been reduced to increase by half. For example, the importance of becoming a shape on a storage wafer has made the process of accessing and recalling the scale down the challenge. Through technology, it has become a chip with a reduced volume and a random capacitance. In particular, the challenges that occur in the body are still common, dynamic improvement. By shrinking the density, the manufacturing process (dram) has been able to reliably increase the error of the process. While the phase continues to increase, the equivalent of electronic memory, electronic components, rulers, electronic components, and many new shrinkages are missing. The degree played by the base is also more and more dynamic, and the quantity is also an array using a buried bit line (b u r e d i 11 i n e) or a non-buried bit line structure. In the case of a non-buried bit line structure, generally, a vertical deep perforation must be etched into the insulating layer 'to go straight to the switching transistor. And this non-buried bit line structure can be further divided into the bit line capacitor structure (capacitor_under ~ bit line 46 50 3 5 5 'Invention Description (2)' CUB) and the bit line capacitor structure (capacitor-over — Bitiine; COB). In the prior art, making self-aligI1 contact (SAC) is an important part of the semiconductor process, but it also faces difficulties. The main steps include forming a field oxide region on the semiconductor substrate to define the active region, and then depositing the gate. An oxide layer and a polycrystalline silicon layer are above the field oxidation region and the substrate. Then, a silicon dioxide layer or a nitride nitride layer is deposited on the polycrystalline silicon layer. Definition The photoresist etches the above-mentioned gate oxide layer, polycrystalline silicon layer, and nitride to form a gate structure with a cap layer. The above cap layer is to prevent the subsequent deposited film layer from making electrical contact with the gate to cause a short circuit. In the next step ', after depositing a dielectric layer, the dielectric layer is etched by a etch process to form a sidewall gap over the sidewall of the gate structure. After fabrication of the Yuancheng sidewall gap, source and non-doping are performed. A dielectric layer is deposited on the surface of the above structure. Generally, a silicon oxide is used, and a photoresist pattern is defined on the dielectric layer. The photoresist pattern is used as a cover. The above-mentioned dielectric layer is etched using the last engraving technique to make a contact window. Finally, the photoresist is removed to complete the fabrication of the contact window. Generally, the side wall gap is made of nitrogen stone as the material. During the SAC etch process, it is easy to cause the loss of the side wall gap 'and cause the gate to short-circuit. United States Patent No. 6, 〇57, 187 The inventor J e η and others disclosed a bit line contact process applied to dynamic random access memory. Title: " DRAM structure with multiple

465035 V. Description of the invention (3) memory cells sharing the same bit-line contact and fabrication method thereof ". Another previous technology is United States Patent No. 5, 858,829, entitled " Method for fabricating dynamic random access memory (DRAM) cells with mi ni in um active cell areas using side wall spacer bit lines11 'which is also proposed The sidewall gap is used as the structure of the bit line. Furthermore, U.S. Patent States No. 6, 0 8 3, 8 31 proposes a method for making a contact hole. This method includes forming an insulating dielectric material at the position of the capacitor plate, and then etching to form an opening (open i ng) in the insulation above the position of the plate. Then, a film layer is deposited along the surface of the dielectric layer engraved by the shoe, and then the film layer is anisotropically etched to facilitate the fabrication of the side wall gap on the side wall of the opening. The above-mentioned side wall gap will help to form the contact hole n: Ϊ = impurity. In addition, in the traditional 寸 -inch range, the width of the side wall gap on the gate side will be limited. Purpose and summary of the invention: The main purpose of the present invention is to provide an integrated circuit with bit line contact.

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V. Description of the invention (4) Another object of the present invention is to provide a method for making extremely narrow bit line contacts without making side wall gaps in a dynamic random access memory system. The present invention discloses making bit lines without making side wall gaps. The contact method includes forming a gate oxide layer on the substrate, forming a polycrystalline silicon layer on the gate oxide layer, and forming a silicon nitride layer on the polycrystalline silicon layer. The thickness of the above-mentioned silicon nitride layer is about 500-200 Angstroms. After that, the silicon nitride layer, the polycrystalline silicon layer, and the gate polarization layer are etched to form a gate structure. An oxide is formed on the surface of the gate electrode by thermal oxidation to avoid the step of making a sidewall gap before the wire. A drain and source gate structure is formed next. Then, the first silicon oxide layer is patterned on the gate structure to expose the source electrode, and the thickness of the silicon oxide layer is between about 100 and 2000 angstroms. A capacitor is then formed on the above structure and connected to the source. A second silicon oxide layer is formed later, and the thickness of the silicon oxide layer is between about 300 and 100 angstroms. Then, the silicon oxide layer is etched to expose the drain electrode, thereby forming a contact hole in the silicon oxide layer. Finally, the bit lines are formed in contact with the contact holes. Detailed description of the invention: As shown in FIG. 1, a single crystal semiconductor with a crystal plane of < 1 0 0 > is used as a substrate, such as a P-type or N-type single-crystal silicon substrate 2 ^ Next, it is fabricated as an isolation device The insulating region 4 can generally use field oxidation fabrication technology or trench isolation technology. According to an embodiment, a conventional L 0 C 0 S process is used to fabricate a thick field oxide region 4 as an insulator of the active region, and the field oxide is oxidized.

Page 7 λ r η ^ 5 _ V. Description of the invention (5) ------ The area is formed by thermal oxidation in an aerobic vapor environment. Warm production produces a dioxygen cut between 85 thieves and has a thickness of 4_ — = Egypt is picking up

With 'formed a ρ on the substrate 2', the cover of the Q method is called the silicon screen fm 葚 3 pole oxide layer 6 'recycling chemical vapor deposition daylight stone 7 layer 8 covering the gate nitrogen a > In the above-mentioned polycrystalline silicon 8 = 'thickness is 1000 to 2 _ Angstrom 1 〇, u ^, said Table 8 is a chemical vapor deposition covering layer, f is covered with polycrystalline silicon ... of "Dagger nitrogen" material As between the above. Then n = iV; '^ degree range is 5 to 20 00 angstroms ^ ^. The resist pattern is on the silicon nitride layer 10 to etch ΐ 1G' polycrystalline dream layer 8 and closed electrode oxide layer to strengthen: prepare wood #Etching removes areas not covered by photoresist to form a closed electrode structure. The nitride layer 10 is used as a cover layer for the gate structure. Its main function is to prevent a short circuit between the polycrystalline silicon layer 8 and subsequent conductive film phenomenon. Equal function materials can also replace silicon nitride as a cover layer. The above nitrided layer 10 can be formed by chemical vapor deposition method, for example, low pressure chemical vapor deposition method. Generally, Si Η 4, NH 3, N 2, N 2 0 or other suitable materials can be used in the reaction chamber. The reactant forms a nitrided layer at a temperature of 300 to 800 degrees Celsius. As can be seen from the figure, during the etching process of making the gate electrode, the word line is also formed on the insulating structure 4 at the same time. Next, an oxide 12 is formed on the surface of the polycrystalline silicon gate electrode 8 as shown in FIG. The thickness is about 5 0-2 0 0 Angstroms. The function of this oxide 12 is similar to that of the covering layer 10, which acts as a barrier (b a r r e e r) for the etching, in order to prevent the polycrystalline stone layer 8 from forming a short circuit with the subsequent conductive structure. In a preferred embodiment,

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Claims (1)

This is my% positive __ VI. Patent application scope 1 A method for making bit line contact without making sidewall gap, the method includes: forming an interlayer oxide layer on a substrate; forming polycrystalline silicon on the gate oxide Layer; forming a first dielectric layer on the polycrystalline silicon layer as a cover layer; etching the first dielectric layer, the polycrystalline silicon layer, and the gate polarization layer to form a gate structure * the gate The electrode structure includes a gate oxide layer, a gate electrode, and a cover layer; an oxide is formed around the surface of the gate electrode by a thermal oxidation method; a drain electrode and a source electrode are formed adjacent to the gate electrode structure; and a second dielectric layer is patterned on Above the gate structure, the source electrode is exposed; a third dielectric layer is formed on the above-mentioned result surface; the third dielectric layer is etched to expose the drain electrode, and thus a contact hole is formed in the third dielectric Layers; and forming bit lines into contact with the contact holes. 2. The method of making a bit line without the need to make a side wall gap according to the first patent application scope, wherein after patterning the second dielectric layer, it further comprises forming a capacitor. 3. The method for making a bit line contact without the need to make a side wall gap according to item 1 of the scope of the patent application, wherein the above-mentioned first dielectric layer includes silicon nitride. 4 If the method of making a bit line without making a side wall gap is required in the first scope of the patent application, wherein the thickness of the first dielectric layer is about 500-200 Angstroms. Page 12 4. 6 5 0 b 6. Between patent applications. 5. The method for making a bit line without the need to make a side wall gap according to item 1 of the scope of the patent application, wherein the above-mentioned second dielectric layer includes silicon oxide. 6. The method of making a bit line contact without the need to make a side wall gap according to item 1 of the scope of the patent application, wherein the thickness of the second dielectric layer is about 100-200 Angstroms. 7. The method for making a bit line without the need to make a side wall gap according to item 1 of the scope of the patent application, wherein the third dielectric layer described above includes silicon oxide. 8. The method for making a bit line contact without the need to make a side wall gap according to item 1 of the scope of the patent application, wherein the thickness of the third dielectric layer is about 300-1000 Angstroms. 9. The method for making a bit line without the need to make a side wall gap according to item 1 of the scope of patent application, wherein after forming the third dielectric layer, the method further includes planarizing the third dielectric layer. 10—A method for making bit line contact without making a sidewall gap, the method includes: forming a gate oxide layer on a substrate; forming polycrystalline silicon on the gate oxide layer; Page 13 4 6 5 L ·-VI. Patent application scope: forming a silicon nitride layer on the polycrystalline silicon layer as a cover layer; etching the silicon nitride layer, the polycrystalline silicon layer and the gate polarization layer To form a gate structure, the gate structure including a gate oxide layer, a gate electrode, and a cover layer; forming an oxide to surround the gate electrode surface by a thermal oxidation method; forming a drain electrode and a source electrode adjacent to the gate structure; Forming a first silicon oxide layer on the gate structure to expose the source; forming a capacitor on the above structure and connecting to the source; forming a second silicon oxide layer on the above-mentioned resulting surface; planarizing the A second silicon oxide layer; etching the second silicon oxide layer to expose the drain electrode, thereby forming a contact hole in the second silicon oxide layer; and forming a bit line in contact with the contact hole. 11 According to the method of manufacturing bit line contact which does not need to make a side wall gap according to item 10 of the scope of the patent application, the thickness of the above silicon nitride layer is between about 500 and 2000 angstroms. 1 2 According to the method of manufacturing bit line contact without the need to make a side wall gap in item 10 of the scope of patent application, the thickness of the first silicon oxide layer is about 100-200 Angstroms. 1 3 According to the method of making a bit line contact without making a side wall gap in item 10 of the scope of patent application, wherein the thickness of the second silicon oxide layer is about Page 14 46503d Page 15