KR100209223B1 - Semiconductor device manufacturing method for forming contact - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

A semiconductor device having a design rule of 150 nm or less

2. Technical Problems to be Solved by the Invention

To form a contact of a highly integrated semiconductor device whose design rule is 150 nm or less.

3. The point of the solution of the invention

Grow selective epitaxial layers to increase contact area and contact depth.

4. Important Uses of the Invention

Manufacturing of semiconductor devices

Description

Highly integrated semiconductor device fabrication method for fine contact formation

As the degree of integration of semiconductor devices increases, the cell area decreases in inverse proportion, which seriously limits the formation of contacts for connection between conductive layers. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for a micro contact, and more particularly, to a method of forming a contact, which can be applied not only to a dynamic RAM having a 1 Giga class or higher but also a device having a similar design rule .

As the degree of integration of a semiconductor device increases, it is necessary to fabricate a device having the same function within a small cell area. In this case, various problems arise. One of them is the contact formation. In the past, since the pattern is formed by the lithography process, that is, the mask and the etching, the overlay accuracy of the lithography reaches the limit due to the increase of the integration degree, A short circuit with the gate electrode occurs in the film pattern, for example, the bit line or the capacitor contact process.

Conventionally, a self-aligned contact (SAC) method is used to improve this. The SAC process will be briefly described below with reference to FIGS. 1A and 1C.

First, FIG. 1A shows a step of forming a field oxide film 12 for device isolation on a silicon substrate 11 and patterning a mask oxide film 15 for protecting the gate oxide film 13, the gate electrode 14, And then the spacer oxide film 16 is formed on the gate sidewall. Subsequently, a source / drain junction (not shown) is formed, and then a thin silicon nitride film (SiN) 17 of about 30 nm thick is deposited as shown in FIG. 1B, a planarized interlayer oxide film 18 is formed thereon , And a photoresist pattern 19 which is a contact mask pattern is formed. Then, as shown in FIG. 1C, the interlayer oxide film 18 is selectively etched by using an etching recipe having a high selectivity to the silicon nitride film 17, and then the exposed silicon nitride film 17 is etched. At this time, the silicon nitride film 17 on the sidewall of the spacer oxide film 16 serves as a barrier due to the anisotropic etching property, thereby preventing a short circuit between the gate and the contact.

However, one of the problems of the related art as described above is that the silicon nitride film is left on the side wall of the gate to reduce the contact area. This problem is conspicuous in the design rule of 150 nm or less. For example, when the design rule is 150 nm, since the spacing between the gates is 150 nm, 150-2 * 40 = 70 nm when the spacer oxide film of 40 nm is used becomes an active region that can be contacted. Therefore, since a silicon nitride film of about 30 nm is required in the SAC process, it can be seen that the final contact area (bottom surface size of the contact hole) formed after etching the silicon nitride film is very small as 70-2 * 30 = 10 nm.

As a result, the covering of the conductive material filling the contact hole becomes poor, and the contact resistance becomes large, thereby reducing the reliability of the device.

It is an object of the present invention to provide a method of manufacturing a highly integrated semiconductor device for forming a contact of an ultra high concentration semiconductor device having a design rule of 150 nm or less.

In order to achieve the above object, the present invention has been made to increase the contact area by growing a selective epitaxial layer after forming a spacer oxide film on the gate sidewall, and also to prevent short- A silicon nitride film was used as a barrier for the gate pattern.

1A and 1C show a conventional self-aligned contact forming process,

FIGS. 2A through 2D are views showing a process of forming a contact according to an embodiment of the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

21: silicon substrate 22: field oxide film

23: gate oxide film 24: polysilicon film

25: mask oxide film 26: silicon nitride film

27: spacer oxide film 28: epitaxial layer

29: interlayer oxide film 30: photoresist pattern

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2A and 2D.

2A, a gate oxide film 23, a gate electrode polysilicon film 24, a gate protection mask oxide film 25, and a silicon nitride film 24 are formed on a silicon substrate 21 on which a field oxide film 22 is formed, (26) are sequentially stacked, and then the above-mentioned deposited layer is patterned by a mask and an etching process, and a spacer oxide film (27) is formed on the sidewalls of the patterned layers (23, 24, 25, 26).

Then, a source / drain junction (not shown in the figure) is formed through ion implantation on the exposed silicon substrate as shown in FIG. 2B, and then a selective epitaxial layer 28 is grown. The height of the epitaxial layer 28 corresponds to the height of the patterned layer 23, 24, 25, 26, and may be less than this and slightly higher.

Next, a planarized interlayer oxide film 29 is formed as shown in FIG. 2C, and then a photoresist pattern 30, which is a contact mask pattern, is formed.

2D, a contact hole is formed by etching the interlayer oxide film 29 by high selective etching with the silicon nitride film 26 as shown in FIG. 2D. At this time, the important point is that the silicon nitride film 26 acts as a barrier to prevent a short circuit with the gate 24.

Here, the epitaxial layer may be an epitaxial layer including any one of silicon, polysilicon, tungsten, and titanium silicide, and the mask layer may include any one of a silicon nitride film, a polymer, and a silicon oxide misfire film. have.

The epitaxial layer according to an embodiment of the present invention broadens the contact area margin and reduces the contact depth, thereby improving the layer coverage of the contact material deposited thereon. In another embodiment of the present invention, the process is performed in the same manner as in the above example until the formation of the gate pattern, thermal oxidation is performed at 800 DEG C for 30 minutes without forming a spacer oxide film, Dry etching to remove the thin oxide film in the active region and selectively form a titanium silicide film (TiSi ₂ ) to achieve the object of the present invention.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art.

The present invention easily forms a relatively large contact hole in the conventional process even in a small cell area, so that a semiconductor device having a design rule of 150 nm or less, for example, a 1G DRAM, a 4G DRAM, a 16G DRAM and a 1G SRAM Thereby improving process margins and thus yield, reliability, and the like.

Claims (6)

A method for manufacturing a semiconductor device for forming a second conductive layer pattern insulated on a first conductive layer and forming a third conductive layer connected to the first conductive layer through a space between the second conductive layer patterns, Stacking a first insulating layer and a second conductive layer on the first conductive layer, and a mask layer protecting the upper portion of the second conductive layer in this order; Patterning the laminated layer by a lithography process; Forming a second insulating layer covering a side wall of the stacked layer; Selectively forming an epitaxial layer on the exposed first conductive layer; Forming a third insulating film on the entire structure; Selectively etching the third insulating film by a contact mask and an etching process to form a contact hole through which a predetermined portion of the epitaxial layer is exposed; And And forming a third conductive layer in contact with the exposed epitaxial layer. The method according to claim 1, Wherein the first conductive layer is a silicon substrate and the second conductive layer is a gate electrode. The method according to claim 1, Wherein the epitaxial layer is formed to have a height substantially equal to a height of the stacked layers. The method according to claim 1, Wherein the mask layer is a layer having the third insulating film and the high etch selectivity ratio. The method according to claim 1, Wherein the epitaxial layer is an epitaxial layer containing any one of silicon, polysilicon, tungsten, and titanium silicide. 5. The method of claim 4, Wherein the mask layer comprises one of a silicon nitride film, a polymer, and a silicon oxide misfire film.