KR100431709B1 - Mos transistor with vertical channel using local epitaxial layer, semiconductor memory cell and manufacturing method thereof - Google Patents
Mos transistor with vertical channel using local epitaxial layer, semiconductor memory cell and manufacturing method thereof Download PDFInfo
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- KR100431709B1 KR100431709B1 KR1019960045169A KR19960045169A KR100431709B1 KR 100431709 B1 KR100431709 B1 KR 100431709B1 KR 1019960045169 A KR1019960045169 A KR 1019960045169A KR 19960045169 A KR19960045169 A KR 19960045169A KR 100431709 B1 KR100431709 B1 KR 100431709B1
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Abstract
Description
본 발명은 수직 방향의 채널을 갖는 모스트랜지스터(MOSFET)와 그를 포함하는 반도체 메모리 셀 및 그 들의 제조 방법에 관한 것으로, 특히 반도체 기억소자가 고집적화됨에 따라, 이 집적도를 높이기 위해 기억소자를 구성하는 단위 셀들의 각 모스트랜지스터 차지하는 면적을 최소화할 수 있는 기술에 관한 것이다.The present invention relates to a MOS transistor having a channel in a vertical direction, a semiconductor memory cell including the MOSFET, and a method of manufacturing the same. More particularly, as the semiconductor memory device is highly integrated, To a technique capable of minimizing the area occupied by each MOS transistor of the cells.
일반적으로, 반도체 메모리 소자를 구성하는 모스트랜지스터는 실리콘 기판과 수평하게 채널이 형성되어 있다. 따라서, 소자의 고집적화를 위해 모스트랜지스터가 차지하는 면적을 최소화 할 때, 채널의 길이는 짧아질 수 밖에 없으며 이로인해 심각하게 대두되는 문제점은 숏채널 효과(short channel effect)이다. 숏채널 효과를 방지하기 위해서는 기판의 농도를 고농도로 유지하여야하나, 이 방식 역시 핫 캐리어 효과(hot carrier effect)에 의해 기판의 누설전류가 급증하고 또한 채널 영역에서 캐리어(전자 또는 홀)의 이동도가 감소하여 트랜지스터의 전류구동 능력이 감소하게 된다.Generally, a MOS transistor constituting a semiconductor memory element has a channel formed horizontally with a silicon substrate. Therefore, when the area occupied by the MOS transistor is minimized for high integration of the device, the channel length must be shortened, and a serious shortcoming is the short channel effect. In order to prevent the short channel effect, the concentration of the substrate must be maintained at a high concentration. However, in this method, too, the leakage current of the substrate is rapidly increased by the hot carrier effect and the carrier (electron or hole) The current driving capability of the transistor is reduced.
본 발명의 목적은 채널을 수직 방향으로 형성하여 양호한 특성을 유지하면서 소자의 고집적화에 대응할 수 있는 트랜지스터와 그를 포함하는 반도체 메모리 셀 및 그들의 제조 방법을 제공하는데 있다.It is an object of the present invention to provide a transistor, a semiconductor memory cell including the same, and a method of manufacturing the same, which can form a channel in a vertical direction and can cope with high integration of devices while maintaining good characteristics.
도 1은 본 발명의 일실시예에 따른 모스트랜지스터 구조를 나타내는 단면도,1 is a cross-sectional view illustrating a MOS transistor structure according to an embodiment of the present invention,
도 2A 내지 도 2G는 본 발명의 일실시예에 따른 모스트랜지스터 제조 공정도,2A to 2G are diagrams illustrating a MOS transistor manufacturing process according to an embodiment of the present invention,
도 3은 본 발명의 일실시예에 따른 다이나믹 램 셀 구조를 나타내는 단면도.3 is a cross-sectional view illustrating a dynamic RAM cell structure according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
11: 실리콘 기판11: silicon substrate
12: 소자분리막12: Element isolation film
13: 제1에피택셜 실리콘층13: a first epitaxial silicon layer
14: 게이트 산화막14: gate oxide film
15: 폴리실리콘막15: Polysilicon film
16,17: 소오스/드레인 접합층16, 17: Source / drain junction layer
18: 제2 에피택셜 실리콘층18: second epitaxial silicon layer
상기 목적을 달성하기 위한 본 발명의 모스트랜지스터는 반도체 기판과 그로부터 선택적으로 성장된 제1에피택셜 반도체층에 의해 형성되는 채널 유기층, 상기 제1에피택셜 반도체층의 일측 측벽에 게이트 절연막을 개재하여 형성된 게이트 전도층, 상기 제1에피택셜 반도체층과 상기 반도체 기판이 접하지 않은 상기 제1에피택셜 반도체층의 일면과 상기 반도체 기판의 일면에 형성된 소오스/드레인 접합, 및 상기 반도체기판에 기판 바이어스를 걸어주기 위해 상기 제1에피택셜 반도체층의 타측 측벽에 형성되는 제2에피택셜 반도체층을 구비한다.According to an aspect of the present invention, there is provided a MOS transistor comprising: a channel organic layer formed by a semiconductor substrate and a first epitaxial semiconductor layer selectively grown therefrom; a channel organic layer formed on a side wall of the first epitaxial semiconductor layer through a gate insulating film A source / drain junction formed on one surface of the first epitaxial semiconductor layer and the first semiconductor epitaxial semiconductor layer not contacting the first epitaxial semiconductor layer and the semiconductor substrate, and a source / drain junction formed on the semiconductor substrate, And a second epitaxial semiconductor layer formed on the other side wall of the first epitaxial semiconductor layer in order to provide the second epitaxial semiconductor layer.
또한 본 발명의 반도체 메모리 샐은 반도체 기판과 그로부터 선택적으로 성장된 제1에피택셜 반도체층에 의해 채널이 형성되고, 상기 제1에피택셜 반도체층과 상기 반도체 기판이 접하지 않은 상기 제1에피택셜 반도체층의 일면과 상기 반도체 기판의 일면에 형성된 소오스/드레인 접합이 형성되며, 상기 제1에피택셜 반도체층의 일측 측벽에 게이트 절연막을 개재하여 게이트가 형성된 모스트랜지스터, 상기 소오스 접합에 콘택되는 제1전극과, 상기 제1전극 표면에 형성된 유전막 및 상기 유전막을 덮는 제2전극으로 이루어진 캐패시터, 상기 드레인 접합에 콘택되는 비트라인, 및 상기 반도체 기판에 기판 바이어스를 걸어주기 위해 상기 제1에피택셜 반도체층의 타측 측벽에 형성되는 제2에피택셜 반도체층을 구비한다.In the semiconductor memory of the present invention, a channel is formed by a semiconductor substrate and a first epitaxial semiconductor layer selectively grown therefrom, and the first epitaxial semiconductor layer and the first epitaxial semiconductor And a source / drain junction formed on one surface of the semiconductor substrate, wherein the source / drain junction is formed on one side of the first epitaxial semiconductor layer and the gate electrode is formed on one side of the first epitaxial semiconductor layer with a gate insulating film interposed therebetween, A capacitor comprising a dielectric layer formed on the surface of the first electrode and a second electrode covering the dielectric layer; a bit line contacted to the drain junction; and a second epitaxial semiconductor layer And a second epitaxial semiconductor layer formed on the other side wall.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 일실시예에 따른 트랜지스터 구조를 나타내는 단면도로서, 실리콘 기판(11)과 그로부터 선택적으로 성장된 제1에피택셜 실리콘층(13)에 의해 채널영역을 형성되며, 상기 제1에피택셜 실리콘층(13)의 일측 측벽에 게이트 산화막(14)을 개재하여 스페이서 형상으로 형성되는 폴리실리콘막(15)에 의해 게이트가 형성된다. 그리고, 제1에피택셜 실리콘층(13)과 실리콘 기판(11)이 접하지 않은 제1에피택셜 실리콘층(11)의 일면 및 실리콘 기판(11)의 일면에는 소오스/드레인접합층(16,17)이 각각 형성된다. 부가적으로 게이트가 형성되지 않은 제1에피택셜 실리콘층(13)의 타측 측벽에는 기판 바이어스를 가해주기 위한 영역인 제2 에피택셜 실리콘층(18)이 형성되게 된다. 미설명 도면부호 12는 소자분리막을 나타낸다.1 is a cross-sectional view illustrating a transistor structure according to an embodiment of the present invention, in which a channel region is formed by a silicon substrate 11 and a first epitaxial silicon layer 13 selectively grown therefrom, A gate is formed by a polysilicon film 15 formed in a spacer shape via a gate oxide film 14 on one sidewall of the positive silicon layer 13. [ On one surface of the first epitaxial silicon layer 11 where the first epitaxial silicon layer 13 and the silicon substrate 11 are not in contact with each other and on one surface of the silicon substrate 11, source / drain junction layers 16 and 17 Respectively. In addition, a second epitaxial silicon layer 18, which is a region for applying a substrate bias, is formed on the other side wall of the first epitaxial silicon layer 13 where no gate is formed. 12 is a device isolation film.
도면에 도시된 바와같이 본 발명의 일실시예에 따른 트랜지스터는 채널길이가 에피택셜 실리콘층(13)의 두께에 의존함으로 매우적은 실리콘 기판 면적에서도 채널길이가 큰 모스트랜지스터를 형성할 수 있어 숏 채널 효과를 방지할 수 있다. 또한, 이후의 설명에서도 상세히 언급되겠지만 트랜지스터의 소오스/드레인 영역이 수직 트랜지스터의 위/아래에 위치하고 있어 이 영역들을 캐패시터와 비트라인에 연결시키면 고집적 다이나믹 램 셀의 제조가 가능하다.As shown in the figure, since the channel length of the transistor according to the embodiment of the present invention depends on the thickness of the epitaxial silicon layer 13, it is possible to form a MOS transistor having a large channel length even in a very small silicon substrate area, The effect can be prevented. Also, as will be described later in detail, the source / drain region of the transistor is located above / below the vertical transistor, and these regions are connected to the capacitor and the bit line, thereby enabling the fabrication of a highly integrated dynamic RAM cell.
도 2A 내지 도 2G는 도 1과 같은 모스트랜지스터를 형성하기 위한 제조 공정도로서, 이를 통해 수직 채널을 갖는 모스트랜지스터 제조 공정을 상세히 살펴본다.FIGS. 2A to 2G are process diagrams for forming a MOS transistor as shown in FIG. 1, and a MOS transistor manufacturing process having a vertical channel will be described in detail.
먼저, 도 2A는 제1실리콘 기판(201) 상에 국부적으로 트렌치 타입의 소자분리막(202)을 형성한 후, 소자분리막(202)이 형성되지 않은 제1실리콘 기판 표면으로부터 선택적으로 제1에피택셜 실리콘층(203)을 성장시킨다. 이 제1에피택셜 실리콘층(203)은 트랜지스터의 채널이 형성될 지역으로 그 두께에 의해 채널 길이가 결정됨으로 유의해야 할 것이다.2A illustrates a method of forming a trench type device isolation layer 202 on a first silicon substrate 201 and then selectively removing a first epitaxial layer 202 from a surface of the first silicon substrate on which the isolation layer 202 is not formed The silicon layer 203 is grown. It should be noted that the first epitaxial silicon layer 203 is a region where the channel of the transistor is to be formed, and the channel length is determined by its thickness.
이어서, 도 2B와 같이 제1에피택셜 실리콘층(203)의 일측 측벽에 질화막(SiN) 스페이서(204)를 형성하는데, 질화막 스페이서(204)를 형성하는 구체적인 방법은, 전체구조 상부에 질화막을 증착한 다음 마스크 및 식각 공정으로 패터닝하고(도면부호 204a) 다시 패터닝된 질화막(204a)을 비등성 전면식각하여 형성한다. 이 질화막 스페이서(204)를 형성하는 이유는 제2에피택셜 실리콘층(203)의 일측 측벽을 질화막 스페이서(204)가 감싸도록 함으로써 이곳이 후속 공정으로부터 보호되어 이후에 이곳에서 제2에피택셜 실리콘층이 성장되도록 하기 위함이다.2B, a nitride film (SiN) spacer 204 is formed on one sidewall of the first epitaxial silicon layer 203. A specific method of forming the nitride film spacer 204 includes depositing a nitride film on the entire structure Followed by patterning with a mask and etching process (reference numeral 204a) and patterning the back nitride film 204a by an isotropic front etching. The reason for forming this nitride film spacer 204 is that the nitride film spacer 204 surrounds one sidewall of the second epitaxial silicon layer 203 so that it is protected from the subsequent process so that the second epitaxial silicon layer 203 To grow.
이어서, 도 2C 와 같이 열적 산화를 이용하여 노출된 제1에피택셜 실리콘층(203)에 게이트 산화막(205)을 성장시킨 후, 상기 질화막 스페이서(204)를 형성한 방법과 동일하게 공정을 진행하여 상기 제1에피택셜 실리콘층(203)의 타측 측벽에 폴리실리콘막 스페이서(206)를 형성한다.Next, the gate oxide film 205 is grown on the exposed first epitaxial silicon layer 203 by thermal oxidation as shown in FIG. 2C, and then the process is performed in the same manner as the nitride film spacer 204 is formed A polysilicon film spacer 206 is formed on the other side wall of the first epitaxial silicon layer 203.
이어서, 도 2D와 같이 질화막 스페이서(204)를 습식 제거한 후, 질화막 스페이서(204)의 제거로 인해 노출된 제1에피택셜 실리콘층(203)으로부터 성장된 제2에피택셜 실리콘층(207)을 형성한다.2D, the second epitaxial silicon layer 207 grown from the first epitaxial silicon layer 203 exposed by the removal of the nitride film spacer 204 is formed by wet-removing the nitride film spacer 204 as shown in FIG. 2D do.
이어서, 제1에피택셜 실리콘층(203) 상에 불순물을 이온 주입하여 소오스(또는 드레인) 접합층(208)을 형성하고, 도 2E와 같이, 전체구조 상부에 절연막, 예컨데 산화막(209)을 형성한 후, 상기 소오스 접합층(208)에 금속막을 콘택하고 패터닝하여 소오스 전극(210)을 형성한다.Next, an impurity is ion-implanted on the first epitaxial silicon layer 203 to form a source (or drain) junction layer 208, and an insulating film, for example, an oxide film 209 is formed on the entire structure as shown in FIG. 2E A source electrode 210 is formed by contacting and patterning a metal film on the source bonding layer 208.
계속해서, 도 2F와 같이 평탄화된 보호막(passivation layer)(211)을 형성하고, 제2실리콘 기판(212)을 접합시킨다.Next, a planarized passivation layer 211 is formed as shown in FIG. 2F, and the second silicon substrate 212 is bonded.
이어서, 도 2G는 설명상 편의를 위하여 상기 도 2F를 180°회전시킨 것으로, 도면에 도시된 바와같이 제1실리콘 기판(201)의 밑면을 화학적/기계적 연마(Chemical Mechanical Polishing) 공정을 이용하여 소자분리막(2022)이 드러날때까지 에치백한다. 이때 소자분리막은 에치 스토퍼(Etch stopper) 역할을 한다. 이어서 소자분리막 사이로 드러난 제1실리콘 기판(201)에 불순물을 이온 주입하여 드레인 접합층(213)을 형성하고 여기에 금속막으로 드레인 전극(214)을 콘택하여 모스트랜지스터를 완성한다.2G is rotated by 180 ° for convenience of explanation. As shown in the figure, the bottom surface of the first silicon substrate 201 is subjected to a chemical mechanical polishing And returns to its original position until the separation membrane 2022 is exposed. At this time, the element isolation film serves as an etch stopper. Next, impurities are ion-implanted into the first silicon substrate 201 exposed between the device isolation films to form a drain junction layer 213, and the drain electrode 214 is contacted with a metal film to complete the MOS transistor.
이상에서 도 1와 같은 수직 형상의 모스트랜지스터를 제조하는 방법을 설명하였는데, 상기와 같은 도 1의 모스트랜지스터 및 그 제조 방법을 이용하여 다이나믹 램 셀을 구성할 수 있는데, 이를 도 3을 통해 살펴본다.A method of fabricating a vertical MOS transistor as shown in FIG. 1 has been described. The MOS transistor of FIG. 1 and the fabrication method of the MOS transistor of FIG. 1 can be used to form a dynamic RAM cell. .
도 3은 본 발명의 일실시예에 따른 다이나믹 램 셀 구조를 나타내는 단면도로서, 도면에 도시된 바와같이 도 1의 모스트랜지스터 구조에서, 소오스 접합(16)에는 스토리지 노드(31)/유전막(32)/플레이트전극(33)으로 이루어지는 캐패시터를 콘택하고, 드레인 접합(17)에는 비트라인(34)을 콘택하면 고집적화된 다이나믹 램 셀을 구성할 수 있다. 미설명 도면부호 34는 산화막, 35는 제2실리콘 기판을 나타낸다.1, the source junction 16 includes a storage node 31 / a dielectric layer 32, a source / drain region 32, and a source / drain region 32. In the MOS transistor structure of FIG. 1, / Plate electrode 33 and the bit line 34 is connected to the drain junction 17, a highly integrated dynamic RAM cell can be formed. 34 is an oxide film, and 35 is a second silicon substrate.
상기 도 3의 구조를 갖는 다이나믹 램 셀은 도면을 참조할시, 그 제조 방법을 용이하게 실시할 수 있으므로, 굳이 여기서 설명은 피하기로 한다. 단지 캐패시터의 스토리지 노드(31)는 폴리사이드로 형성하고, 유전막은 탄탈늄 산화막(Ta2O5)으로 형성하며 플레이트 전극은 인-슈트 도핑된(In-situ doped) 폴리실리콘을 사용하여 고집적 소자에 부합되는 캐패시터 용량을 얻도록 한다.The dynamic RAM cell having the structure of FIG. 3 can be easily fabricated by referring to the drawings, so that the description will be omitted here. Only the storage node 31 of the capacitor is formed of polycide, the dielectric film is formed of tantalum oxide film (Ta 2 O 5 ), and the plate electrode is made of in-situ doped polysilicon, Thereby obtaining a capacitor capacity corresponding to the capacitance of the capacitor.
이상에서 설명한 본 발명은 전술한 실시예를 포함하여 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 치환, 변형 및 변경이 가능하다.The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
반도체 기억 소자의 집적도가 증가할수록 좁은 영역안에서 트랜지스터나 셀을 형성시키는 기술이 필수적이다. 본 발명에 의하여 실리콘 웨이퍼에 대해 수직 방향의 채널을 형성하는 트랜지스터 또는 트랜지스터와 커패시터를 갖는 3차원적 다이나믹 램 셀을 형성함으로써 더 높은 집적도를 갖는 반도체 기억 소자의 제조를 가능하게 한다.As the degree of integration of the semiconductor memory device increases, techniques for forming transistors and cells in a narrow region are essential. According to the present invention, it is possible to manufacture a semiconductor memory device having a higher integration degree by forming a transistor or a three-dimensional dynamic RAM cell having a transistor and a capacitor which form a channel in a vertical direction with respect to a silicon wafer.
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| US8022457B2 (en) | 2005-11-17 | 2011-09-20 | Samsung Electronics Co., Ltd. | Semiconductor memory device having vertical channel transistor and method for fabricating the same |
| KR101076565B1 (en) * | 2011-05-17 | 2011-10-24 | 권의필 | High integrated mos device and the manufacturing method thereof |
| US8053817B2 (en) | 2007-11-05 | 2011-11-08 | Hynix Semiconductor Inc. | Vertical transistor and method for forming the same |
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| KR100725370B1 (en) * | 2006-01-05 | 2007-06-07 | 삼성전자주식회사 | Method for fabricating a semiconductor device and semiconductor device by the same |
| KR101415542B1 (en) * | 2013-04-10 | 2014-07-04 | 한국과학기술원 | Memory device and fabrication method thereof |
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| JPS6025272A (en) * | 1983-07-21 | 1985-02-08 | Nec Corp | Insulated gate field-effect type transistor |
| JPS63229756A (en) * | 1987-03-18 | 1988-09-26 | Nec Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS6025272A (en) * | 1983-07-21 | 1985-02-08 | Nec Corp | Insulated gate field-effect type transistor |
| JPS63229756A (en) * | 1987-03-18 | 1988-09-26 | Nec Corp | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8022457B2 (en) | 2005-11-17 | 2011-09-20 | Samsung Electronics Co., Ltd. | Semiconductor memory device having vertical channel transistor and method for fabricating the same |
| US8283714B2 (en) | 2005-11-17 | 2012-10-09 | Samsung Electronics Co., Ltd. | Semiconductor memory device having vertical channel transistor and method for fabricating the same |
| US8482045B2 (en) | 2005-11-17 | 2013-07-09 | Samsung Electronics Co., Ltd. | Semiconductor memory device having vertical channel transistor and method for fabricating the same |
| US8053817B2 (en) | 2007-11-05 | 2011-11-08 | Hynix Semiconductor Inc. | Vertical transistor and method for forming the same |
| US8198161B2 (en) | 2007-11-05 | 2012-06-12 | Hynix Semiconductor Inc. | Vertical transistor and method for forming the same |
| KR101076565B1 (en) * | 2011-05-17 | 2011-10-24 | 권의필 | High integrated mos device and the manufacturing method thereof |
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