KR20000039964A - Method for plug for forming semiconductor device - Google Patents
Method for plug for forming semiconductor device Download PDFInfo
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- KR20000039964A KR20000039964A KR1019980055469A KR19980055469A KR20000039964A KR 20000039964 A KR20000039964 A KR 20000039964A KR 1019980055469 A KR1019980055469 A KR 1019980055469A KR 19980055469 A KR19980055469 A KR 19980055469A KR 20000039964 A KR20000039964 A KR 20000039964A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
Description
본 발명은 반도체장치의 플러그 형성방법에 관한 것으로서, 특히, 콘택 형성시 자기정렬콘택을 형성하는 대신 워드라인 위에 도핑된 폴리실리콘을 증착한 후 산소와 염소의 혼합 플라즈마를 이용하여 셀부에만 잔류시키므로서 설계상의 오버레이 마진을 확보하고 별도의 식각장비가 필요하지 않고 공정을 단순화시켜 콘택의 균일성과 재현성을 확보하도록 한 반도체장치의 콘택플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a plug of a semiconductor device, and more particularly, by depositing doped polysilicon on a word line instead of forming a self-aligned contact when forming a contact, and remaining only in a cell part using a mixed plasma of oxygen and chlorine. The present invention relates to a method for forming a contact plug of a semiconductor device which secures a overlay margin of a design and does not require an additional etching equipment, thereby simplifying a process to secure uniformity and reproducibility of a contact.
종래 디램(DRAM)소자의 콘택 형성방법에서는 반응성이온식각법(reactive ion etching), 플라즈마 타입등의 기존의 플라즈마를 이용한 방식으로 진행되며 사용되는 기체로는 Ar, CF4, CHF3등의 혼합기체를 사용하여 왔고 일부 고밀도 플라즈마를 이용하는 경우에는 C2F6만을 첨가하여 콘택홀 형성공정을 진행하여 왔다.The conventional dynamic random access memory (DRAM) in the contact method of forming a device, reactive ion etching (reactive ion etching), to a gas that is used is conducted in a manner using conventional plasma such as a plasma-type mixed, such as Ar, CF 4, CHF 3 gas In the case of using some high density plasma, only C 2 F 6 was added to the contact hole forming process.
일반적으로 실리콘 기판 위에 산화막이 두껍게 증착되고 그위에 콘택홀 형성을 위한 포토레지스트패턴이 형성되는데 콘택홀이 형성된 후의 실리콘기판의 표면도 일부 식각되어진다.In general, a thick oxide film is deposited on a silicon substrate, and a photoresist pattern for forming a contact hole is formed thereon. The surface of the silicon substrate after the contact hole is also partially etched.
종래 기술에 따른 디램소자의 셀부에 미세 콘택홀 형성방법은 다음과 같다.A method of forming a fine contact hole in a cell portion of a DRAM device according to the prior art is as follows.
산화막과 질화막의 고선택비를 이용한 자기정렬 콘택(self-aligned contact)형성공정을 이용하여 셀부에 층간절연층을 제거하여 콘택홀을 형성한다. 이때, 워드라인과 콘택홀에 형성되는 플러그와의 단락현상을 방지하기 위하여 워드라인 위에 캡핑용 질화막을 두껍게 형성하고 또한, 캡핑용 질화막 위에 식각정지막으로 이용되는 배리어 질화막을 기판 표면에 형성한다.A contact hole is formed by removing an interlayer insulating layer in the cell part by using a self-aligned contact forming process using a high selectivity ratio between an oxide film and a nitride film. In this case, in order to prevent a short circuit between the word line and the plug formed in the contact hole, a capping nitride film is formed thick on the word line, and a barrier nitride film used as an etch stop film is formed on the substrate surface on the capping nitride film.
차세대 고집적소자 형성공정중 곤란한 점의 하나는 0.2㎛ 이하의 홀(hole)을 패터닝하는 문제이다. 현재 일반적으로 사용되는 사진공정장비로 요구되는 해상도와 설계상의 오버레이 마진을 만족시키기 곤란하다.One of the difficulties in the next generation of highly integrated device formation process is the problem of patterning holes of 0.2 μm or less. It is difficult to meet the resolution and design overlay margin required by the photo processing equipments currently used.
이러한 문제점을 극복하기 위해 사용되는 방법이 자기정렬콘택(self-aligned contact) 형성방법이다. 산화막/질화막의 식각선택비가 큰 식각공정을 질화실리콘 배리어막이 형성된 셀부 콘택형성공정에 이용하므로서 오버레이 마진을 늘릴수 있고, 식각 프로파일을 경사지게 형성하므로서 최대 선폭(critical dimension)을 0.2㎛ 이하로 형성할 수 있다.The method used to overcome this problem is a method of forming a self-aligned contact. By using the etching process with a large etching selectivity of the oxide film / nitride film in the cell contact forming process in which the silicon nitride barrier film is formed, the overlay margin can be increased, and the etch profile is inclined to form a maximum critical dimension of 0.2 μm or less. have.
그러나, 이러한 자기정렬콘택 형성방법 역시 홀의 선폭이 0.15㎛ 이하로 되면, 사진공정의 해상도가 저하되어 현재의 장비로 신뢰성 있는 홀을 형성하기 곤란하다.However, such a self-aligned contact forming method is also difficult to form a reliable hole with the current equipment when the line width of the hole is 0.15㎛ or less, the resolution of the photo process is reduced.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치 플러그 형성용 콘택홀 형성방법을 도시하는 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a contact hole for forming a semiconductor device plug according to the related art.
도 1a를 참조하면, 트렌치형 필드산화막(11)이 형성된 반도체기판인 실리콘기판(10)상에 게이트절연막(12)을 열산화막으로 형성한 후 게이트 형성을 위한 도핑된 폴리실리콘층(13)을 증착하여 형성한 다음 그위에 캡핑용절연막으로 질화막(14)을 증착하여 형성하고 사진식각공정을 실시하여 워드라인(13)인 게이트(13)를 패터닝하여 형성한다.Referring to FIG. 1A, a gate insulating layer 12 is formed as a thermal oxide layer on a silicon substrate 10, which is a semiconductor substrate on which a trench type field oxide layer 11 is formed, and then a doped polysilicon layer 13 is formed to form a gate. After the deposition, the nitride layer 14 is formed by depositing a capping insulating layer thereon, and the gate 13, which is the word line 13, is patterned by performing a photolithography process.
그리고 게이트(13)를 이용하여 소스/드레인인 저농도 불순물 확산영역을 형성한 다음, 게이트패턴을 포함하는 기판 전면에 산화막을 화학기상증착법으로 증착한 후 에치백하여 게이트 측벽 스페이서(15)를 형성한다.After forming the source / drain low concentration impurity diffusion region using the gate 13, an oxide film is deposited on the entire surface of the substrate including the gate pattern by chemical vapor deposition, and then etched back to form the gate sidewall spacer 15. .
그리고 기판의 전면에 고농도 불순물 이온 주입을 실시하여 저농도 불순물 확산영역과 함께 LDD형 소스 드레인(16)을 형성한다.A high concentration of impurity ions are implanted into the entire surface of the substrate to form an LDD type source drain 16 together with a low concentration of impurity diffusion region.
그 다음 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화막(17)을 증착하여 배리어막(17)을 측벽 스페이서(15) 표면을 포함하는 기판(10)의 전면에 형성한다.Next, a nitride film 17 is deposited by chemical vapor deposition (hereinafter, referred to as CVD) to form a barrier film 17 on the entire surface of the substrate 10 including the surface of the sidewall spacers 15.
그리고, 질화막으로 이루어진 배리어층(17) 위에 층간절연층(18)을 워드라인(13) 사이의 골을 매립하도록 두껍게 증착한다. 이때 층간절연층으로 BPSG, PETEOS, USG 등을 사용할 수 있다.The interlayer insulating layer 18 is thickly deposited on the barrier layer 17 made of a nitride film so as to fill the valleys between the word lines 13. At this time, BPSG, PETEOS, USG, etc. may be used as the interlayer insulating layer.
상기에서 기판(10)은 불순물영역(16)이 확산된 반도체기판이거나 또는, 하부 배선층(도시되지 않음)일 수도 있다.The substrate 10 may be a semiconductor substrate in which the impurity region 16 is diffused or a lower wiring layer (not shown).
도 1b를 참조하면, 층간절연층(18) 상에 포토레지스트를 도포한 후 노광 및 현상에 의해 층간절연층(18)의 소정 부분을 노출시키는 포토레지스트패턴(19)을 형성한다. 이 때, 층간절연층(18)의 노출된 부분은 반도체기판(10)의 불순물영역(16) 및 게이트(13)의 상부 일부 표면과 대응한다.Referring to FIG. 1B, after the photoresist is applied on the interlayer insulating layer 18, a photoresist pattern 19 is formed to expose a predetermined portion of the interlayer insulating layer 18 by exposure and development. In this case, the exposed portion of the interlayer insulating layer 18 corresponds to the surface of the upper portion of the impurity region 16 and the gate 13 of the semiconductor substrate 10.
도 1c를 참조하면, 포토레지스트가 제거된 부분을 통하여 Ar, CHF3, CF4의 혼합기체 플라즈마를 사용한 건식식각을 실시한다. 이때, 노출된 층간절연층은 제거되고 배리어층(17)의 일부 표면이 노출되면서 콘택홀이 형성된다. 그러나, 노출된 배리어층(17)이 불순물 확산영역(16)의 표면을 보호하고 있으므로 기판 표면은 콘택홀 식각공정에서 손상을 입지 않는다.Referring to FIG. 1C, dry etching using a mixed gas plasma of Ar, CHF 3 , and CF 4 is performed through the portion where the photoresist is removed. In this case, the exposed interlayer insulating layer is removed and a portion of the barrier layer 17 is exposed to form a contact hole. However, since the exposed barrier layer 17 protects the surface of the impurity diffusion region 16, the substrate surface is not damaged in the contact hole etching process.
도 1d를 참조하면, 노출된 배리어층을 식각하여 콘택홀(H) 부위의 캡핑용 질화막(14)과 측벽 스페이서(15)의 표면, 그리고 불순물 확산영역(16) 표면을 노출시키므로서 콘택홀 형성공정을 완료한다.Referring to FIG. 1D, the exposed barrier layer is etched to expose the surface of the capping nitride layer 14, the sidewall spacer 15, and the surface of the impurity diffusion region 16 in the contact hole H, thereby forming a contact hole. Complete the process.
이후, 도시되지는 않았지만, 콘택홀(H)에 도핑된 폴리실리콘 또는 텅스텐 등의 도전체를 형성하여 플러그를 형성한다.Subsequently, although not shown, a plug is formed by forming a conductor such as polysilicon or tungsten that is doped in the contact hole H.
그러나, 상술한 종래 기술에 따른 플러그 형성방법은 콘택홀 형성용 식각시 층간절연층과 배리어층의 높은 식각선택비가 요구되어 이를 위한 전용 식각장비가 필료하고, 홀의 싸이즈가 감소함에 따라 종횡비가 증가하여 워드라인의 질화막에 대한 침식이 심화되며, 콘택홀 형성공정 및 플러그형성공정등의 많은 공정이 필요하여 전체 공정수가 증가하고, 또한, 노광에서 해상도에 한계가 있으므로 콘택홀의 균일성과 재현성이 열화되는 문제점이 있다.However, the above-described plug forming method according to the related art requires a high etching selectivity of the interlayer insulating layer and the barrier layer during etching for forming the contact hole, and thus requires a dedicated etching device for this, and the aspect ratio increases as the hole size decreases. The erosion of the nitride film of the word line is intensified, and many processes such as a contact hole forming process and a plug forming process are required, and the total number of processes increases. Also, since the resolution is limited in exposure, the contact hole quality and reproducibility deteriorate. There is this.
따라서, 본 발명의 목적은 콘택 형성시 자기정렬콘택을 형성하는 대신 워드라인 위에 도핑된 폴리실리콘을 증착한 후 산소와 염소의 혼합 플라즈마를 이용하여 셀부에만 잔류시키므로서 설계상의 오버레이 마진을 확보하고 별도의 식각장비가 필요하지 않고 공정을 단순화시켜 콘택의 균일성과 재현성을 확보하도록 한 반도체장치의 콘택플러그 형성방법을 제공하는데 있다.Therefore, an object of the present invention is to deposit overlay doped polysilicon on the word line instead of forming a self-aligned contact when forming a contact, and to maintain the overlay margin on the design by remaining only in the cell portion using a mixed plasma of oxygen and chlorine The present invention provides a method for forming a contact plug of a semiconductor device in which a uniform process and a reproducibility of a contact are secured by eliminating the need for etching equipment.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 플러그 형성방법은 불순물 확산영역과 캡절연막, 게이트라인, 게이트절연막, 게이트측벽 스페이서로 이루어진 복수개의 워드라인을 활성영역과 필드영역이 정의된 반도체기판에 형성하는 단계와, 복수개의 워드라인 사이의 공간에 도전성 물질로 복수개의 플러그를 형성하는 단계와, 필드영역에 형성된 플러그를 제거하는 단계를 포함하여 이루어진다.A plug forming method of a semiconductor device according to the present invention for achieving the above objects is a semiconductor substrate having a plurality of word lines consisting of an impurity diffusion region, a cap insulation layer, a gate line, a gate insulation layer, and a gate side wall spacer. And forming a plurality of plugs with a conductive material in a space between the plurality of word lines, and removing the plugs formed in the field region.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 콘택홀 플러그 형성방법을 도시하는 공정단면도1A to 1D are cross-sectional views illustrating a method of forming a contact hole plug in a semiconductor device according to the related art.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 폴리실리콘 플러그 형성방법을 도시하는 공정단면도2A to 2D are cross-sectional views showing a method for forming a polysilicon plug of a semiconductor device according to the present invention.
본 발명은 자기정렬콘택 형성방법 대신 셀 플러그 형성공정을 사용하여 진행된다. 자기정렬콘택이 워드라인과 측벽스페이서 형성 후 층간절연층을 형성한 것과는 달리, 셀 플러그 공정에서는 워드라인과 측벽스페이서 형성 후 도전층으로 도핑된 폴리실리콘층을 증착한 다음 평탄화공정을 실시한 후 필드영역에 있는 폴리실리콘층을 사진식각공정으로 선택적으로 제거한다. 즉, 종래의 자기정렬콘택 공정이 활성영역과 비트라인의 전기적 연결을 위해 먼저 층간절연층을 식각한 다음 플러그를 형성한 것과는 정 반대되는 단계로 본 발명은 수행된다.The present invention proceeds using the cell plug forming process instead of the self-aligning contact forming method. Unlike the self-aligned contact forming the interlayer insulating layer after the word line and the sidewall spacers are formed, in the cell plug process, the polysilicon layer doped with the conductive layer is deposited after the wordline and the sidewall spacers are formed, followed by the planarization process. Selectively remove the polysilicon layer in the photolithography process. That is, the present invention is performed in a manner opposite to that of a conventional self-aligned contact process, in which an interlayer insulating layer is first etched and then a plug is formed for electrical connection between an active region and a bit line.
본 발명은 0.2㎛2셀을 기준으로, 노광공정에서 폴리실리콘이 제거될 부위만을 선(line)이나 섬(island)의 형태로 디파인하므로 종래에 콘택홀 형성 부위를 디파인 하는 것 보다 훨씬 용이하다. 소자설계시, 오버레이 마진은 자기정렬콘택의 경우 거의 없으나 셀 플러그 공정에서는 확보된다.According to the present invention, since only the portions from which polysilicon is to be removed in the exposure process based on 0.2 μm 2 cells are defined in the form of lines or islands, the present invention is much easier than those of conventionally forming contact hole forming sites. In device design, overlay margins are rare for self-aligned contacts but are secured in cell plug processes.
셀 플러그 형성공정은 비트라인과 활성영역을 연결하기 위한 공정이므로 폴리실리콘이 제거되는 부위에 폴리실리콘이 절대로 잔류하여서는 않된다. 워드라인 사이의 공간에 형성된 폴리실리콘을 제거하기 위하여 적절한 등방성 식각방법이 요청되므로, 헬리콘 타입의 고밀도 플라즈마 식각장치에서 염소와 산소의 혼합 플라즈마를 사용한다. 이때, 산소와 염소의 총 유량에서 산소의 유량은 10-20%일때 폴리실리콘이 제거되고 워드라인 등의 프로파일도 유지된다. 산화막에 대한 선택비는 15|1에서 20|1까지 가능하며, 포토레지스트의 선택비도 약 2:1이 된다.Since the cell plug forming process is a process for connecting the bit line and the active region, the polysilicon should never remain in the region where the polysilicon is removed. Since an appropriate isotropic etching method is required to remove the polysilicon formed in the space between the word lines, a mixed plasma of chlorine and oxygen is used in the helicon type high density plasma etching apparatus. At this time, when the flow rate of oxygen in the total flow rate of oxygen and chlorine is 10-20%, polysilicon is removed and the profile of the word line is maintained. The selectivity to the oxide film can be from 15 | 1 to 20 | 1, and the selectivity of the photoresist is also about 2: 1.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 폴리실리콘 플러그 형성방법을 도시하는 공정단면도이다.2A to 2D are cross-sectional views illustrating a method for forming a polysilicon plug of a semiconductor device according to the present invention.
도 2a를 참조하면, 활성영역과 필드영역을 정의하는 트렌치형 필드산화막(21)이 형성된 반도체기판인 실리콘기판(20)상에 게이트절연막(22)을 열산화막으로 형성한 후 게이트 형성을 위한 도핑된 폴리실리콘층(23)을 증착하여 형성한 다음 그위에 캡핑용절연막으로 질화막(24)을 증착하여 형성하고 사진식각공정을 실시하여 워드라인(23)인 게이트라인(23)을 패터닝하여 형성한다.Referring to FIG. 2A, a gate insulating layer 22 is formed as a thermal oxide layer on a silicon substrate 20, which is a semiconductor substrate having a trench type field oxide layer 21 defining an active region and a field region, and then doped to form a gate. Formed by depositing the polysilicon layer 23 formed thereon and then depositing a nitride film 24 on the capping insulating layer thereon and performing a photolithography process to pattern the gate line 23, which is a word line 23. .
그리고 게이트라인(23)를 이용한 이온주입으로 기판의 활성영역에 소스/드레인인 저농도 불순물 확산영역을 형성한 다음, 워드라인을 포함하는 기판(20) 전면에 산화막을 화학기상증착법으로 증착한 후 에치백하여 게이트 측벽 스페이서(25)를 형성한다.After ion implantation using the gate line 23 to form a low concentration impurity diffusion region as a source / drain in the active region of the substrate, an oxide film is deposited on the entire surface of the substrate 20 including the word line by chemical vapor deposition. The back side is formed to form the gate sidewall spacer 25.
그리고 기판(20)의 전면에 고농도 불순물 이온 주입을 실시하여 저농도 불순물 확산영역과 함께 LDD형 소스 드레인(26)을 형성한다.A high concentration of impurity ions are implanted into the entire surface of the substrate 20 to form the LDD type source drain 26 together with the low concentration impurity diffusion region.
그 다음 도전성 플러그를 형성하기 위하여 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 불순물이 도핑된 폴리실리콘층(27)을 증착하여 측벽 스페이서(25) 표면을 포함하는 기판(20)의 전면에 형성한다.Subsequently, the substrate 20 including the surface of the sidewall spacer 25 is deposited by depositing a polysilicon layer 27 doped with impurities by a chemical vapor deposition (CVD) method to form a conductive plug. Form on the front of the.
도 2b를 참조하면, 캡핑용 질화막(24)을 식각정지층으로 이용하는 평탄화공정을 폴리실리콘층에 실시한다. 이때, 평탄화공정은 CMP(Chemical-Mechanical Polishing, 이하 CMP라 칭함)공정으로 실시하거나 에치백 공정으로 실시한다.Referring to FIG. 2B, a planarization process using the capping nitride film 24 as an etch stop layer is performed on the polysilicon layer. In this case, the planarization process may be performed by a chemical-mechanical polishing (CMP) process or an etch back process.
따라서, 워드라인(23) 사이에는 잔류한 폴리실리콘층(270)으로 이루어진 플러그(270)가 형성된다.Accordingly, a plug 270 formed of the remaining polysilicon layer 270 is formed between the word lines 23.
도 2c를 참조하면, 노출된 캡핑용질화막(24)과 플러그(270) 표면을 포함하는 기판의 전면에 포토레지스트를 도포한 후 적절한 포토마스크로 노광 및 현상을 실시하여, 필드영역인 필드산화막(21)위에 형성된 플러그(270)를 제거하기 위한 활성영역 상부를 덮는 포토레지스트패턴을(28) 형성한다.Referring to FIG. 2C, after the photoresist is coated on the entire surface of the substrate including the exposed capping nitride film 24 and the surface of the plug 270, exposure and development are performed using an appropriate photomask, thereby forming a field oxide film as a field region. A photoresist pattern 28 is formed to cover the top of the active region for removing the plug 270 formed on the top surface 21.
도 2d를 참조하면, 워드라인(23) 사이의 공간에 형성되고 포토레지스트패턴으로 보호되지 않는 부위의 폴리실리콘으로 이루어진 플러그를 제거하기 위하여 적절한 등방성 식각을 기판의 전면에 실시한다. 이때, 식각은 헬리콘 타입의 고밀도 플라즈마 식각장치에서 염소와 산소의 혼합 플라즈마를 사용하며, 산소와 염소의 총 유량에서 산소의 유량은 10-20%일때 폴리실리콘이 제거되고 워드라인 등의 프로파일도 유지된다. 산화막에 대한 선택비는 15|1에서 20|1까지 가능하며, 포토레지스트의 선택비도 약 2:1이 된다.Referring to FIG. 2D, an appropriate isotropic etching is performed on the entire surface of the substrate in order to remove a plug made of polysilicon in a portion formed between the word lines 23 and not protected by the photoresist pattern. At this time, the etching uses a mixed plasma of chlorine and oxygen in the helicon-type high-density plasma etching apparatus, and polysilicon is removed when the oxygen flow rate is 10-20% at the total flow rate of oxygen and chlorine, and the profile of the word line, etc. maintain. The selectivity to the oxide film can be from 15 | 1 to 20 | 1, and the selectivity of the photoresist is also about 2: 1.
따라서, 본 발명은 콘택 형성시 자기정렬콘택을 형성하는 대신 워드라인 위에 도핑된 폴리실리콘을 증착한 후 산소와 염소의 혼합 플라즈마를 이용하여 셀부에만 잔류시키므로서 설계상의 오버레이 마진을 확보하고 별도의 식각장비가 필요하지 않고 공정을 단순화시켜 콘택의 균일성과 재현성을 확보하는 장점이 있다.Therefore, in the present invention, instead of forming a self-aligned contact at the time of contact formation, the doped polysilicon is deposited on the word line, and then remains only in the cell part using a mixed plasma of oxygen and chlorine to secure overlay margin on the design and separate etching. It does not require equipment and has the advantage of simplifying the process to ensure uniformity and reproducibility of the contact.
Claims (6)
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| KR1019980055469A KR20000039964A (en) | 1998-12-16 | 1998-12-16 | Method for plug for forming semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030001104A (en) * | 2001-06-28 | 2003-01-06 | 주식회사 하이닉스반도체 | A forming method of self align contact using ArF photo resist |
| KR100850080B1 (en) * | 2006-12-27 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Method of manufacturing transistor in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5100838A (en) * | 1990-10-04 | 1992-03-31 | Micron Technology, Inc. | Method for forming self-aligned conducting pillars in an (IC) fabrication process |
| KR100190047B1 (en) * | 1996-06-20 | 1999-06-01 | 윤종용 | Method of forming shallow junction |
| KR100209223B1 (en) * | 1996-10-05 | 1999-07-15 | 김영환 | Semiconductor device manufacturing method for forming contact |
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1998
- 1998-12-16 KR KR1019980055469A patent/KR20000039964A/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5100838A (en) * | 1990-10-04 | 1992-03-31 | Micron Technology, Inc. | Method for forming self-aligned conducting pillars in an (IC) fabrication process |
| KR100190047B1 (en) * | 1996-06-20 | 1999-06-01 | 윤종용 | Method of forming shallow junction |
| KR100209223B1 (en) * | 1996-10-05 | 1999-07-15 | 김영환 | Semiconductor device manufacturing method for forming contact |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030001104A (en) * | 2001-06-28 | 2003-01-06 | 주식회사 하이닉스반도체 | A forming method of self align contact using ArF photo resist |
| KR100850080B1 (en) * | 2006-12-27 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Method of manufacturing transistor in semiconductor device |
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