KR100361515B1 - Method of fabricating a contact in a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a contact portion of a semiconductor device. In particular, a final upper insulating layer in which a contact hole is formed is formed by using insulating films having a high etch selectivity such as a nitride film / oxide film and a fine contact hole. In order to secure a process margin by sequentially etching the insulating layers stacked in the first etching step having the slanted etch profile and the second etching step having the vertical etch profile, the transient etching problem of the conductive layer for plug formation filling the fine contact hole is solved. The present invention relates to a method for forming a memory device contact portion of a semiconductor device to solve the problem and to improve the reliability of the memory device. The present invention includes forming a first insulating layer on a substrate, forming an etch stop layer on the first insulating layer with an insulating film having a large etching selectivity with the first insulating layer, and a second insulating layer on the etch stop layer. Forming a layer, forming a cap-conducting film on the second insulating layer, removing a predetermined portion of the cap-conducting film and the second insulating layer, and an etch profile is inclined and the surface of the etch stop layer is removed. Forming a first opening through which the first opening is exposed; and removing a predetermined portion of the etch stop layer and the first insulating layer exposed by the first opening to expose a predetermined portion of the substrate. And a second etching step of forming a second opening having the second opening.

Description

Method of fabricating a contact in a semiconductor device {Method of fabricating a contact in a semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a contact portion of a semiconductor device, and in particular, to form a final upper insulating layer on which a contact hole is formed by using insulating films having a laminated structure such as a nitride film / oxide film and to form a fine contact hole. The process layer is secured by sequentially etching the insulating layers stacked in the first etching step having the second etching step and the second etching step having the vertical etching profile, and the transient etching problem of the plug forming conductive layer filling the fine contact hole is solved. A method of forming a memory device contact portion of a semiconductor device to improve the reliability of the semiconductor device.

In the prior art of manufacturing a memory device such as a DRAM cell of a semiconductor device, in order to electrically connect a storage electrode node of a capacitor and an impurity diffusion region for a source / drain, a first contact hole and a first contact hole are filled in an interlayer insulating layer under the device. After forming the first plug, the bit line, and the like, the interlayer insulating layer is formed again, and a predetermined portion is removed to form a second contact hole exposing the upper surface of the first plug. To form.

However, in the related art, since the insulating layer in which the second contact hole is formed is formed only of an oxide film, the second plug filling the second contact hole is formed as an etch back, then a nitride film is formed and the storage electrode forming portion is defined. 2 It is difficult to control the size of the contact hole, which causes the problem of the bit line and short circuit in the vicinity. If the amount of recess is not accurately controlled by the excessive etching amount of the second plug by the etch back, the storage electrode and the bit line A short circuit problem or a problem such as a decrease in contact resistance between the first plug and the second plug due to residual nitride film measurement occurs.

1A to 1H are cross-sectional views illustrating a method of manufacturing a contact portion of a semiconductor device according to the related art, and illustrate a method of forming a contact portion at a capacitor and a bit line in a DRAM cell.

Referring to FIG. 1A, a first interlayer insulating layer 12 is formed of a source / drain impurity diffusion region 11 and an oxide film on a first conductivity-type semiconductor substrate 10, which is a p-type silicon substrate. After removing a predetermined portion of the interlayer dielectric layer to form a first contact hole exposing the surface of the impurity diffusion region 11, the first contact hole is filled with a conductor such as doped polysilicon to fill the first plug 13. Form.

A second interlayer insulating layer 14 is formed on the first interlayer insulating layer 12 including the surface of the first plug 13 by a high temperature low pressure dielectric (HLD) or the like to a predetermined thickness, and thereafter, a bit line is formed thereon. (15) is formed.

Then, the first nitride film 16 for bit line insulation is deposited on the second interlayer insulating layer 14 including the surface of the bit line 15 by a thin film (300-500 kPa) by chemical vapor deposition.

Next, a first p-TEOS film 17 is formed on the first nitride film 16 to a thickness of 500-1000 GPa, and then an oxide film is deposited on the 17 to form a third interlayer insulating layer 18 for planarization. To form a thickness of 3000-6000 GPa, a second p-TEOS film 19 is thinly formed on the surface of the third interlayer insulating layer 18 (500-1000 GPa).

Then, the cap-polysilicon layer 20 is formed on the second p-TEOS film 19 by a predetermined thickness (1500-2500 kPa), and a photosensitive film is applied thereon, and then the first plug is exposed and developed. (13) A first photoresist pattern 21 defining a second contact hole formation site for exposing the surface is formed.

Referring to FIG. 1B, a cap-polysilicon layer / second p-TEOS film / third interlayer insulating layer / first p-TEOS film / nitride film / first interlayer insulating layer of a portion not protected by the first photoresist pattern is illustrated. Cap-polysilicon layer 200 / second p-TEOS film 190 / third interlayer insulating layer 180 / first p-TEOS film 170 / nitride film 160 / first layer remaining after removal After forming the second contact hole H1 formed by the insulating layer 140, the first photoresist pattern is removed.

At this time, the etching conditions of the cap-silicon layer 200 is dry etching by performing for 40-70 seconds with 3-7mT, 300-600Ws, 100-300Wb, 80-120 sccm Cl ₂ , 2-8 sccm N ₂ , The etching conditions of the oxide films are dry etched by 30-50 mT, 1800-2200Ws, 800-1500Wb, 30-60 sccm CHF ₃ , 5-10 sccm O ₂ , and 300-700 sccm Ar for 100-140 seconds.

At this time, the key to the formation of the second contact hole is the diameter A1 of the second contact hole H1 penetrating between the bit lines 15. According to the size of the diameter A1, the thickness A2 of the insulating layers that insulate the bit line may be determined to cause a short circuit between the plug and the bit line. This is because the etching profile is inclined when the insulating film made of the oxide film is etched. Therefore, in the prior art, it is difficult to control such diameter A1 or thickness A2.

Referring to FIG. 1C, a doped polysilicon layer 22 is deposited by chemical vapor deposition on the remaining cap-polysilicon layer 200 to sufficiently fill the first contact hole to form a second plug. . At this time, the deposition thickness is 3000-5000 kPa.

Referring to FIG. 1D, the doped polysilicon layer and the cap-polysilicon layer are etched back to completely expose the surface of the second p-TEOS layer 190 and include a polysilicon layer remaining in the second contact hole. The second plug 220 is formed. At this time, the etch back is performed by dry etching and the etching conditions are performed by 3-7mT, 20-50W, 10-30 sccm SF ₆ for 80-120 seconds. Accordingly, the recessed polysilicon thickness R1 is about 300-1000 kPa, and the amount of recess can be up to 2000 kPa if necessary. At this time, an important factor is to minimize the loss of polysilicon.

Referring to FIG. 1E, the nitride film 23 is formed by chemical vapor deposition on the surface of the second p-TEOS film 190 including the exposed surface of the second plug 220 as a stopper. At this time, the deposition thickness of the nitride film 23 is set to 500-1000 kPa.

Referring to FIG. 1F, a fourth interlayer insulating layer 24 is formed by depositing an oxide film on the nitride film 23. At this time, the fourth interlayer insulating layer 24 is formed to a thickness of about 10000-15000 kPa.

The fourth interlayer insulating layer 24 disposed on the storage electrode forming portion is formed by applying photoresist to the surface of the fourth interlayer insulating layer 24 and then exposing and developing using an exposure mask defining a storage electrode forming portion of the capacitor. A photoresist pattern 25 exposing the surface is formed.

Referring to FIG. 1G, the surface of the second plug 220 and the surface thereof 220 may be sequentially removed by sequentially removing the fourth interlayer insulating layer / nitride film / second p-TEOS film / third interlayer insulating layer which are not protected by the photoresist pattern. An opening is formed to expose a portion of the third interlayer insulating layer 180 extending from the.

At this time, the oxide film is removed by two stages of dry etching and the etching conditions are first, 30-50mT, 1800-2200Ws, 800-1500Wb, 10-20 sccm C ₄ F ₈ , 5-10 sccm O ₂ , 300-700 sccm Ar After performing 150-200 seconds to one-step etching, and then 30-70mT, 1800-2200Ws, 800-1500Wb, 30-60 sccm CHF ₃ , 300-700 sccm Ar is carried out for 10-20 seconds to etch in two steps.

The most important thing in forming the openings in which the storage electrode pattern is to be formed is the distance B1 from the surface of the exposed third interlayer insulating layer 180 forming the bottom surface of the opening to the surface of the first p-TEOS film 170. Forming the distance B1 as large as possible can prevent a short circuit between the bit line 15 and the storage electrode.

That is, in FIG. 1D, when the polysilicon loss R1 is greater than 1000 μs, the etching amount of the third interlayer insulating layer 180 increases when the opening is formed, so that the bit line 15 disposed under the opening may be exposed.

Referring to FIG. 1H, polysilicon doped to form a storage electrode on an insulating layer 240 having an opening including the exposed surface of the second plug 220 and the surface of the third interlayer insulating layer 180 and the fourth insulating layer 240. A conductive film 25 such as the above is formed by vapor deposition by chemical vapor deposition. In this case, when the conductor film 25 is formed of doped polysilicon, the thickness thereof is 500-1000 kPa.

Although not shown in the drawing, the conductive film 25 is appropriately patterned in a subsequent process to complete the storage electrode, and a dielectric film and a pleated electrode are formed thereon to manufacture a capacitor.

However, the above-described conventional semiconductor device controls the size of the diameter when forming the second contact hole for forming the second plug when the capacitor has a structure on the bit line in the highly integrated DRAM cell. It may be difficult to cause a short circuit between adjacent bit lines and the like, and a large amount of polysilicon loss may occur when the second plug is formed, and if the interlayer insulating layer under the storage electrode is excessively etched, the storage electrode and the bit line of the capacitor may be shorted. If the lower interlayer insulating layer is not sufficiently etched, the nitride film may remain in a sidewall shape at a portion where the second plug is recessed to increase the contact resistance between the second plug and the first plug.

Accordingly, an object of the present invention is to form a final upper insulating layer on which a contact hole is formed by using insulating films having a stacked structure such as a nitride film / oxide film, and a vertical etching process with a first etching step having a etch profile to form a fine contact hole. A semiconductor device is fabricated to sequentially process insulating layers stacked in a second etching step having a profile to secure a process margin, and to solve a problem of transient etching of a plug forming conductive layer filling a fine contact hole, thereby improving reliability of a memory device. A memory device contact portion forming method is provided.

According to another aspect of the present invention, there is provided a method of manufacturing a contact portion of a semiconductor device, the method including forming a first insulating layer on a substrate, forming an etch stop layer on the first insulating layer, and forming a etch stop layer on the etch stop layer. Forming a second insulating layer, forming a cap-conductive film on the second insulating layer, and removing a predetermined portion of the cap-conductive film and the second insulating layer to incline the etch profile and stop the etch stop. A first etching step of forming a first opening exposing the surface of the film; a vertical portion of removing the predetermined portion of the etch stop layer and the first insulating layer exposed by the first opening to expose a predetermined portion of the substrate; And a second etching step of forming a second opening having an etching profile.

According to another aspect of the present invention, there is provided a method of manufacturing a contact portion of a semiconductor device, wherein an impurity diffusion region penetrates through a first insulating layer and the first insulating layer on a semiconductor substrate, and the impurity diffusion is performed. Forming a first plug in contact with a region, forming a second insulating layer on the first insulating layer including the first plug surface and forming a bit line on the second insulating layer; Forming a third insulating layer on the second insulating layer including a line; forming a fourth insulating layer / etch stop film / fifth insulating layer on the third insulating layer; Forming a cap-conductive film on the substrate, removing a predetermined portion of the cap-conductive film and the fifth insulating layer to expose a surface of the etch stop film, and forming a first opening in which the etch profile is inclined And removing the exposed etch stop layer and the fourth insulating layer, the third insulating layer, and the second insulating layer disposed below, exposing the surface of the first plug to form a second opening having a vertical etch profile. Forming a conductive layer on the remaining cap-conductive film including the first opening and the second opening, and etching back the conductive layer and the cap-conducting film to form the fifth insulating layer. Forming a second plug exposing the surface of the layer and filling the first and second openings, forming a sixth insulating layer on the surface of the fifth insulating layer including the second plug surface and Removing a predetermined portion of the sixth insulating layer and the fifth insulating layer to form a third opening that partially exposes the second plug surface and the etch stop layer, and at the inner surface of the third opening; It characterized in that it comprises a step of forming a capacitor.

1A to 1H are cross-sectional views illustrating a method of manufacturing a contact portion of a semiconductor device according to the related art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a contact portion of a semiconductor device according to the present invention.

In general, in a capacitor on bit line structure when forming a highly integrated DRAM cell, the possibility of shorting between the storage node contact and the bit line should be considered when forming the storage node. In order to solve this problem, in the related art, as the contact size of the second storage node is made small to secure a margin for an electrical short with the bit line, the second storage node contact separate from the first storage node contact due to the small contact size Must be formed and connected again, and a separate cylindrical storage node must be formed to secure the capacity of the capacitor.

The present invention controls the diameter of the second contact hole in which the second plug is formed when forming the storage electrode node contact and prevents the etching of the interlayer insulating layer under the storage electrode by forming an etch stop layer using a nitride film, thereby preventing the side surface between the second plug and the bit line. This prevents a short circuit and prevents a vertical short circuit between the storage electrode and the bit line.

Hereinafter, with reference to the accompanying drawings will be described the present invention.

2A to 2G are cross-sectional views illustrating a method of manufacturing a contact portion of a semiconductor device according to the present invention and illustrate a method of forming contact portions at a capacitor and a bit line in a DRAM cell as a memory device.

Referring to FIG. 2A, a first interlayer insulating layer 32 is formed of an n-type second conductive impurity diffusion region 31 for source / drain and an oxide film on a first conductive semiconductor substrate 30 that is a p-type silicon substrate. Next, after forming a first contact hole exposing a surface of the impurity diffusion region 31 by removing a predetermined portion of the first interlayer insulating layer, the first contact hole is filled with a conductor such as doped polysilicon. The first plug 33 is formed.

A second interlayer insulating layer 34 is formed to a predetermined thickness on a first interlayer insulating layer 32 including the surface of the first plug 33 by a high temperature low pressure dielectric (HLD) or the like, and then a bit line thereon. (35) is formed.

The first nitride film 36 for bit line insulation is deposited on the second interlayer insulating layer 34 including the surface of the bit line 35 by a thin film (300-500 kPa) by chemical vapor deposition.

Next, a first p-TEOS film 37 is formed on the first nitride film 36 to a thickness of 500 to 1000 占 퐉, and thereafter, an oxide film is deposited on the 37 to form a third interlayer insulating layer 38 for planarization. To form a thickness of 2500-6000Å.

Then, the second nitride film 39 is formed on the surface of the third interlayer insulating layer 38 to a thickness of 500-1500 Å to form an etch stop layer 39.

Next, a second p-TEOS film 40 is formed on the surface of the etch stop layer 39 made of a nitride film (1000-3000 mm 3).

Then, the cap-polysilicon layer 41 is deposited on the second p-TEOS film 40 to a predetermined thickness (1500-2500 kPa), and a photosensitive film is applied thereon, and then the first plug is exposed and developed. (33) A first photoresist pattern 42 defining a second contact hole formation site for exposing the surface is formed.

Referring to FIG. 2B, a cap-polysilicon layer / second p-TEOS film / nitride film / third interlayer insulation layer / first p-TEOS film / nitride film / first interlayer insulation in a region not protected by the first photoresist pattern The cap-polysilicon layer 410, the second p-TEOS film 400, the etch stop layer 390, the third interlayer insulating layer 380, and the first p-TEOS film 370 remaining after the layers were sequentially removed. ) And a second contact hole H2 surrounded by the exposed side of the first nitride film 360 / the second interlayer insulating layer 340, and then the first photoresist pattern is removed.

At this time, the etching conditions of the cap-silicon layer 410 is dry etching by performing for 40-70 seconds with 3-7mT, 300-600Ws, 100-300Wb, 80-120 sccm Cl ₂ , 2-8 sccm N ₂ .

The second p-TEOS layer 400 is dry etched so that the etching profile is inclined to reduce the diameter of the second contact hole. At this time, the etching conditions are performed until the etching stop film 390, which is a nitride film, is exposed using an etching gas such as C5F8 or C4F8, in which a polymer is generated, 30-50 mT, 1800-2400 Ws, 500-1000 Wb, 20-30 seconds with 10-30 sccm C ₅ F ₈ or C ₄ F ₈ , 10-20 sccm O ₂ , 300-700 Ar.

Then, using the diameter of the narrowed second p-TEOS film 400, the remaining nitride film and oxide films are continuously removed to have a vertical etching profile to expose the surface of the second plug 33. At this time, the etching conditions are carried out by 30-50mT, 1800-2400Ws, 1000-1500Wb, 30-60 sccm CHF ₃ , 5-10 sccm O ₂ , 300-700 sccm Ar for 50-100 seconds dry etching.

In this case, the key to the formation of the second contact hole is the diameter A3 of the second contact hole H2 penetrating between the bit lines 35. According to the size of the diameter A3, the thickness A4 of the insulating layers that insulate the bit line may be determined to cause a short circuit between the plug and the bit line. This is because the etching profile is inclined when the insulating film made of the oxide film is etched. Accordingly, in the embodiment of the present invention, the diameter A3 or the thickness A4 is controlled by two-step etching to prevent a short circuit between the plug and the bit line 35.

That is, in the embodiment of the present invention, the oxide film is divided into two steps, and in particular, in one-step etching, C ₅ H ₈ or C ₄ F ₈ , in which many polymers are formed, is used as an etching gas. The oxide film is etched to have an inclined etching profile of about 70-80 °. If there is no etch stop layer, it is difficult to etch the oxide film inclinedly. In the second etching process, the etch stop layer 390 and the third interlayer insulating layer 380 are etched vertically to adjust the diameter A3 of the second contact hole, thereby forming the bit line 35 and the second contact hole H2. Process margin for the thickness A4 in between can be secured.

Referring to FIG. 2C, the doped polysilicon layer 43 is formed by chemical vapor deposition on the remaining cap-polysilicon layer 410 to sufficiently fill the first contact hole to form the second plug. . At this time, the deposition thickness is 3000-5000 kPa.

Referring to FIG. 2D, the doped polysilicon layer and the cap-polysilicon layer are etched back without forming an etch mask to completely expose the surface of the oxide layer of the second p-TEOS layer 400, and at the same time, the second contact. A second plug 430 made of a polysilicon layer remaining in the hole is formed. At this time, the etch back is performed by dry etching and the etching conditions are performed by 3-7mT, 20-50W, 10-30 sccm SF ₆ for 80-120 seconds. Therefore, the thickness of the recessed polysilicon (R2) is about 300-1000 kPa, and the amount of recess can be up to 2000 kPa if necessary. At this time, an important factor is to minimize the loss of polysilicon.

Referring to FIG. 2E, a fourth interlayer insulating layer 44 is formed on the surface of the second p-TEOS film 400 including the exposed surface of the second plug 430 by an oxide film. At this time, the thickness of the fourth interlayer insulating layer 44 is formed to be about 10000-15000 Å thick.

The fourth interlayer insulating layer 44 disposed on the storage electrode forming portion is formed by applying photoresist to the surface of the fourth interlayer insulating layer 44 and then exposing and developing using an exposure mask that defines the storage electrode forming portion of the capacitor. A second photoresist pattern 45 exposing the surface is formed.

Referring to FIG. 2F, the surface of the second plug 430 and a portion of the etch stop layer 390, which is a nitride film, may be removed by sequentially removing the fourth interlayer insulating layer / second p-TEOS film which is not protected by the second photoresist pattern. An opening to be exposed is formed. In this case, the opening is formed to provide a portion where the storage electrode pattern of the capacitor is to be formed.

At this time, the oxide film is removed by two stages of dry etching and the etching conditions are first, 30-50mT, 1800-2200Ws, 800-1500Wb, 10-20 sccm C ₄ F ₈ , 5-10 sccm O ₂ , 300-700 sccm Ar After performing 150-200 seconds to one-step etching, and then 30-70mT, 1800-2200Ws, 800-1500Wb, 30-60 sccm CHF ₃ , 300-700 sccm Ar is carried out for 10-20 seconds to etch in two steps.

The most important thing in forming the openings in which the storage electrode pattern is to be formed is the distance B2 from the surface of the exposed third interlayer insulating layer 380 that forms the bottom portion of the opening to the surface of the first p-TEOS film 370. Since the distance B2 is fixed by the etch stop layer 390 which is a nitride film, a short circuit between the bit line 35 and the storage electrode to be formed in a subsequent process can be prevented.

Then, removing the second photoresist pattern by ashing, oxygen (O ₂ ashing).

Referring to FIG. 2G, an opening including the exposed surface of the second plug 430 and the surface of the etch stop layer 390 and polysilicon doped to form a storage electrode on the fourth interlayer insulating layer 440. The conductor film 45 is formed by vapor deposition by chemical vapor deposition. At this time, when the conductor film 45 is formed of doped polysilicon, the thickness thereof is 500-1000 kPa.

Although not shown in the drawing, the conductive film 45 is properly patterned in a subsequent process to complete the storage electrode, and a dielectric film and a pleated electrode are formed thereon to manufacture a capacitor.

Accordingly, the present invention controls the diameter of the second contact hole in which the second plug is formed when forming the storage electrode node contact and prevents the etching of the interlayer insulating layer under the storage electrode by forming an etch stop layer using a nitride film, thereby preventing the second plug and the bit line. By preventing side short circuits and preventing vertical short circuits between the storage electrodes and the bit lines, the capacitor formation margin is increased to maximize cell area efficiency.

Claims (7)

Forming a first insulating layer on the substrate, Forming an etch stop layer on the first insulating layer; Forming a second insulating layer on the etch stop layer; Forming a cap-conductive film on the second insulating layer; A first etching step of removing a predetermined portion of the cap-conductive film and the second insulating layer to form a first opening in which an etching profile is inclined and exposes the surface of the etching stop film; A second etching step of forming a second opening having a vertical etching profile exposing a predetermined portion of the substrate by removing a portion of the etch stop layer and the first insulating layer exposed by the first opening; Method for manufacturing a contact portion of a device. The method according to claim 1, And the first opening is formed by dry etching using an etching gas having a large amount of polymer generation. The method according to claim 1, And the first and second insulating layers are formed of an oxide film and the etch stop layer is formed of a nitride film. The method according to claim 1, After the second etching step, Forming a conductive layer on the cap-conductive film including the first opening and the second opening, the conductive layer being made of the same material as the cap-conducting film; And etching back the conductive layer and the remaining cap-conductive film to expose a surface of the second insulating film, and forming a plug made of the remaining conductive layer. . The method of claim 1, wherein the second insulating layer is formed to have a thickness sufficient to incline the etching profile of the first opening. Forming a first plug penetrating the first insulating layer and the first insulating layer and contacting the impurity diffusion region on a semiconductor substrate having an impurity diffusion region formed in a predetermined region; Forming a second insulating layer on the first insulating layer including the first plug surface and forming a bit line on the second insulating layer; Forming a third insulating layer on the second insulating layer including the bit line; Forming a fourth insulating layer / etch stop film / fifth insulating layer on the third insulating layer; Forming a cap-conductive film on the fifth insulating layer; Removing a predetermined portion of the cap-conductive film and the fifth insulating layer to expose a surface of the etch stop film and forming a first opening having an inclined etch profile; Removing the exposed etch stop layer and the fourth insulating layer / third insulating layer / second insulating layer disposed below, exposing the surface of the first plug to form a second opening having a vertical etch profile. Steps, Forming a conductive layer on the remaining cap-conductive film comprising the first opening and the second opening; Etching back the conductive layer and the cap-conductive film to expose a surface of the fifth insulating layer and form a second plug in contact with the first plug and filling the first opening and the second opening. Steps, Forming a sixth insulating layer on the surface of the fifth insulating layer including the second plug surface and removing a predetermined portion of the sixth insulating layer and the fifth insulating layer to remove the surface of the second plug surface and the etch stop layer. Forming a third opening that partially exposes the light; And forming a capacitor on the inner surface of the third opening. The method according to claim 6, And the first opening is formed by dry etching using an etching gas having a large amount of polymer generation.