KR20000040449A - Beat line formation of semiconductor device - Google Patents

Abstract

PURPOSE: A formation of the beat lines in a semiconductor device is obtained by forming the top of a beat line plug to an island form, and forming a beat line surface levelly through mitigating the situations winding at the contacting spot with the beat line. CONSTITUTION: A formation method of the beat lines in a semiconductor device consists of the following processes: a process to form plural word lines on a semiconductor substrate by which the active regions, the field regions, and the beat line contact spots were defined, herein plural word lines were consisted by impurity diffusion regions, capping dielectric layers, gate lines, gate dielectric layers, and gate side wall spacers; a process to form the plural plugs with the dielectric layers so as to be projected in the spaces of the beat line contact spots through filling up the spaces between the word lines; a process to form an inter layer dielectric on the capping dielectric layers and the conducting layers of the spots except the plugs which are projected as high as the height of the projected plugs; and a process to form the distribution wire to be connected with the projected plugs on the inter layers dielectric.

Description

Bit line formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to form a top portion of a bit line plug in an island shape to improve a process of bending at a contact portion with a bit line, thereby improving a process and flattening a bit line surface A method of forming a flattened bit line in a semiconductor device is disclosed.

One of the difficulties in the next generation of highly integrated device formation process is the problem of patterning holes of 0.2 μm or less. It is difficult to meet the resolution and design overlay margin required by the photo processing equipments currently used.

Therefore, instead of forming a self-aligned contact when forming a contact, a doped polysilicon is deposited on a word line, and then a predetermined portion is etched to remain only in the cell part, thereby securing an overlay margin in design and eliminating the need for a separate etching equipment. Simplification ensures contact uniformity and reproducibility. In this case, since the cell plug forming process is a process for connecting the bit line and the active region, the polysilicon should never remain in the region where the polysilicon is removed.

Then, an insulating film is formed on the entire surface of the substrate including the upper part of the plug. Then, the insulating film of the bit line contact portion is removed to expose the bit line contact plug surface, and then a conductive layer is formed on the insulating film to cover the plug surface. You will complete the line.

However, since the surface of the formed bit line is stepped as much as the thickness of the insulating film is removed from the contact portion, in order to obtain a flattened bit line surface profile, the conductive layer is deposited thicker than necessary, and then again CMP (chemical mechanical polishing) An additional step is required to planarize the surface of the conductive layer, for example, CMP).

1A to 1C are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the prior art.

Referring to FIG. 1A, a trench insulating field oxide layer 11 defining an active region and a field region is formed on a silicon substrate 10, which is a semiconductor substrate, to form a gate oxide layer 12 as a thermal oxide layer, and then doping for gate formation. The formed polysilicon layer is deposited and then formed by depositing a nitride film 14 with a capping insulating film thereon and performing a photolithography process to pattern the gate line 13, which is a word line 13.

In addition, by forming a low concentration impurity diffusion region that is a source / drain in the active region of the substrate by ion implantation using the word line 13, a chemical vapor deposition method is performed by using an insulating film as an insulating film on the entire surface of the substrate 10 including the word line 13. To be deposited.

Next, an oxide film is etched back to form a gate sidewall spacer 15 made of the remaining oxide film.

The high concentration ion implantation forms a high concentration impurity diffusion region (not shown) in the active region of the substrate around the gate 13.

Thus, a transistor having an LDD structure is formed and a word line connecting the transistor is formed.

Then, the doped polysilicon layer 16 is deposited by CVD to form a contact plug to be connected to the bit line.

In order to planarize the deposited polysilicon layer, chemical mechanical polishing is performed on the polysilicon layer to leave the planarized polysilicon layer 16 to form a plug 16.

Referring to FIG. 1B, an oxide film 17 is formed by depositing an interlayer insulating layer 17 on the surfaces of the exposed capping insulating film 14 and the planarized polysilicon layer 16 by CVD.

Then, a photoresist is applied on the oxide layer 17 to expose the surface of the plug 16 of the portion to be connected to the bit line, and then a photoresist pattern (not shown) is formed by performing exposure and development using an appropriate photomask. The oxide film in the portion not protected by the photoresist pattern is etched to expose the surface of the plug 16 on the bit line contact portion.

Referring to FIG. 1C, tungsten is deposited on the surface of the oxide film 17 including the exposed surface of the plug 16 as a conductive layer by CVD or sputtering, and then patterned by a photolithography process to form a bit line 18. . At this time, when the bit line metal layer is formed, the profile of the upper portion of the contact of the conductive layer deposited due to the step difference between the surface of the bit line contact plug 16 and the surface of the oxide film 18 may have a recessed shape.

Therefore, in order to form the bit line profile of the planarized contact portion, the conductive layer must be formed thicker than necessary, and then a planarization process such as a CMP process should be further performed.

However, since the bit line forming method of the semiconductor device according to the related art is formed so that a step occurs in a hole shape at a portion where a contact plug and a bit line contact the bit line contact portion, the bit line profile is curved. Since it is difficult to secure a margin in the process, there is a problem that an additional process such as a planarization process is required to solve this problem.

Accordingly, it is an object of the present invention to planarize a semiconductor device in which the upper portion of the bit line plug is formed in an island shape to improve the process of bending the contact portion with the bit line, thereby improving the process and forming a flattened bit line surface. To provide a bit line forming method.

A bit line forming method of a semiconductor device according to the present invention for achieving the above object is a plurality of word lines consisting of an impurity diffusion region, a cap insulation layer, a gate line, a gate insulation layer, a gate sidewall spacer and an active region, a field region and a bit line contact. Forming a portion in a semiconductor substrate having a defined region, forming a plurality of plugs with a conductive layer so as to fill the space between the word lines and protrude in the space of the bit line contact portion, and protrude the protrusion height of the protruding plug. Forming an interlayer insulating film on the conductive layer and the cap insulating film except for the plug, and forming a wiring connected to the protruding plug on the interlayer insulating film.

1A to 1C are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the prior art.

2A to 2C are cross-sectional views illustrating a method of forming a bit line in a semiconductor device according to the present invention.

The present invention forms an island-shaped protrusion on top of a contact plug instead of a hole in the bit line contact portion and a contact plug of the bit line contact portion, so that a curved portion is not formed when the conductive layer for the bit line is formed. It is possible to form a flattened bit line pattern without an additional process.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a planarization method of a semiconductor device and a plug formation method using the same according to the present invention.

Referring to FIG. 2A, a trench insulating field oxide layer 21 defining an active region and a field region is formed on the silicon substrate 20, which is a semiconductor substrate. After the polysilicon layer is formed by depositing, the nitride layer 24 is formed by depositing a capping insulating layer thereon, and a photolithography process is performed to pattern the gate line 23, which is a word line 23.

In addition, a low concentration impurity diffusion region (not shown), which is an LDD source / drain, is formed in an active region of the substrate 20 by ion implantation using the word line 23, and then the entire surface of the substrate 20 including the word line 23. The oxide film is deposited by chemical vapor deposition as an insulating film.

Next, an oxide film is etched back to form a gate sidewall spacer 25 made of the remaining oxide film.

A high concentration of ion implantation forms a high concentration impurity diffusion region (not shown) in the active region of the substrate around the gate 23 to form an LDD type source drain (not shown).

Thus, a MOS transistor having an LDD structure is formed and a word line connecting the morph transistor is formed.

Then, the doped polysilicon layer 26 is deposited by CVD to form a contact plug to be connected to the bit line.

In order to planarize the deposited polysilicon layer, chemical mechanical polishing (CMP) is performed on the polysilicon layer to leave the planarized polysilicon layer 16. In this case, the CMP process may be performed such that the polysilicon layer may remain on the capping insulating layer 24 to have a predetermined thickness.

Then, a photolithography process using a photoresist is performed on the remaining polysilicon layer to form an etch stop mask covering only the polysilicon layer of the bit line contact portion, and then an etch back process using the etch stop mask is performed using the insulating film 24 for capping. By using the etch stop layer to the polysilicon layer to form a bit line pad.

Accordingly, the surface of the substrate after the etch back process has a profile in which the plug 27 of the bit line contact portion protrudes over the surface of the capping insulating film 24 to have an island-shaped head.

As another method of forming the bit line pad, the polysilicon layer is planarized by the CMP method until the capping insulating film is exposed, and then the conductive layer is added to the entire surface of the substrate, and then the conductive layer is patterned by a photolithography process. The conductive layer may remain only on the bit line contacts.

Referring to FIG. 2B, an interlayer insulating film is deposited by an CVD method with an oxide film on the entire surface of the substrate 20 to cover the protruding bit line contact plug 27, and then the planarization process is performed by an etch back or a CMP process on the interlayer insulating film. To expose the surface of the protruding bit line contact plug 27. Therefore, the surface of the bitwise contact plug 27 and the surface of the interlayer insulating film 28 are positioned at the same level, and are automatically formed in a flattened shape on the conductive layer for bit line formation to be deposited thereafter.

Referring to FIG. 2C, tungsten is deposited as a conductive layer on the surface of the interlayer insulating film 28, which is an oxide film including the exposed bit line contact plug 26, by CVD or sputtering, and then patterned by a photolithography process. (29) is formed. At this time, when forming the bit line metal layer, since there is no step difference between the surface of the bit line contact plug 16 and the surface of the oxide film 18, the contact upper profile of the conductive layer to be deposited has a flat shape.

Therefore, in order to form the bit line profile of the planarized contact region, it is not necessary to form the conductive layer thicker than necessary and then further perform a planarization process such as a CMP process.

Therefore, the present invention forms an island-like protrusion on the contact plug instead of the conventional hole in the bit line of the contact portion and the contact plug, so that the curved portion is not formed when the conductive layer for the bit line is formed. Since it is possible to form a flattened bit line pattern without an additional process, there is an advantage of simplifying the process.

Claims (4)

Forming a plurality of word lines including an impurity diffusion region, a cap insulation layer, a gate line, a gate insulation layer, and a gate sidewall spacer on a semiconductor substrate having active regions, field regions, and bit line contact portions defined therein; Filling a space between the word lines and forming a plurality of plugs with a conductive layer to protrude from the space on the bit line contact; Forming an interlayer insulating film on the conductive layer and the cap insulating film except for the plug protruding by the protruding height of the protruding plug; And forming a wiring connected to the protruding plug on the interlayer insulating film. The method according to claim 1, wherein the wiring is a bit line. The method of claim 1, wherein the filling of the spaces between the word lines and forming a plurality of plugs with a conductive layer to protrude from the spaces on the bit line contacts include: Forming the conductive layer on the front surface of the semiconductor substrate to fill the space; Planarizing the conductive layer to expose a surface of the cap insulating layer to form a plurality of plugs including the remaining conductive layer; And forming a conductive pad on an upper portion of the plug formed in the space above the bit line contact portion. The method of claim 1, wherein the filling of the spaces between the word lines and forming a plurality of plugs with a conductive layer to protrude from the spaces on the bit line contacts include: Forming the conductive layer on the front surface of the semiconductor substrate by a predetermined thickness so as to completely fill the space; Planarizing the conductive layer to remain on the cap insulation layer by the protrusion height; And etching the upper portion of the bit line contact portion with an etch stop mask to etch back using the cap insulation layer as an etch stop layer on the planarized surface of the conductive layer. Way.