CN106158599A - It is etched back the method for hard mask and the manufacture method of interconnection layer structure - Google Patents
It is etched back the method for hard mask and the manufacture method of interconnection layer structure Download PDFInfo
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- CN106158599A CN106158599A CN201510173521.1A CN201510173521A CN106158599A CN 106158599 A CN106158599 A CN 106158599A CN 201510173521 A CN201510173521 A CN 201510173521A CN 106158599 A CN106158599 A CN 106158599A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
This application provides a kind of method being etched back hard mask and the manufacture method of interconnection layer structure.Being etched back in the method for hard mask, hard mask is arranged on dielectric layer, and hard mask has the first through hole, and dielectric layer has second through hole corresponding with the first through hole, and the method comprises the following steps: form photoresist layer in the second through hole；Outwards being etched back hard mask along the first through-hole wall, to form third through-hole in hard mask, the cross-sectional area of third through-hole is more than the cross-sectional area of the first through hole；Remove photoresist layer.The method first forms photoresist layer in the through hole of the dielectric layer being positioned at below hard mask; the hardest mask is performed etching; utilize the photoresist layer formed that through hole is protected, thus avoid etching liquid and the device bottom hard mask is caused damage, improve the stability of chip.
Description
Technical field
The application relates to the manufacture technology field of semiconductor device, particularly relates to a kind of method being etched back hard mask and interconnection layer structure
Manufacture method.
Background technology
During the processing technology of integrated circuit, it usually needs hard mask is etched back, to expand the window of later processing operation
Mouthful.Such as, in the manufacturing process of trench isolations, after forming shallow trench by photoetching and etching technics in substrate, it is right to need
Hard mask is etched back, and etches the dielectric layer below hard mask and substrate the most again, forms the shallow trench with round and smooth drift angle, from
And reduce the leakage current concentrated to groove drift angle and cause due to electronics.The most such as, in the manufacturing process of interconnection layer, the most first
Low dielectric material is formed the hard mask with through hole, and forms groove along the low dielectric material of this via etch；Then, to firmly
Mask carries out being etched back to expand the width of through hole, thus expands follow-up process window in groove during deposition metal level, improves
Adhesion between metal level and groove.
The making of existing interconnection layer structure generally includes following steps: first, has the first mutual of the first metallic region 25 ' in inside
The even upper hard mask 40 ' forming second interconnection layer 30 ' with primary through hole 35 ' and there is the first through hole 41 ' of layer 20 ', wherein first
Interconnection layer 20 ' is arranged in semiconductor device district (include dielectric layer 10 ' and contact metal layer 11 '), and the first interconnection layer 20 ' includes the
One etching barrier layer 21 ', the first dielectric layer 23 ', the second interconnection layer 30 ' includes the second etching barrier layer 31 ', the second dielectric layer 33 ',
And first through hole 41 ' corresponding with primary through hole 35 ', be also formed with adhesion layer 50 ' between the second interconnection layer 30 ' and hard mask 40 ',
Form basal body structure as shown in Figure 1.Then, the second dielectric layer 33 ' and second etch stopper of the first through hole 41 ' lower section are etched
Layer 31 ', is formed such that the second through hole 37 ' that the first metallic region 25 ' upper surface is exposed, concurrently forms matrix knot as shown in Figure 2
Structure.As it is shown on figure 3, it follows that be outwards etched back hard mask 40 ' along the first through-hole wall, form third through-hole 43 ', concurrently form
Basal body structure as shown in Figure 3.Finally, to the second through hole 37 ' middle deposition metal material, form the second metallic region 39 ', then go
Except hard mask 40 ' and adhesion layer 50 ', form basal body structure as shown in Figure 4.
But, during being etched back hard mask, the device below hard mask can be damaged by etching liquid.Such as, in above-mentioned interconnection
In the manufacturing process of Rotating fields, generally with EKC and H2O2As etching liquid, hard mask 40 ' is etched back, however EKC and
H2O2Reagent can erode part first metallic region 25 ' of the second through hole 37 ' lower section, causes the first technical area 25 ' to produce and loosens,
And then RC time delay can be caused, affect the stability of chip.The most such as, in the manufacturing process of trench isolations, it is etched back hard mask also
Substrate can be caused damage, and then affect the effect of trench isolations and the stability of chip.At present, still do not have for the problems referred to above
There is effective solution.
Summary of the invention
The application is intended to provide a kind of method being etched back hard mask and the manufacture method of interconnection layer structure, to reduce hard mask
The damage that device below hard mask is caused by etch back process.
On the one hand the application provides a kind of method being etched back hard mask.Wherein hard mask is arranged on dielectric layer, and on hard mask
Having the first through hole, have second through hole corresponding with described first through hole simultaneously on dielectric layer, the method includes: second
Through hole is formed photoresist layer；Hard mask outwards it is etched back along the first through-hole wall, to form third through-hole in hard mask, the 3rd
The cross-sectional area of through hole is more than the cross-sectional area of the first through hole；Remove photoresist layer.
Further, in the method for the hard mask of above-mentioned eat-back, the step forming photoresist layer includes: is formed and covers at hard mask
Surface on, and be filled in the photoresist preparation layers in the first through hole and the second through hole；Etching is removed in photoresist preparation layers and is positioned at
On the surface of hard mask, and it is positioned at the part in the first through hole, is formed and be positioned at the photoresist layer in the second through hole.
Further, in the method for the hard mask of above-mentioned eat-back, the step being etched back hard mask uses the mode of wet etching, preferably
Ground, wet etching is carried out at a temperature of 25～45 DEG C.
Further, in the method for the hard mask of above-mentioned eat-back, the step of wet etching uses H2O2Solution or SC1 solution
Described hard mask is performed etching.
Further, in the method for the hard mask of above-mentioned eat-back, above-mentioned hard mask includes TiN.
The application further aspect is that the manufacture method providing a kind of interconnection layer structure.This manufacture method includes: formed internal
There is the first interconnection layer of the first metallic region；First interconnection layer is formed and there is the second interconnection layer of the second through hole and have the
The hard mask of one through hole, wherein the first through hole and the second through hole are corresponding；The method being etched back hard mask using the application above-mentioned is returned
Lose hard mask；The second metallic region is formed in the second through hole.
Further, in the manufacture method of above-mentioned interconnection layer structure, form internal first interconnection layer with the first metallic region
Step include: semiconductor device district surface along away from the direction in semiconductor device district sequentially form the first etching barrier layer,
First dielectric layer, to form the first interconnection layer；It is sequentially etched the first dielectric layer and the first etching barrier layer, in the first interconnection layer
Form the first raceway groove；The first metallic region is formed in the first raceway groove.
Further, in the manufacture method of above-mentioned interconnection layer structure, the first interconnection layer is formed there is the second of the second through hole
Interconnection layer includes with the step of the hard mask with the first through hole: depend on along the direction away from the first interconnection layer at the first interconnection layer surfaces
Secondary formation the second etching barrier layer and the second dielectric layer, to form the second interconnection layer；Second interconnection layer is formed hard mask, and
Etch hard mask, hard mask is formed the first through hole；The second dielectric layer and the second etching barrier layer is etched downwards along the first through hole,
Second through hole exposed to be formed such that the first metallic region upper surface.
Further, in the manufacture method of above-mentioned interconnection layer structure, before forming the step of hard mask, at the second dielectric layer
Upper formation adhesion layer.
Further, in the manufacture method of above-mentioned interconnection layer structure, adhesion layer is SiO2。
The technical scheme of application the application, by forming photoresist layer, the most again edge in first the second through hole in being positioned at dielectric layer
The first through-hole wall being positioned in hard mask is outwards etched back hard mask so that the photoresist layer formed can be protected under the second through hole
The device of side, thus decrease the damage that the device below the second through hole is caused by etch back process, improve the stability of device.
Accompanying drawing explanation
The accompanying drawing of the part constituting the application is used for providing further understanding of the present application, the illustrative examples of the application and
Its explanation is used for explaining the application, is not intended that the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows in the manufacture method of existing interconnection layer structure, has shape on the first interconnection layer of the first metallic region in inside
The cross-sectional view of the matrix after becoming the second interconnection layer and there is the adhesion layer of the first through hole and hard mask；
Fig. 2 shows the second interconnection layer below the first through hole shown in etching Fig. 1, is formed such that the first metallic region upper surface is naked
The cross-sectional view of the matrix after the second through hole of dew；
Fig. 3 shows and is outwards etched back hard mask along the first through-hole wall shown in Fig. 2, after forming the hard mask with third through-hole
The cross-sectional view of matrix；
Fig. 4 shows and forms the second metallic region in the second through hole shown in Fig. 3, and removes the matrix after hard mask and adhesion layer
Cross-sectional view；
Fig. 5 shows the schematic flow sheet of the method being etched back hard mask that the application embodiment provided；
Fig. 6 shows the schematic flow sheet of the manufacture method of the interconnection layer structure that the application embodiment provided；
Fig. 7 shows in the manufacture method of the interconnection layer structure that the application embodiment provided, and is formed and internal has the first metal
The cross-sectional view of the matrix after first interconnection layer in region；
Fig. 8 shows to be formed on the first interconnection layer shown in Fig. 7 have the second interconnection layer of the second raceway groove and have the first through hole
Adhesion layer and hard mask after the cross-sectional view of matrix；
Fig. 9 shows and etches downwards the second interconnection layer along the first through hole shown in Fig. 8, forms second interconnection with the second through hole
The cross-sectional view of the matrix after Ceng；
Figure 10 shows that formation covers on the hard mask shown in Fig. 9, and is filled in the photoresist in the first through hole and the second through hole
The cross-sectional view of the matrix after preparation layers；
Figure 11 shows and is positioned on hard mask in photoresist preparation layers shown in etching removal Figure 10 and is positioned at the photoetching in the first through hole
Glue preparation layers, forms the cross-sectional view of the matrix after being positioned at the photoresist layer in the second through hole；
Figure 12 shows and is outwards etched back hard mask along the first through-hole wall shown in Figure 11, forms the section of the matrix after third through-hole
Structural representation；
Figure 13 shows the matrix after the photoresist layer used in the nmp solution etching removal the first metallic region shown in Figure 12
Cross-sectional view；And
Figure 14 shows the cross-sectional view of the matrix after forming the second metallic region in the second through hole shown in Figure 13.
Detailed description of the invention
Below in conjunction with the detailed description of the invention of the application, the technical scheme of the application is described in detail, but implements as follows
Example is only to understand the application, and can not limit the application, and the embodiment in the application and the feature in embodiment can be mutual
Combination, the multitude of different ways that the application can be defined by the claims and cover is implemented.
It should be noted that term used herein above merely to describe detailed description of the invention, and be not intended to restricted root according to this Shen
Illustrative embodiments please.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to
Including plural form, additionally, it should be understood that, when use belongs to " comprising " and/or " including " in this manual, its
Indicate existing characteristics, step, operation, device, assembly and/or combinations thereof.
For the ease of describing, space relative terms here can be used, as " ... on ", " ... top ", " ...
Upper surface ", " above " etc., be used for describing such as a device shown in the figure or feature and other devices or the space bit of feature
Put relation.It should be appreciated that space relative terms is intended to comprise using in addition to the orientation that device is described in the drawings
Or the different azimuth in operation.Such as, " above other devices or structure " if the device in accompanying drawing is squeezed, then it are described as
Or will be positioned as after the device of " on other devices or structure " " at other devices or below constructing " or " at other devices or
Under structure ".Thus, exemplary term " in ... top " can include " in ... top " and " in ... lower section " two kinds of orientation.
This device can also other different modes location (90-degree rotation or be in other orientation), and to space used herein above phase
Respective explanations is made in description.
From background technology, the device below hard mask can be caused damage by the etch back process of hard mask.Present inventor
Study for the problems referred to above, it is provided that a kind of method being etched back hard mask.In the method, hard mask is arranged on dielectric layer,
Having the first through hole on hard mask, dielectric layer has second through hole corresponding with the first through hole, and the method comprises the following steps:
Photoresist layer is formed in the second through hole；Hard mask outwards it is etched back along the first through-hole wall, to form third through-hole in hard mask,
The cross-sectional area of third through-hole is more than the cross-sectional area of the first through hole；Remove photoresist layer.The method is by being first positioned at dielectric layer
In the second through hole in form photoresist layer, be outwards etched back hard mask along the first through-hole wall of being positioned in hard mask the most again, make
The photoresist layer that be formed can protect the device below the second through hole, thus decrease etch back process to the second through hole below
The damage that device causes, improves the stability of device.
Fig. 5 shows the schematic flow sheet of the method being etched back hard mask that the application embodiment provided.Below in conjunction with Fig. 5
Further illustrate the provided herein method being etched back hard mask.
First, the second through hole forms photoresist layer.In a preferred embodiment, the second through hole forms photoresist
The step of layer includes: is initially formed and covers on hard mask, and is filled in the photoresist preparation layers in the first through hole and the second through hole；
Etching is positioned on hard mask in removing photoresist preparation layers the most again, and is positioned at the part in the first through hole, is formed and is positioned at second
Photoresist layer in through hole.
The method of above-mentioned deposition photoresist preparation layers includes but not limited to the technique such as spin coating, deposition；Above-mentioned etching photoresist preparation layers
Step include: use N-methyl 2-pyrrolidone photoresist preparation layers is carried out wet etching, wet etching can use infusion method
With rotary spray method.In a kind of preferred implementation that the application provides, etch above-mentioned photoresist by infusion method；At another
In preferred embodiment, use rotary spray method, use N-methyl 2-pyrrolidone solution temperature at 70 DEG C～80 DEG C, etch photoresist
Preparation layers 30～120 seconds.
After completing to be formed the step of photoresist in the second through hole, outwards it is etched back hard mask along the first through-hole wall, with at hard mask
Middle formation third through-hole, the cross-sectional area of third through-hole is more than the cross-sectional area of the first through hole.In this step, it is etched back hard mask
Step preferably employ the mode of wet etching, wherein the reagent of wet etching is preferably H2O2Solution or SC1 solution.More
Preferably, wet etching temperature is 25～45 DEG C, and etch period is 60～300 seconds.H is used in above-mentioned wet etching2O2
During solution, preferably this H2O2H in solution2O2With H2Volume ratio 1:4 of O～10.Use SC1 molten in above-mentioned wet etching
During liquid, preferably NH in this SC1 solution4OH、H2O2And H2The volume ratio of O is 1:1～4:50～200；Etching temperature is
25～45 DEG C；Etch period is 60～300 seconds.
Above-mentioned etch back process can use infusion method or rotary spray method.In a preferred embodiment, it is etched back by infusion method
The concrete steps of hard mask include: by H2O2Or SC1 solution is placed in etching groove, controls the temperature of cleaning reagent in etching groove and exist
25～45 DEG C, then the silicon chip comprising hard mask is placed in H2O2Or in SC1 solution, hard mask is performed etching, etching time
Between be 60～300 seconds.In another detailed description of the invention that the application provides, it is etched back the concrete of hard mask by rotary spray method
Step includes: by H2O2Or SC1 liquid sprays to comprise on the silicon chip treating hard mask, and made by low speed rotation (< 500rpm)
SC1 solution is uniformly distributed on the chip surface, under temperature is 25～50 DEG C of parts, performs etching hard mask, the time of etching
It it is 60～300 seconds.
Complete outwards to be etched back hard mask along the first through-hole wall, with in hard mask, form third through-hole step after, remove light
Photoresist layer.In the step removing photoresist layer, can use and include but not limited to that photoresist is carried out wet by N-methyl 2-pyrrolidone
Method etches, and then removes photoresist layer.Preferably, during etching removes photoresist, temperature is 70 DEG C～80 DEG C, etching
Time is 30～120 seconds.
Above-mentioned wet etching can use infusion method or rotary spray method.When removing photoresist layer by infusion method, a kind of preferred
Mode includes: be placed in etching groove by N-methyl 2-pyrrolidone, and in control etching groove, the temperature of cleaning reagent is at 70～80 DEG C, so
After comprise photoresist layer silicon chip be placed in N-methyl 2-pyrrolidone so that photoresist layer reacts with N-methyl 2-pyrrolidone,
Response time is 30～120 seconds.When removing photoresist layer by rotary spray method, a kind of preferably mode includes: by N-methyl
2-pyrrolidone solution spraying is on the silicon chip comprising photoresist layer, and makes N-methyl 2-pyrrolidone by low speed rotation (< 500rpm)
Solution is evenly distributed on silicon chip surface, under the conditions of temperature is 70～80 DEG C so that photoresist layer is sent out with N-methyl 2-pyrrolidone
Raw reaction, the response time is 30～120 seconds.
Meanwhile, present invention also provides the manufacture method of a kind of interconnection layer structure.As shown in Figure 6, this manufacture method includes: shape
Become internal first interconnection layer with the first metallic region；On the first interconnection layer formed have the second through hole the second interconnection layer and
Having the hard mask of the first through hole, wherein the first through hole and the second through hole are corresponding；What employing the application was above-mentioned is etched back hard mask
Method is etched back hard mask；The second metallic region is formed in the second through hole.
Above-mentioned manufacture method is by forming photoresist layer in first the second through hole in being positioned at dielectric layer, the most again along being positioned at hard mask
In the first through-hole wall be outwards etched back hard mask so that the photoresist layer formed can protect the first gold medal below the second through hole
Belong to region, thus decrease the damage that the first metallic region is caused by etch back process, improve the stability of interconnection layer structure.
Fig. 7 to Figure 14 shows in the manufacture method of the interconnection layer structure that the application embodiment provides, after each step
The cross-sectional view of the semiconductor device arrived.Below in conjunction with Fig. 7 to 14, further illustrate interconnection provided herein
The manufacture method of Rotating fields.
First, being initially formed inside and have the first interconnection layer 20 of the first metallic region 25, its structure is as shown in Figure 7.In the application
A kind of preferred implementation in, the first interconnection layer 20 includes the first etching barrier layer 21 and the first dielectric layer 23, it is preferable that
First etching barrier layer 21 material includes but not limited to Si3N4；First dielectric layer 23 is Jie of low-k (dielectric constant ＜ 3)
Electric material, includes but not limited to SiCOH, porous Si.The use of dielectric materials can under conditions of not reducing wiring density,
Effectively reduce interconnection capacitance value, make the quickening of chip operation speed, lower power consumption.Preferably, form inside and there is the first metal
The step of first interconnection layer 20 in region 25 includes: sequentially form the first etching resistance from lower to upper on the surface in semiconductor device district
Barrier the 21, first dielectric layer 23；First dielectric layer 23 and the first etching barrier layer 21 are performed etching, forms the first raceway groove；
The first metallic region 25 is formed in the first raceway groove.In a preferred embodiment, as it is shown in fig. 7, semiconductor device district wraps
Include dielectric layer 10 and contact metal layer 11.
In a kind of preferred implementation of the application, the step etching the first dielectric layer 23 and the first etching barrier layer 21 can be adopted
Use dry etch process.In a kind of preferred implementation of the application, using plasma etching technics is to the first dielectric layer 23 He
First etching barrier layer 21 performs etching, and processing step includes: put on the carrier of reactor by chip to be etched, and regulation is poly-
Burnt ring and the distance of substrate；Opening heating power supply, wherein sputtering power is 400～1200 watts so that oxygen and helium occur electricity
From forming plasma；Plasma is by part Si3N4Bombard out with SiCOH.Wherein, etching temperature is 25～50 DEG C,
Etch period is 30～90 seconds.
In a kind of preferred implementation of the application, the step forming the first metallic region 25 in the first raceway groove includes: first
In raceway groove, deposition metal, then planarizes metal.Preferably, above-mentioned metal includes but not limited to Cu or Al etc..Heavy
Long-pending technique includes but not limited to physical vapour deposition (PVD), chemical gaseous phase deposition, plating, chemical plating, and flatening process includes but do not limits
In chemically mechanical polishing.Above-mentioned technique is state of the art, does not repeats them here.
After completing to form the internal step of the first interconnection layer 20 with the first metallic region 25, shape on the first interconnection layer 20
Become to have the second interconnection layer 30 of the second through hole 37 and there is the hard mask 40 of the first through hole 41, wherein the first through hole 41 and the
Two through holes 37 match with the first metallic region 25 position.In a preferred embodiment, in order to preferably fill second
Metal, the second through hole 37 formed in the second interconnection layer 30 is generally proximal to the cross-sectional area of the first metallic region 25 part with
The cross-sectional area of the first metallic region 25 is consistent, and the cross-sectional area away from the first metallic region 25 part is more than the first metal area
The cross-sectional area in territory 25.
Preparation has the second interconnection layer 30 of the second through hole 37 of said structure and the step of the hard mask 40 with the first through hole 41
Suddenly include: sequentially form second etching barrier layer the 31, second dielectric layer 33 on the first interconnection layer 20 surface from lower to upper and have
The hard mask 40 of primary through hole, etches downwards the second dielectric layer 33 along primary through hole, forms cross-sectional area and the first metallic region 25
The second raceway groove 35 of being consistent of cross-sectional area, and be etched back hard mask 40 so that primary via area becomes big, forms the first through hole 41,
And then form structure as shown in Figure 8；Table the second interconnection layer 30 to the first metallic region 25 is etched downwards from the first through hole 41
Face is exposed, and the cross-sectional area of the cross-sectional area and the first metallic region 25 that are formed close to the first metallic region 25 part is consistent, and
Away from the cross-sectional area of the first metallic region 25 part more than second through hole 37 of cross-sectional area of the first metallic region 25, and then
Form basal body structure as shown in Figure 9.
In order to improve the bonding force between above-mentioned hard mask 40 and the second interconnection layer 30, in a preferred embodiment, upper
State and between hard mask 40 and the second interconnection layer 30, form adhesion layer 50 (as shown in Figure 8 and Figure 9).This adhesion layer includes but does not limits
In using SiO2.There is on this adhesion layer 50 the adhesion layer through hole matched with the first through hole 41 in hard mask 40.Now originally
In the hard masking method of eat-back that application is provided, formed in the step of photoresist layer 60 in the second through hole, photoresist layer 60
Upper surface and the upper surface flush of second dielectric layer 33, or the upper surface higher than second dielectric layer 33, equal to less than this adhesion layer
The upper surface of 50.
Those skilled in the art it should be explicitly made clear at this point, forms above-mentioned second interconnection layer 30 with the second through hole 37 and has the
The method of the hard mask 40 of one through hole 41 has a lot, is not limited in above-mentioned preferred implementation.Another kind in the application
In preferred implementation, form second interconnection layer 30 with the second through hole 37 and the hard mask 40 with the first through hole 41
Step includes: sequentially form second etching barrier layer the 31, second dielectric layer 33 and tool from lower to upper on the first interconnection layer 20 surface
There is the hard mask 40 of the first through hole 41；The second dielectric layer 33 and the second etching barrier layer 31 is etched downwards along the first through hole 41,
It is formed such that the second through hole 37 that the first metallic region 25 upper surface is exposed.It should be noted that in view of those skilled in the art
This preferred implementation can be realized according to the teachings of the present invention completely, the most do not provide the structure of this preferred implementation
Figure is to saving space.
In above two preferred implementation, the structure of the second interconnection layer 30 and hard mask 40 can be carried out according to prior art
Arrange.Preferably, the second interconnection layer 30 includes the second etching barrier layer 31 and the second dielectric layer 33.Preferably, the second etching
Barrier layer 31 material includes but not limited to Si3N4；Second dielectric layer 33 is the dielectric material of low-k (dielectric constant ＜ 3),
Include but not limited to SiCOH, porous Si.Hard mask 40 includes but not limited to TiN, Si3N4Or one or more in SiON.
The technique forming above-mentioned second interconnection layer 30 and hard mask 40 includes but not limited to spin coating proceeding, CVD technique, and above-mentioned technique is
The state of the art, does not repeats them here.
The step etching above-mentioned hard mask 40 and the second interconnection layer 30 can use dry etch process.More preferably use plasma
Etching technics, use plasma etching industrial process conditions include: sputtering power is 400～1200 watts, etching temperature be 25～
50 DEG C, etch period is 30～120 seconds.
Complete to be formed on the first interconnection layer 20 and there is the second interconnection layer 30 of the second through hole 37 and there is the hard of the first through hole 41
After the step of mask 40, the second through hole 37 forms photoresist layer 60.In a kind of preferred implementation of the application, shape
The step becoming photoresist layer 60 includes: is formed and covers on hard mask 40, and is filled in the first through hole 41 and the second through hole 37
In photoresist preparation layers 60 ', and then form structure as described in Figure 10；Etching is removed in photoresist preparation layers 60 ' and is positioned at
On hard mask 40, and it is positioned at the photoresist preparation layers 60 ' in the first through hole 41, is formed and be positioned at the photoetching in the second through hole 37
Glue-line 60, and then form basal body structure as shown in figure 11.In order to increase the technique that subsequent deposition forms the second metallic region 70
Window, in a preferred embodiment, after forming the step of above-mentioned photoresist layer 60, along the first through hole 41 inwall to
The hard mask of outer eat-back 40, forms the cross-sectional area third through-hole 43 more than the cross-sectional area of the first through hole 41, and then is formed such as figure
Basal body structure shown in 12.
The method forming above-mentioned photoresist preparation layers 60 ' includes but not limited to the technique such as spin coating, deposition；Above-mentioned etching photoresist is pre-
The step of standby layer 60 ' including: using N-methyl 2-pyrrolidone that photoresist preparation layers 60 ' is carried out wet etching, wet etching can
To use infusion method and rotary spray method.In a kind of preferred implementation that the application provides, etched by rotary spray method
Stating photoresist preparation layers 60 ', preferably etch technological condition is: by the temperature of N-methyl 2-pyrrolidone solution at 70 DEG C～80 DEG C,
The time of etching is 30～120 seconds.
The step being etched back above-mentioned hard mask 40 can be in the way of using wet etching, and wherein the reagent of wet etching is preferably H2O2
Solution or SC1 solution.Preferably, wet etching temperature is 25～45 DEG C, and etch period is 60～300 seconds.Above-mentioned wet
Method etching uses H2O2During solution, preferably NH in this SC1 solution4OH、H2O2And H2The volume ratio of O is 1:1～4:
50～200；Etching temperature is 25～45 DEG C；Etch period is 60～300 seconds.In above-mentioned steps, owing to being positioned at hard mask
The second through hole 37 below 40 is formed photoresist layer 60, therefore when performing etching hard mask 40, photoresist layer 60 energy
Enough the second through hole 37 is protected, thus avoid etching liquid and the device bottom hard mask 40 is caused damage, improve core
The stability of sheet.
Being etched back in the step of above-mentioned hard mask 40, etch back process can use infusion method or rotary spray method.It is preferable to carry out in one
In mode, the concrete steps being etched back hard mask 40 by infusion method are included: by H2O2Or SC1 solution is placed in etching groove, control
In etching groove processed, the temperature of cleaning reagent is at 25～45 DEG C, and the silicon chip then comprising hard mask 40 is placed in H2O2Or in SC1 solution,
Performing etching hard mask 40, the time of etching is 60～300 seconds.In another detailed description of the invention, by rotary spray method
The concrete steps being etched back hard mask 40 include: H2O2Or SC1 liquid sprays to comprise on the silicon chip of hard mask 40 to be etched, and lead to
Crossing low speed rotation (300～500rpm) makes SC1 solution be uniformly distributed on the chip surface, under temperature is 25～50 DEG C of parts,
Performing etching hard mask, the time of etching is 60～300 seconds.
After completing to be formed the step of above-mentioned photoresist layer 60 in the second through hole 37, nmp solution etching is used to remove the first gold medal
Belong to the photoresist layer 60 on region, and then form basal body structure as shown in fig. 13 that.Etching is excellent during removing above-mentioned photoresist
Choosing uses infusion method or rotary spray method.When removing photoresist layer by infusion method, a kind of preferably process conditions are: N-methyl
The temperature of 2-pyrrolidone solution is 70 DEG C～80 DEG C, and the time of etching is 30～120 seconds.
After completing to use nmp solution to etch the step of the photoresist layer 60 removed in the first metallic region, at the second through hole 37
Middle formation the second metallic region 39, and then form basal body structure as shown in figure 14.In the optional embodiment of one, formed
The step of above-mentioned second metallic region 39 includes: deposit metal preparation layers in the second through hole 37 and on the surface of hard mask 40；
And this metal preparation layers is planarized, to remove the metal preparation layers on hard mask 40 and hard mask 40 surface, shape
Become above-mentioned second metallic region 39, and then form basal body structure as shown in Figure 10.
Preferably, the material of above-mentioned metal preparation layers includes but not limited to use Cu, Al, the technique of deposition metal preparation layers to include
But be not limited to physical vapour deposition (PVD), chemical gaseous phase deposition, plating, chemical plating, the technique of planarization material preparation layers include but not
It is limited to chemically mechanical polishing.Above-mentioned technique is the state of the art, does not repeats them here.
As can be seen from the above embodiments, the application the above embodiments achieve following technique effect: the application is by through hole
With the photoresist layer of the lower surface defined in groove less than hard mask, harder mask is performed etching, thus avoid quarter
Hard mask bottom device is caused damage by erosion process.Use the provided herein method etching hard mask to prepare to include
The chip of interconnection layer structure, in obtained chip, the loss of metal level is reduced, and the partial properties of IC chip obtains
Improve.
These are only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art,
The application can have various modifications and variations.All within spirit herein and principle, any amendment of being made, equivalent,
Improve, within should be included in the protection domain of the application.
Claims (10)
1. the method being etched back hard mask, described hard mask is arranged on dielectric layer, and described hard mask has the first through hole, institute
State dielectric layer and there is second through hole corresponding with described first through hole, it is characterised in that said method comprising the steps of:
Photoresist layer is formed in described second through hole；
Described hard mask outwards it is etched back along described first through-hole wall, to form third through-hole in described hard mask, described
The cross-sectional area of third through-hole is more than the cross-sectional area of described first through hole；
Remove described photoresist layer.
Method the most according to claim 1, it is characterised in that the step forming described photoresist layer includes:
Formed and cover on the surface of described hard mask, and the photoresist being filled in described first through hole and the second through hole is pre-
Standby layer；
Etching is removed in described photoresist preparation layers and is positioned on the surface of described hard mask, and is positioned in described first through hole
Part, formed be positioned at the photoresist layer in described second through hole.
Method the most according to claim 1, it is characterised in that the step of the hard mask of described eat-back uses the mode of wet etching,
Preferably, described wet etching is carried out at a temperature of 25～45 DEG C.
Method the most according to claim 3, it is characterised in that use H in the step of described wet etching2O2Solution or SC1
Described hard mask is performed etching by solution.
Method the most according to claim 1, it is characterised in that described hard mask is TiN.
6. the manufacture method of an interconnection layer structure, it is characterised in that described manufacture method includes:
Form internal first interconnection layer with the first metallic region；
Described first interconnection layer is formed and there is the second interconnection layer of the second through hole and there is the hard mask of the first through hole, its
Described in the first through hole corresponding with described second through hole；
The method being etched back hard mask according to any one of claim 1 to 5 is used to be etched back described hard mask；
The second metallic region is formed in described second through hole.
Manufacture method the most according to claim 6, it is characterised in that form inside and there is the described of described first metallic region
The step of the first interconnection layer includes:
Semiconductor device district surface along away from the direction in described semiconductor device district sequentially form the first etching barrier layer and
First dielectric layer, to form described first interconnection layer；
It is sequentially etched described first dielectric layer and described first etching barrier layer, in described first interconnection layer, forms the first ditch
Road；
Described first metallic region is formed in described first raceway groove.
Manufacture method the most according to claim 6, it is characterised in that formed on described first interconnection layer and there is the second through hole
The second interconnection layer and the step of the hard mask with the first through hole include:
The second etching barrier layer and the is sequentially formed along away from the direction of described first interconnection layer at described first interconnection layer surfaces
Two dielectric layers, to form described second interconnection layer；
Described second interconnection layer is formed hard mask, and etches described hard mask, described hard mask is formed described
One through hole；
Described second dielectric layer and the second etching barrier layer is etched downwards, to be formed such that the first metal along described first through hole
Described second through hole that region upper surface is exposed.
Manufacture method the most according to claim 8, it is characterised in that before forming the step of described hard mask, described
Adhesion layer is formed on second dielectric layer.
Manufacture method the most according to claim 9, it is characterised in that described adhesion layer is SiO2。
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417529A (en) * | 2018-02-09 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | A kind of lithographic method of contact hole |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202228A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Method of protecting plow groove bottom in deep plow groove technics |
| US20120065332A1 (en) * | 2006-07-27 | 2012-03-15 | Techno Polymer Co.,Ltd. | Thermoplastic polymer composition and molded product |
| CN104425356A (en) * | 2013-08-27 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
-
2015
- 2015-04-13 CN CN201510173521.1A patent/CN106158599A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120065332A1 (en) * | 2006-07-27 | 2012-03-15 | Techno Polymer Co.,Ltd. | Thermoplastic polymer composition and molded product |
| CN101202228A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Method of protecting plow groove bottom in deep plow groove technics |
| CN104425356A (en) * | 2013-08-27 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417529A (en) * | 2018-02-09 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | A kind of lithographic method of contact hole |
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