CN104124197B - A kind of preparation method of semiconductor devices - Google Patents

A kind of preparation method of semiconductor devices Download PDF

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Publication number
CN104124197B
CN104124197B CN201310145232.1A CN201310145232A CN104124197B CN 104124197 B CN104124197 B CN 104124197B CN 201310145232 A CN201310145232 A CN 201310145232A CN 104124197 B CN104124197 B CN 104124197B
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layer
handled
plasma
interlayer dielectric
method described
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CN104124197A (en
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周鸣
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Abstract

The present invention relates to a kind of preparation method of semiconductor devices, methods described includes：Semiconductor substrate is provided；Metal interconnection structure is formed on the semiconductor substrate；The surface of metal material and interlayer dielectric layer in the metal interconnection structure is handled, following sub-step is the treating method comprises：（a）From NH3Plasma is handled；（b）From SiH4Plasma is handled；（c）Handled from tetramethylsilane plasma.It is when preparing metal interconnection structure in the present invention, filling metallic copper is simultaneously planarized, then the surface of the metallic copper and ultra low-K material is handled, the space of the ultra low-K material layer can be eliminated by the processing, the surface bigger than ultra low-K material layer hardness is formed, and for the processing of copper surface, then makes the copper surface more smooth, its roughness is reduced, to eliminate the seam between metallic copper and coating on metallic copper（cap layer seam）, improve the VBD performances of device.

Description

A kind of preparation method of semiconductor devices
Technical field
The present invention relates to field of semiconductor manufacture, in particular it relates to a kind of preparation method of semiconductor devices.
Background technology
The development of semiconductor integrated circuit technology proposes new demand to interconnection technique, interconnection integration technology in the recent period and A series of challenge of technologies and physical limit will be faced in long term development.With the continuous contraction of dimensions of semiconductor devices, interconnection Structure also becomes more and more narrow, so as to result in higher and higher interconnection resistance.Copper has turned into by its excellent electric conductivity One of solution of interconnection integration technology in technical field of integrated circuits.
In copper wiring technique, because the space between metal connecting line is being gradually reduced, isolating metal line thus be accordingly used in Between intermediate insulating layer（IMD）Also thin down, can so cause may occur unfavorable phase between metal connecting line Interaction or crosstalk.It has been found that reducing the dielectric constant of the intermediate insulating layer for isolating metal connecting line layer（k）, Ke Yiyou This crosstalk of effect ground reduction.Another benefit that low k-value intermediate insulating layer is brought is can effectively to reduce the resistance electricity of interconnection Hold（RC）Delay.Therefore, ultralow-k material film has been applied to be used as isolating metal copper in Cu interconnection processes more and more widely now Intermediate insulating layer.
In order to drop low k-value, very widely used today is porous material.Porous material outstanding feature the most is to be easy to absorb And moisture is kept, and air is the medium (k=1.0) for the most low k-value being currently available, this namely porous material k value is relatively low The reason for.The k values of porous material can reach about 2.3 to 2.9.However, porous can cause the mechanical strength of material relatively low, because The problem of this brings new for the manufacture of integrated circuit, that is, cause the breakdown voltage of semiconductor devices（Breakdown Voltage, VBD）Degradation.
In the preparation process of the interconnection of metallic copper described in prior art, after trench formation toward filling gold in the groove Belong to copper, then perform planarisation step, after planarisation steps, the surface roughness of the metallic copper is very big, and metal Copper, copper ion stay in the low K, in ultralow K layer of dielectric material and low K, the space of the presence of ultralow K dielectric materials layer surface （As shown in Figure 2）That causes that the VBD performances of device become is worse.
In order to remove the metallic copper and copper ion that low K, ultralow K dielectric materials layer surface are present, generally using ammonia plasma Body is handled the metallic copper and low K, the surface of ultralow K layer of dielectric material, in the low K, ultralow K layer of dielectric material Surface is formed with film, but after the processing, the VBD performances of device are further reduced.
Therefore, in metal copper interconnection structure, time delay, resistance electricity are solved after low-K material well although introducing Hold（RC）The problems such as delay, but caused after planarization because low-K material characteristic in itself and copper surface are coarse Device VBD performances further deteriorate, and can't solve the problem well in the prior art, and the solution of the problem is mutual as metal The problem of linking structure urgent need to resolve, there is material impact for the raising of device performance.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in embodiment part One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
The present invention in order to overcome the problem of presently, there are there is provided a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided；
Metal interconnection structure is formed on the semiconductor substrate；
The surface of metal material and interlayer dielectric layer in the metal interconnection structure is handled, the processing method bag Include following sub-step：
（a）From NH3Plasma is handled；
（b）From SiH4Plasma is handled；
（c）Handled from tetramethylsilane plasma.
Preferably, the sub-step（b）In selecting SiH4Progress one, which is included, after plasma is handled selects Ar The step of corona treatment.
Preferably, the sub-step（c）In progressive one included after being handled from tetramethylsilane plasma The step of from Ar corona treatments.
Preferably, the sub-step（b）Middle SiH4The power of corona treatment is 50-1000w, pressure 0.5- 10torr, gas flow 100-1000sccm.
Preferably, the sub-step（c）In tetramethylsilane plasma power be 50-1000w, pressure 0.5- 10torr, gas flow 100-1000sccm.
Preferably, the power of the Ar corona treatments is 200-1000w, pressure is 0.5-5torr, gas flow For 500-1000sccm.
Preferably, the metal material is metallic copper.
Preferably, the interlayer dielectric layer is porous ultra low-K material.
Preferably, the method for forming metal interconnection structure on the semiconductor substrate is：
Etch stop layer, interlayer dielectric layer and hard mask stack are formed on the semiconductor substrate；
The etch stop layer, the interlayer dielectric layer and the mask stack are patterned, to form groove；
The groove is filled from metal material；
Planarisation step is performed to the interlayer dielectric layer.
Preferably, the etch stop layer is the silicon carbide layer of N doping.
Preferably, the hard mask stack includes NCC rock layers and the teos layer stacked gradually.
In the present invention in order to improve device VBD performances, the stability of device is improved, when preparing metal interconnection structure, Filling metallic copper is simultaneously planarized, and then the surface of the metallic copper and ultra low-K material is handled, so that the ultralow K The surface property of material layer is improved, and the space of the ultra low-K material layer can be eliminated in particular by the processing, is formed than ultralow The big surface of K material layer hardness, and for the processing of copper surface, then make the copper surface more smooth, reduce it Roughness, to eliminate the seam between metallic copper and coating on metallic copper（cap layer seam）, improve device VBD performances.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair Bright embodiment and its description, for explaining the device and principle of the present invention.In the accompanying drawings,
Fig. 1 a-d are the diagrammatic cross-section of semiconductor devices preparation process described in the embodiment of the invention；
Fig. 2 is the diagrammatic cross-section of semiconductor devices preparation process described in prior art；
The process chart of the semiconductor devices is prepared in Fig. 3 embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So And, it is obvious to the skilled person that the present invention can be able to without one or more of these details Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half The preparation method of conductor device.Obviously, what execution of the invention was not limited to that the technical staff of semiconductor applications is familiar with is special Details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have it His embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative Intention includes plural form.Additionally, it should be understood that, when in this manual use term "comprising" and/or " comprising " When, it indicates there is the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or many Other individual features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and these exemplary are implemented The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated Degree, and make identical element is presented with like reference characters, thus description of them will be omitted.
Below, reference picture 1a-d and Fig. 3 is carried out in detail to the preparation method of the semiconductor devices proposed by the present invention Explain.
There is provided Semiconductor substrate as shown in Figure 1a（Not shown in figure）, over the substrate formed etch stop layer 101, Ultra low-K material layer 102 and mask stack.
Specifically, the Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator （SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-SiGeOI）, germanium on insulator SiClx （SiGeOI）And germanium on insulator（GeOI）Deng.
Wherein, the etch stop layer 101 is to protect underlying substrate and active device, preferably, Etch stop layer 101 can be the silicon carbide layer NDC of N doping in the embodiment of the present invention（Nitrogen dopped Silicon Carbite）Or SiN layer, wherein, the silicon carbide layer NDC（Nitrogen dopped Silicon Carbite）Or the deposition process of SiN layer can select chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)（PVD）Method or Ald（ALD）Outside low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selection of the formation such as method One kind in epitaxial growth (SEG), as further preferably, the etch stop layer 101 is the silicon carbide layer NDC of N doping, Its thickness is 20-500 angstroms, passes through physical vapour deposition (PVD)（PVD）Method is formed, but the thickness and forming method be not according to limitation In the example.
Preferably, in the embodiment of the present invention, in order to form metal interconnection structure, in the etching resistance Can also be comprising the first interlayer layer of dielectric material and positioned at the first inter-level dielectric between the lower section of barrier 101 and Semiconductor substrate The first etch stop layer below material layer, wherein layer of dielectric material between the first layer (interlayer dielectric, ILD), as the layer insulation between multi-layer metal wiring in integrated antenna package, it can use poly- from Advanced Packaging in the present invention Compound ILD materials, the material such as polyimides (PI), polybenzoxazole (PBO) and benzocyclobutene (BCB), but not office It is limited to above-mentioned example.Contact hole is formed in interlevel dielectric material layer, specific forming method is the etching inter-level dielectric material The bed of material, forms raceway groove and is subsequently filled conductive material to form contact plug, for the electrical connection in subsequent process.Preferably, The the first interlayer layer of dielectric material formed between the substrate and the first interlayer layer of dielectric material is hard mask layer, to protect Active device in the substrate and substrate is not damaged by, and said structure is to show in figure.
It should be noted that being not limited solely to cited active device in the lower section of the etch stop layer 101, also Other active devices can be included.
Ultra low-K material layer 102 is formed on the etch stop layer 101, in the present invention preferably porous ultra low-K material layer （Porosity low K）As interlayer dielectric layer, the porous low-k materials have low-loss and Low dark curient in terms of electrical property Stream.Specifically, the porous low k material includes organic polymer material, and silica, the amorphous carbon nitrogen film of fluorination etc. are inorganic Material, the porous low k material such as HSQ, MSQ, and nanometer low-k materials, in the present invention, the porous low-k materials（Porosity low K）Replace silica as inter-level dielectric to reduce parasitic capacitance.
The preparation method of the porous low k material has following two：One kind is plasma chemical vapor deposition （CVD）, another is whirl coating（Spin-On Deposition, SOD）.Preferred spin coated (SOD) in the present invention Method, nano-porous film prepared by spin coated (SOD) method has stoichiometric proportion easy to control, structure-controllable, refractive index Adjustable, porosity is high, dielectric constant is small, stability is good, thermal conductivity is low, laser damage threshold is high, technological temperature is low, film forming area Greatly, the advantages of equipment is simple, and with high pressure, the clearance filling capability become reconciled with the adhesiveness that silicon has had, with semiconductor The compatibility of ic core blade technolgy is preferable.
As it is further preferably, can also be further to the porous low-K material after the porous low-k materials are formed Material carries out appropriate corona treatment, and the corona treatment can not only play a part of cleaning, and can be in institute The surface for stating material produces many dangling bonds and improves its chemism, and plasma surface treatment can make the low of preparation The open pore closure on K thin film surface, reduces water imbibition, prevents copper scattering and extraneous pollution.
Then mask stack is formed on the porous low-k materials, the mask stack is hard mask stack, including successively The NCC rock layers of deposition（Black diamond, BD）103 and tetraethyl orthosilicate（TEOS）Layer 104.
Wherein described carbonado layer 103（Black diamond, BD）Dielectric constant be 2.7-3.0 between, it is described black Diamond layer 103（Black diamond, BD）Can be formed by the method for vapour deposition, for example physical vapour deposition (PVD) or Or CVD method etc. is formed, methods described is merely illustrative, and its forming method and dielectric constant do not limit to In the scope.
The tetraethyl orthosilicate（TEOS）Layer 104 can select chemical vapor deposition（CVD）Method, physical vapour deposition (PVD) （PVD）Method or ald（ALD）The low-pressure chemical vapor depositions (LPCVD) of the formation such as method, laser ablation deposition (LAD) with And one kind in selective epitaxy growth (SEG).Preferably, the NCC rock layers（Black diamond, BD）103 and Tetraethyl orthosilicate（TEOS）Layer 104 is of uniform thickness.
The photoresist layer of patterning is formed on the oxide skin(coating) 106, then using the photoresist layer as mask etch The oxide skin(coating) 106 forms groove, the critical size of the groove is 1-20nm, the ditch to the etch stop layer 101 The critical size of groove is not limited to the number range, preferably, in the embodiment of the present invention, the groove It can also be carried out in two steps, by dry etching to the etch stop layer 101, then open the etch stop layer in etching 101, to expose the metal closures being located under etch stop layer 101, metal interconnection structure is formed in follow-up technique.
In the embodiment of the present invention, using the photoresist layer being patterned as mask, CF is being passed through4With CHF3Etching condition under, the hard mask layer is performed etching, until exposing ultra low-K material layer 102, forms graphical Hard mask layer, the etching pressure in this step：50-150mTorr；Power：300-800W；Time：5-15s；Wherein gas Body flow：CF4, 10-30sccm；CHF3, 10-30sccm.
Then using the hard mask layer being patterned as mask, it is passed through CF4And CHF3Ultra low-K material layer 102 is carved Erosion, its etching pressure：50-150mTorr；Power：300-800W；Time：5-15s；Gas flow：CF410-30sccm； CHF310-30sccm。
Finally it is being passed through CO2Or O2Or N2Under the conditions of, etch stop layer 101 is performed etching, groove, step master is formed If utilizing CO2Or O2Or N2The polymer in side wall deposition in a upper etch step is removed, so that the side wall in subsequent etching Keep vertical, pressure：15-35mTorr；Power is 50-200W；Time：5-15s；Gas flow：CO2Or O2Or N2, 100- 400sccm, finally obtains pattern as shown in Figure 1 b.
It should be noted that the shape of the groove can be etched as needed, the critical size and ditch of opening The number of groove is limited to a certain number range, in the embodiment of the present invention, as illustrated in figure 1 c, in the implementation In example, 3 grooves are formed, the wherein critical size of two grooves in the left side is 1-20 angstroms, the critical size of the right groove is 2-50 Angstrom, and ultralow K material of the height less than both sides of the ultra low-K material layer 102 ultra low-K materials layer between the groove of two, the left side The height of the bed of material 102, its forming method can be after the groove is formed, beyond the relatively low ultra low-K material layer 102 Place forms mask layer, and the relatively low ultra low-K material layer 102 is further etched, wherein the engraving method can be with From method commonly used in the art, or from the method for the above-mentioned etching ultra low-K material layer 102.It should be noted that at this The shape of groove described in invention, number, height etc. can be according to being designed the need for technique, and above-mentioned example is only Schematically.
Formed after the groove, a wet-cleaning or wet etch step can also be further included, to expand The critical size at the top of groove is stated, structure wide at the top and narrow at the bottom is formed, to easily facilitate the filling of subsequent conductive material.
When the critical size of device（critical dimension）, it is necessary to make when in going reduction to deep sub-micron range Reduce the RC delay times caused by dead resistance and parasitic capacitance with multiple layer metal connecting line construction, in the present invention described Barrier layer 101 is formed on substrate, preferably, being preferably formed as copper barrier layer in the present invention（copper barrier）, it is described Copper barrier layer（copper barrier）Forming method can select physical vaporous deposition and chemical vapor deposition to be main Method, specifically, can select evaporation, electron beam evaporation, plasma spray deposition and sputtering, in the present invention preferably grade from Daughter jet deposition and sputtering method form the copper barrier layer.The thickness of the copper barrier layer be not limited to a certain numerical value or In the range of person, it can be adjusted as needed.
Then the groove is filled from metallic copper 105, physical vapour deposition (PVD) can be passed through in the present invention（PVD）Method or Person's Cu electroplating（ECP）Method fill the groove, preferably, being preferred to use physical vapour deposition (PVD) in the present invention （PVD）Method fills the groove, elected Cu electroplating（ECP）Method when, copper coating thickness（um）=current density (ASF) × electroplating time (min) × electroplating efficiency × 0.0202；General electro-coppering current efficiency is 90-100%, in the present invention Need to fill the groove, therefore additive is needed to use in plating, the additive is flat dose（LEVELER）, accelerate Agent（ACCELERATORE）And inhibitor（SUPPRESSOR）.
Preferably, formed after the metallic copper is formed can also further comprising annealing the step of, annealing can be Carried out 2-4 hours at 80-160 DEG C, to promote with recrystallizing, long big crystal grain reduces resistance and improves stability, obtains such as figure Pattern shown in 1c.
Reference picture 1d, performs planarisation step to ultra low-K material layer 102.
Specifically, flattening method conventional in field of semiconductor manufacture can be used in one embodiment of this invention Realize the planarization on surface.The non-limiting examples of the flattening method include mechanical planarization method and chemically mechanical polishing is flat Smoothization method.Chemically mechanical polishing flattening method is more often used.
The NCC rock layers are removed in this step（Black diamond, BD）103 and tetraethyl orthosilicate（TEOS） Layer 104, to expose the ultra low-K material layer 102, and the metallic copper being embedded in the groove.
In the present invention in order to improve the VBD performances of device, the stability of device is improved, respectively to the ultra low-K material The surface of layer 102 and the metallic copper being embedded in the groove is handled, so that the surface property of ultra low-K material layer 102 Improve, the space of the ultra low-K material layer 102 can be eliminated in particular by the processing, form harder than ultra low-K material layer 102 The big surface of degree, and for the processing of copper surface, then make the copper surface more smooth, its roughness is reduced, with Eliminate the seam between metallic copper and coating on metallic copper（cap layer seam）, improve the VBD performances of device.
Specifically, in the embodiment of the present invention, first from NH3Corona treatment（NH3plasma treatment）, NH described in the step3What power, pressure and the time of plasma can be commonly used from prior art Parameter, it is not limited to a certain number range, preferably, the NH3The power of plasma is 50-500w, and pressure is 0.2-5 is held in the palm（torr）, flow is 50-1000sccm.In NH3After corona treatment, SiH is then carried out4Corona treatment （SiH4plasma treatment）, in this step from SiH4As reacting gas, the SiH4Work(in corona treatment Rate is 50-1000w, pressure 0.5-10torr, flow 100-1000sccm, is then performed after this step at Ar plasmas Reason, power is 200-1000w in Ar plasma treatment steps, and pressure is 0.5-5torr, and gas flow is 500- 1000sccm。
Pass through SiH during managing in this place4Expose in two steps of corona treatment and Ar corona treatments, groove Metallic copper surface formed a smooth film, its surface roughness reduction, its surface property is greatly improved, thereon It can be combined together well after forming coating, and in the absence of any gap, in this step, the NH3Plasma The parameter of processing can select scope commonly used in the art, but SiH4Two steps of corona treatment and Ar corona treatments Middle relevant parameter needs to select scope of the present invention.
After complete to the surface treatment of the metallic copper, the surface of ultra low-K material layer 102 be still it is porous, because This needs to be for further processing to the surface of ultra low-K material layer 102, in the embodiment of the present invention, from tetramethyl Base silane（Tetramethylsilane, TMS or 4MS）Plasma is handled, preferably, described in the step etc. Gas ions processing power be 50-1000w, pressure 0.5-10torr, flow 100-1000sccm, be then followed by Ar etc. from Daughter is handled, and power is 200-1000w in Ar plasma treatment steps, and pressure is 0.5-5torr, and gas flow is 500- 1000sccm。
Performing tetramethylsilane（Tetramethylsilane, TMS or 4MS）Corona treatment and Ar etc. from After daughter processing, the space on 102 surface of ultra low-K material layer is filled, and one layer of comparatively dense film is formed on its surface, Its hardness is bigger than ultra low-K material layer 102, and without space, improves the VBD performances of device and the stability of device.
Preferably, after the surface of the ultra low-K material layer 102 and metallic copper has been handled, can also be further Coating is being formed over the substrate.Wherein, the coating can be the silicon carbide layer NDC of N doping（Nitrogen dopped Silicon Carbite）Or SiN layer, wherein, the silicon carbide layer NDC（Nitrogen dopped Silicon Carbite）Or the deposition process of SiN layer can select chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)（PVD）Method or Ald（ALD）Outside low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selection of the formation such as method One kind in epitaxial growth (SEG), preferably, selecting physical vapour deposition (PVD) in the present invention（PVD）Method.
Planarisation step is finally can also carry out, specifically, semiconductor system can be used in one embodiment of this invention Flattening method conventional in field is made to realize the planarization on surface.The non-limiting examples of the flattening method include machinery Flattening method and chemically mechanical polishing flattening method.Chemically mechanical polishing flattening method is more often used.
In the present invention in order to improve device VBD performances, the stability of device is improved, when preparing metal interconnection structure, Filling metallic copper is simultaneously planarized, and then the surface of the metallic copper and ultra low-K material is handled, so that the ultralow K The surface property of material layer is improved, and the space of the ultra low-K material layer can be eliminated in particular by the processing, is formed than ultralow The big surface of K material layer hardness, and for the processing of copper surface, then make the copper surface more smooth, reduce it Roughness, to eliminate the seam between metallic copper and coating on metallic copper（cap layer seam）, improve device VBD performances.
Reference picture 3, illustrated therein is the manufacture method of semiconductor devices of the present invention, specifically comprises the following steps：
Step 201 provides Semiconductor substrate；
Step 202 forms etch stop layer, interlayer dielectric layer and hard mask stack on the semiconductor substrate；
Step 203 patterns the etch stop layer, the interlayer dielectric layer and the mask stack, to form groove；
Step 204 fills the groove from metal material；
Step 205 performs planarisation step to the interlayer dielectric layer；
The surface of the step 206 pair metal material and interlayer dielectric layer is handled, and the treating method comprises following Sub-step：
（a）From NH3Plasma is handled；
（b）From SiH4Plasma is handled, and then carries out corona treatment from Ar；
（c）Handled from tetramethylsilane plasma, then carry out corona treatment from Ar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art Member according to the teachings of the present invention it is understood that the invention is not limited in above-described embodiment, can also make more kinds of Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (11)

1. a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided；
Metal interconnection structure is formed on the semiconductor substrate；
The surface of metal material and interlayer dielectric layer in the metal interconnection structure is handled, to eliminate the inter-level dielectric The space of layer, forms the surface bigger than the interlayer dielectric layer hardness, the treating method comprises following sub-step：
(a) NH is selected3Plasma is handled；
(b) SiH is selected4Plasma is handled；
(c) handled from tetramethylsilane plasma.
2. according to the method described in claim 1, it is characterised in that selecting SiH in the sub-step (b)4Plasma is carried out Progressive one includes the step of selecting Ar corona treatments after processing.
3. according to the method described in claim 1, it is characterised in that in the sub-step (c) from tetramethylsilane etc. from Progressive one includes the step of selecting Ar corona treatments after daughter is handled.
4. according to the method described in claim 1, it is characterised in that SiH in the sub-step (b)4The power of corona treatment For 50-1000w, pressure 0.5-10torr, gas flow 100-1000sccm.
5. according to the method described in claim 1, it is characterised in that in tetramethylsilane plasma in the sub-step (c) Power be 50-1000w, pressure 0.5-10torr, gas flow 100-1000sccm.
6. according to the method in claim 2 or 3, it is characterised in that the power of the Ar corona treatments is 200- 1000w, pressure is 0.5-5torr, and gas flow is 500-1000sccm.
7. according to the method described in claim 1, it is characterised in that the metal material is metallic copper.
8. according to the method described in claim 1, it is characterised in that the interlayer dielectric layer is porous ultra low-K material.
9. according to the method described in claim 1, it is characterised in that form metal interconnection structure on the semiconductor substrate Method is：
Etch stop layer, interlayer dielectric layer and hard mask stack are formed on the semiconductor substrate；
The etch stop layer, the interlayer dielectric layer and the hard mask stack are patterned, to form groove；
The groove is filled from metal material；
Planarisation step is performed to the interlayer dielectric layer.
10. method according to claim 9, it is characterised in that the etch stop layer is the silicon carbide layer of N doping.
11. method according to claim 9, it is characterised in that the hard mask stack includes the NCC stacked gradually Rock layers and teos layer.
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