KR100936805B1 - Method of manufacturing semiconductor device for prevent not open and punch - Google Patents

Method of manufacturing semiconductor device for prevent not open and punch Download PDF

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KR100936805B1
KR100936805B1 KR1020070043614A KR20070043614A KR100936805B1 KR 100936805 B1 KR100936805 B1 KR 100936805B1 KR 1020070043614 A KR1020070043614 A KR 1020070043614A KR 20070043614 A KR20070043614 A KR 20070043614A KR 100936805 B1 KR100936805 B1 KR 100936805B1
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storage node
node contact
semiconductor device
etching
contact plug
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KR1020070043614A
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Korean (ko)
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KR20080098213A (en
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김태한
남기원
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 스토리지노드콘택플러그와 주변 구조간의 단차를 줄여 오픈 불량을 방지함과 동시에 후속 식각공정시 질화막질의 펀치를 방지하여 공정마진을 확보할 수 있는 반도체소자의 제조 방법을 제공하기 위한 것으로, 본 발명의 반도체소자의 제조 방법은 기판 상에 스토리지노드콘택홀이 구비된 절연막을 형성하는 단계; 상기 스토리지노드콘택홀을 채울때까지 전면에 도전막을 형성하는 단계; 상기 도전막을 제1에치백공정으로 식각하여 상기 스토리지노드콘택홀 내부에 스토리지노드콘택플러그를 형성하는 단계; 상기 스토리지노드콘택플러그를 포함한 전면에 희생막(SOG)을 형성하는 단계; 상기 희생막의 표면을 평탄화시키는 단계; 및 상기 평탄화된 희생막을 제2에치백공정으로 제거하면서 상기 스토리지노드콘택플러그 주변의 절연막을 일부 제거하는 단계를 포함한다.The present invention is to provide a method of manufacturing a semiconductor device that can reduce the step between the storage node contact plug and the surrounding structure to prevent open defects and at the same time prevent the punch of the nitride film during the subsequent etching process to secure a process margin. A method of manufacturing a semiconductor device of the present invention includes forming an insulating film having a storage node contact hole on a substrate; Forming a conductive film on an entire surface of the semiconductor device until the storage node contact hole is filled; Etching the conductive layer by a first etch back process to form a storage node contact plug in the storage node contact hole; Forming a sacrificial layer (SOG) on the entire surface including the storage node contact plug; Planarizing the surface of the sacrificial layer; And removing a portion of the insulating layer around the storage node contact plug while removing the planarized sacrificial layer by a second etch back process.

스토리지노드콘택플러그, 단차, 아르곤 스퍼터링, 펀치 Storage node contact plug, step, argon sputtering, punch

Description

오픈불량 및 펀치 방지를 위한 반도체소자의 제조 방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE FOR PREVENT NOT OPEN AND PUNCH}TECHNICAL MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE FOR PREVENTION OF OPEN FAULT AND PUNCH {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE FOR PREVENT NOT OPEN AND PUNCH}

도 1은 종래기술에 따른 반도체소자의 제조 방법을 도시한 도면.1 is a view showing a method for manufacturing a semiconductor device according to the prior art.

도 2는 종래기술에 따른 오픈불량 및 식각배리어막의 펀치를 나타낸 도면.2 is a view showing a punch of an open defect and an etching barrier film according to the prior art.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도,3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

도 4는 종래기술과 본 발명의 스토리지노드콘택플러그를 비교한 사진.Figure 4 is a photograph comparing the storage node contact plug of the prior art and the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 기판 22 : 층간절연막21 substrate 22 interlayer insulating film

23 : 폴리실리콘막 23A : 스토리지노드콘택플러그23: polysilicon film 23A: storage node contact plug

24 : 희생막 25 : 식각배리어막24: sacrificial film 25: etching barrier film

26 : 분리절연막 27 : 오픈영역26: isolation insulating film 27: open area

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 스토리지노드콘택플러그와 주변구조간의 단차를 완화시키는 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for alleviating a step between a storage node contact plug and a peripheral structure.

최근 고집적메모리소자에서 패턴의 미세화로 인해 스토리지노드가 형성될 공간을 제공하는 오픈영역(Storage node hole) 등과 같은 홀패턴의 간격(Hole spacing)이 좁아지고 있다. 이에 따라 높은 종횡비 프로파일(High Aspect profile)로 인해 마진이 급속히 줄어들게 되어 하부층의 단차도 증가한다.Recently, due to the miniaturization of patterns in high-density memory devices, spacing of hole patterns such as storage node holes and the like, which provide a space for forming storage nodes, is narrowing. As a result, the margin is rapidly reduced due to the high aspect profile, which increases the level of the lower layer.

도 1은 종래기술에 따른 반도체소자의 제조 방법을 도시한 도면이고, 도 2는 종래기술에 따른 오픈불량 및 식각배리어막의 펀치를 나타낸 도면이다.1 is a view showing a method of manufacturing a semiconductor device according to the prior art, Figure 2 is a view showing a punch of an open defect and etching barrier film according to the prior art.

도 1을 참조하면, 기판(11) 상에 층간절연막(12)을 형성하고, 층간절연막(12)을 식각하여 스토리지노드콘택홀을 형성하다. 이후, 스토리지노드콘택홀을 채우도록 폴리실리콘막을 증착한 후 에치백을 진행하여 스토리지노드콘택플러그(13)를 형성한다.Referring to FIG. 1, an interlayer insulating layer 12 is formed on a substrate 11, and the interlayer insulating layer 12 is etched to form a storage node contact hole. Thereafter, a polysilicon layer is deposited to fill the storage node contact hole, and then etched back to form the storage node contact plug 13.

그러나, 종래기술은 스토리지노드콘택플러그(Storage node cotact plug, 13) 형성시 폴리실리콘 증착 및 에치백(Etch back)의 순서로 진행하는데, 에치백후 폴리실리콘 디싱(polysilicon dishing) 및 플러그손실(Plug loss)이 증가하면 단차가 심해진다('D' 참조).However, the prior art proceeds in the order of polysilicon deposition and etch back when forming a storage node contact plug (13), polysilicon dishing and plug loss after etch back. ) Increases, the step gets worse (see 'D').

이와 같은 심한 단차(D)로 인해, 도 2에 도시된 바와 같이, 오픈영역(16)을 형성하기 위한 분리절연막(15) 식각공정시 하부 구조의 단차(D)에 따른 식각 마진 부족에 의해 오픈불량(Not Open, 도면부호 '16A')이 발생할 우려가 있다. Due to such a severe step (D), as shown in FIG. 2, due to insufficient etching margin due to the step (D) of the underlying structure during the etching process of the insulating insulating film 15 to form the open region 16. There is a fear that a defect (Not Open, reference numeral '16A') may occur.

오픈불량을 감소시키기 위해 식각 진행 시간을 늘리면 분리절연막(15) 식각 시에 하부의 식각배리어막(14)의 펀치(Punch, 16B)가 발생되어 이후 식각배리어막 (14) 식각시 하부구조가 어택을 받아 전기적 특성 저하를 가져오게 되며, 이로써 리프레시(Refresh) 저하의 주된 원인이 된다. When the etching progress time is increased to reduce the open defect, a punch (Punch, 16B) of the lower etching barrier layer 14 is generated at the time of etching the separation insulating layer 15, and then the underlying structure is attacked when etching the etching barrier layer 14. This results in deterioration of electrical characteristics, which is a major cause of refresh deterioration.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 스토리지노드콘택플러그와 주변 구조간의 단차를 줄여 오픈 불량을 방지함과 동시에 후속 식각공정시 질화막질의 펀치를 방지하여 공정마진을 확보할 수 있는 반도체소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, by reducing the step between the storage node contact plug and the surrounding structure to prevent open defects and at the same time prevent the punch of the nitride film during the subsequent etching process to secure a process margin It is an object of the present invention to provide a method for manufacturing a semiconductor device.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 기판 상에 스토리지노드콘택홀이 구비된 절연막을 형성하는 단계; 상기 스토리지노드콘택홀을 채울때까지 전면에 도전막을 형성하는 단계; 상기 도전막을 제1에치백공정으로 식각하여 상기 스토리지노드콘택홀 내부에 스토리지노드콘택플러그를 형성하는 단계; 상기 스토리지노드콘택플러그를 포함한 전면에 희생막을 형성하는 단계; 상기 희생막의 표면을 평탄화시키는 단계; 및 상기 평탄화된 희생막을 제2에치백공정으로 제거하면서 상기 스토리지노드콘택플러그 주변의 절연막을 일부 제거하는 단계를 포함하는 것을 특징으로 하며, 상기 희생막은 스핀온코팅법으로 형성하는 것을 특징으로 하고, 상기 희생막과 절연막은 상기 제2에치백공정시 동일한 식각속도를 가지 는 물질로 형성하는 것을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating film having a storage node contact hole on the substrate; Forming a conductive film on an entire surface of the semiconductor device until the storage node contact hole is filled; Etching the conductive layer by a first etch back process to form a storage node contact plug in the storage node contact hole; Forming a sacrificial layer on the entire surface including the storage node contact plug; Planarizing the surface of the sacrificial layer; And removing a portion of the insulating layer around the storage node contact plug while removing the planarized sacrificial layer by a second etch back process, wherein the sacrificial layer is formed by a spin-on coating method. The sacrificial layer and the insulating layer may be formed of a material having the same etching rate during the second etch back process.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 3a 내지 도 3e는 본 발명의 실시예에 따른 스토리지노드콘택플러그의 형성 방법을 도시한 공정 단면도이다.3A to 3E are cross-sectional views illustrating a method of forming a storage node contact plug according to an exemplary embodiment of the present invention.

도 3a에 도시된 바와 같이, 트랜지스터 및 비트라인 등의 소정 공정이 완료된 기판(21) 상부에 층간절연막(22)을 형성한 후, 층간절연막(22)을 선택적으로 식각하여 스토리지노드콘택홀(SNC, 도면부호 생략)을 형성한다. 여기서, 층간절연막(22)은 BPSG와 같은 산화막 물질로 형성한다.As shown in FIG. 3A, the interlayer insulating layer 22 is formed on the substrate 21 on which a predetermined process such as a transistor and a bit line is completed, and then the interlayer insulating layer 22 is selectively etched to store the storage node contact hole (SNC). , Reference numerals are omitted). Here, the interlayer insulating film 22 is formed of an oxide film material such as BPSG.

이어서, 스토리지노드콘택홀에 매립된 스토리지노드콘택플러그(23)를 형성한다.Subsequently, the storage node contact plug 23 embedded in the storage node contact hole is formed.

스토리지노드콘택플러그(23)는 스토리지노드콘택홀을 채울때까지 전면에 폴리실리콘막을 증착한 후, 폴리실리콘막을 에치백(Etchback)하여 형성한다. 폴리실리콘막의 에치백 공정은 플라즈마 식각 장비의 일종인 TCP 장비에서 메인식각(Main etch)과 과도식각(Over etch)으로 이루어진다. 메인식각은 스토리지노드콘택홀 외측의 층간절연막(22) 표면의 폴리실리콘막(23)을 식각하여 스토리지노드콘택홀 내부에만 폴리실리콘막을 잔류시키는 식각이다. 위와 같은 메인식각후에는 폴리실리콘 잔류물(Polysilicon residue)을 제거하기 위한 과도식각(Over etch)을 진행하여 스토리지노드콘택플러그(23)를 최종적으로 완성한다.The storage node contact plug 23 is formed by depositing a polysilicon film on the entire surface until the storage node contact hole is filled, and then etching back the polysilicon film. The etchback process of the polysilicon film is made of main etching and overetching in TCP equipment, which is a kind of plasma etching equipment. The main etching is to etch the polysilicon layer 23 on the surface of the interlayer insulating layer 22 outside the storage node contact hole, thereby leaving the polysilicon layer only inside the storage node contact hole. After the main etching as described above, the over-etch to remove the polysilicon residue (polysilicon residue) is carried out to finally complete the storage node contact plug (23).

위와 같은 과도 식각후에 스토리지노드콘택플러그(23)와 주변의 층간절연막(22) 간에는 일정 수준의 단차('D11' 참조)가 존재하게 된다. 이러한 단차는 폴리실리콘막의 에치백공정 중 과도식각에 의해 스토리지노드콘택플러그(23) 상부 표면에서 폴리실리콘막 손실(Polysilicon loss)이 발생되기 때문이며, 이 단차는 후속 오픈영역의 오픈불량 및 식각배리어막의 펀치현상을 유발한다. 한편, 폴리실리콘막 손실은 '플러그손실(Plug loss)'이라고도 일컫는다.After the excessive etching as described above, a certain level of difference (see 'D11') exists between the storage node contact plug 23 and the surrounding interlayer insulating layer 22. This step is caused by the polysilicon loss on the upper surface of the storage node contact plug 23 due to the excessive etching during the etch back process of the polysilicon film. Cause punching. On the other hand, polysilicon film loss is also referred to as 'plug loss'.

본 발명은 이러한 단차에 의한 후속 공정의 불량을 방지하기 위해 다음과 같은 공정을 진행한다.The present invention proceeds as follows to prevent the failure of the subsequent process due to this step.

도 3b에 도시된 바와 같이, 스토리지노드콘택플러그(23) 상부를 덮도록 전면에 희생막(24)을 형성한다. 이때, 희생막(24)은 스핀온코팅법(Spin on coating)을 이용하여 형성한다. 예를 들어, 희생막(24)은 SOG(Spin On Glass)이며, 스핀온코팅법을 이용하므로 갭필특성이 우수하다. 따라서, 플러그손실 부분을 충분히 갭필할 수 있고, 이로써 스토리지노드콘택플러그(23) 상부에서 스토리지노드콘택플러그(23) 주변부보다 더 두껍게 형성할 수 있다.As shown in FIG. 3B, a sacrificial layer 24 is formed on the entire surface of the storage node contact plug 23 to cover the upper portion thereof. In this case, the sacrificial layer 24 is formed by using a spin on coating method. For example, the sacrificial film 24 is spin on glass (SOG), and the spin fill coating method is used to provide excellent gap fill characteristics. Therefore, the plug loss portion can be sufficiently gapfilled, and thus, the plug loss portion can be formed to be thicker than the peripheral portion of the storage node contact plug 23 on the storage node contact plug 23.

바람직하게, 희생막(24)과 층간절연막(22)은 건식식각, 특히 에치백공정시 식각속도가 1:1이 되는 물질로 형성한다. 예컨대, 층간절연막(22)이 산화막인 경우 희생막(24)도 산화막이 될 것이며, SOG도 일종의 산화막 물질이다.Preferably, the sacrificial layer 24 and the interlayer insulating layer 22 are formed of a material having an etching rate of 1: 1 in dry etching, particularly in an etch back process. For example, when the interlayer insulating film 22 is an oxide film, the sacrificial film 24 will also be an oxide film, and SOG is a kind of oxide film material.

도 3c에 도시된 바와 같이, 비활성가스의 스퍼터링, 특히 아르곤 스퍼터링(Ar sputtering)을 진행하여 희생막(24)의 표면을 평탄화시킨다.As shown in FIG. 3C, sputtering of the inert gas, in particular argon sputtering, is performed to planarize the surface of the sacrificial film 24.

아르곤스퍼터링에 의해 희생막패턴(24A)이 스토리지노드콘택플러그(23) 상부에서 스토리지노드콘택플러그(23) 주변부보다 더 두껍게 잔류한다(D1＞D2).Due to argon sputtering, the sacrificial film pattern 24A remains thicker than the peripheral portion of the storage node contact plug 23 on the storage node contact plug 23 (D1> D2).

위와 같이 아르곤 스퍼터링은 희생막패턴(24A)의 평탄화를 확보하고 스토리지노드콘택플러그(23)의 손실은 발생시키지 않는다. 특히, 아르곤스퍼터링을 통해 평탄화하면, 후속 희생막패턴의 에치백공정시 식각균일도를 확보하여 스토리지노드콘택플러그의 추가 손실을 방지할 수 있다.As described above, argon sputtering ensures planarization of the sacrificial film pattern 24A and does not cause loss of the storage node contact plug 23. In particular, when planarization is performed through argon sputtering, an etching uniformity may be secured during the subsequent etchback process of the sacrificial layer pattern, thereby preventing additional loss of the storage node contact plug.

도 3d에 도시된 바와 같이, 에치백공정을 통해 희생막패턴(24A)을 제거한다. 이때, 에치백공정은 스토리지노드콘택플러그(23)의 표면이 노출될때까지 진행하므로써, 스토리지노드콘택플러그(23) 주변지역의 층간절연막 상부(도면부호 '22B')까지 식각한다. 즉, 희생막패턴(24A)의 에치백공정시 주변부의 층간절연막 상부(22B)보다 스토리지노드콘택플러그(23)의 표면이 늦게 노출되므로 스토리지노드콘택플러그(23)의 추가 손실은 최소화하면서 식각마진을 충분히 확보할 수 있다.As shown in FIG. 3D, the sacrificial layer pattern 24A is removed through an etch back process. At this time, the etch back process is performed until the surface of the storage node contact plug 23 is exposed, thereby etching the upper portion of the interlayer insulating film (reference numeral '22B') around the storage node contact plug 23. That is, during the etch back process of the sacrificial layer pattern 24A, the surface of the storage node contact plug 23 is exposed later than the upper surface 22B of the interlayer insulating layer 22 of the peripheral portion, so that the additional loss of the storage node contact plug 23 is minimized while the etching margin is minimized. Can be secured sufficiently.

결국, 에치백공정후에 잔류하는 층간절연막(22A) 표면과 스토리지노드콘택플러그(23)의 표면간 단차가 감소된다.As a result, the step difference between the surface of the interlayer insulating film 22A remaining after the etch back process and the surface of the storage node contact plug 23 is reduced.

바람직하게, SOG로 형성된 희생막패턴(24A)의 에치백공정은 플라즈마식각장비의 일종인 TCP(Transformer Coupled Plasma) 장비에서 진행하되, 바이어스파워와 압력은 최대한 낮게 하여 등방성식각을 유도한다. 예컨대, 바이어스파워(Bias power)는 50∼60W로 작게 하고, 압력은 3∼5mTorr로 낮게 한다. 특히, 압력이 3∼5mTorr로 낮으면 식각제(Etchant)의 평균자유행로(Mean free path)가 증가되어 입자의 입자의 스캐터링(Scattering) 효과를 감소시켜 등방성 식각을 유도하게 된다. 그리고, TCP 장비의 온도를 40℃ 이상(50∼60℃)으로 높여서 플라즈마활성도를 높인다. 이처럼 플라즈마활성도를 높이면 입자간 충돌이 많이 발생되어 산화막에 대한 물리적 식각특성을 줄여주고, 결국 낮은 식각속도를 유도하고 등방성식각을 증대시켜 평탄화를 확보한다.Preferably, the etch back process of the sacrificial film pattern 24A formed of SOG is performed in TCP (Transformer Coupled Plasma) equipment, which is a kind of plasma etching equipment. For example, the bias power is reduced to 50 to 60 W, and the pressure is lowered to 3 to 5 mTorr. In particular, when the pressure is low to 3 to 5mTorr, the mean free path of the etchant is increased to reduce the scattering effect of the particles of the particles, thereby inducing isotropic etching. In addition, the temperature of the TCP equipment is increased to 40 ° C. or higher (50 to 60 ° C.) to increase plasma activity. As such, increasing plasma activity results in a lot of collisions between particles, which reduces physical etching characteristics of the oxide film, thereby inducing a low etching rate and increasing isotropic etching to secure planarization.

그리고, 에치백공정시 식각가스는 불소(Fluorine) 계열 가스를 메인가스로 사용한다. 특히 SF6 가스를 100sccm 이상(100sccm∼500sccm)으로 사용하면 스토리지노드콘택플러그(23)로 사용된 폴리실리콘막에 대한 식각선택비를 10:1 이상으로 높이고, 희생막패턴(24A)과 층간절연막(22)간에는 1:1의 식각선택비를 갖게 할 수 있다. 그리고, 메인가스에 질소(N2) 가스를 소량 첨가할 수 있다. 이때, 질소가스는 5∼10sccm의 유량을 사용한다.In the etching back process, the etching gas uses fluorine-based gas as the main gas. In particular, when SF 6 gas is used at 100 sccm or more (100 sccm to 500 sccm), the etching selectivity for the polysilicon film used as the storage node contact plug 23 is increased to 10: 1 or more, and the sacrificial film pattern 24A and the interlayer insulating film are made. It is possible to have an etching selectivity of 1: 1 between (22). Then, a small amount of nitrogen (N 2 ) gas can be added to the main gas. At this time, nitrogen gas uses a flow rate of 5 to 10 sccm.

그리고, 에치백공정시 소스파워는 500W∼1000W로 사용한다.In the etchback process, the source power is 500W to 1000W.

전술한 바와 같은 조건에 의해 에치백을 진행하면 스토리지노드콘택플러그(23B)의 손실은 억제하면서 희생막패턴(24A)과 층간절연막 상부(22B)를 동시에 식각하므로, 에치백 후에는 스토리지노드콘택플러그(23)와 그 주변의 층간절연막(22A)간 단차를 현저히 감소시킬 수 있다.When the etch back is performed under the conditions described above, the sacrificial film pattern 24A and the upper portion of the interlayer insulating film 22B are simultaneously etched while suppressing the loss of the storage node contact plug 23B. Thus, after the etch back, the storage node contact plug is etched. The step difference between the interlayer insulating film 22A and the surroundings 23 can be significantly reduced.

도 3e에 도시된 바와 같이, 전면에 식각배리어막(25)을 증착한 후, 식각배리어막(25) 상에 분리절연막(26)을 형성한다. 여기서, 식각배리어막(25)은 질화막이고, 분리절연막(26)은 산화막 물질이다. 그리고, 분리절연막(26)은 후속 오픈영역에 형성되는 캐패시터의 하부전극간 분리막이다.As shown in FIG. 3E, after the etching barrier layer 25 is deposited on the entire surface, the isolation insulating layer 26 is formed on the etching barrier layer 25. Here, the etching barrier film 25 is a nitride film, and the isolation insulating film 26 is an oxide film material. The isolation insulating layer 26 is a separator between the lower electrodes of the capacitor formed in the subsequent open area.

위와 같이 식각배리어막(25)은 하부 구조의 단차가 완화된 상태에서 형성되므로 두께균일도가 확보된다.As described above, since the etching barrier layer 25 is formed in a state in which the step difference of the lower structure is relaxed, the thickness uniformity is secured.

이어서, 분리절연막(26)과 식각배리어막(25)을 순차적으로 건식식각하여 스토리지노드콘택플러그(23)의 표면을 노출시키는 오픈영역(27)을 형성한다. 여기서, 오픈영역(27) 형성을 위한 건식식각은 식각배리어막(25)에서 식각이 정지할때까지 분리절연막(26)을 식각하고, 연속해서 식각배리어막(25)을 식각한다. Subsequently, the isolation insulating layer 26 and the etching barrier layer 25 are sequentially dry-etched to form an open area 27 exposing the surface of the storage node contact plug 23. Here, in the dry etching for forming the open area 27, the isolation insulating layer 26 is etched until the etching is stopped in the etching barrier layer 25, and the etching barrier layer 25 is subsequently etched.

위와 같은 식각공정시 하부 구조의 단차가 완화된 상태에서 식각배리어막(25)과 분리절연막(26)이 형성되므로 분리절연막(26) 식각시 오픈불량이 발생하지 않고, 이로써 식각시간을 늘릴 필요가 없으므로 분리절연막(26) 식각시 식각배리어막(25)의 펀치가 발생하지 않는다. 오픈영역(27)은 캐패시터의 하부전극이 형성될 3차원 구조이다.Since the etching barrier layer 25 and the isolation insulating layer 26 are formed in the state that the level difference of the lower structure is relaxed during the etching process as described above, no open defect occurs when the isolation insulating layer 26 is etched, thereby increasing the etching time. Therefore, when the isolation insulating layer 26 is etched, the punch of the etching barrier layer 25 does not occur. The open area 27 is a three-dimensional structure in which the lower electrode of the capacitor is to be formed.

도 4는 종래기술과 본 발명의 스토리지노드콘택플러그를 비교한 사진으로서, 본 발명에 의한 스토리지노드콘택플러그와 주변의 층간절연막간 단차가 종래기술에 비해 현저히 완화됨을 알 수 있다. 예컨대, 종래기술에서는 600Å 이상의 플러그손실이 발생하여 단차가 매우 심하게 발생하였으나, 본 발명의 실시예에서는 플러그손실이 100Å 이하로 발생하여 단차가 현저히 감소된다.Figure 4 is a photograph comparing the prior art and the storage node contact plug of the present invention, it can be seen that the step between the storage node contact plug and the surrounding interlayer insulating film according to the present invention is significantly reduced compared to the prior art. For example, in the prior art, a plug loss of 600 mW or more occurs and the step is very severe. However, in the embodiment of the present invention, the plug loss is less than 100 mW and the step is significantly reduced.

상술한 실시예에 따르면, 식각배리어막 형성전에 스토리지노드콘택플러그 및 그 주변부간 단차를 완화시키므로써, 식각배리어막의 두께균일도를 확보할 수 있고, 이에 따라 후속 분리절연막 식각시 오픈불량 및 펀치현상을 방지할 수 있다.According to the above-described embodiment, by reducing the step difference between the storage node contact plug and the peripheral portion before forming the etching barrier film, it is possible to ensure the thickness uniformity of the etching barrier film, thereby preventing the open defect and punch phenomenon during the subsequent etching of the isolation insulating film. You can prevent it.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 스토리지노드콘택플러그와 주변구조간의 단차를 완화시키므로써 후속 오픈영역 형성을 위한 식각공정의 마진 확보 및 식각배리어막의 펀치를 방지하여 소자의 전기적 특성 향상 및 이로 인한 수율증가, 신뢰성증대를 가져올 수 있는 효과가 있다.The present invention as described above reduces the step between the storage node contact plug and the peripheral structure to secure the margin of the etching process for the formation of the subsequent open area and to prevent the punch of the etching barrier film to improve the electrical characteristics of the device, thereby increasing the yield, reliability increase Has the effect of bringing.

Claims (13)

기판 상에 스토리지노드콘택홀이 구비된 절연막을 형성하는 단계;Forming an insulating layer having a storage node contact hole on the substrate; 상기 스토리지노드콘택홀을 채울때까지 전면에 도전막을 형성하는 단계;Forming a conductive film on an entire surface of the semiconductor device until the storage node contact hole is filled; 상기 도전막을 제1에치백공정으로 식각하여 상기 스토리지노드콘택홀 내부에 스토리지노드콘택플러그를 형성하는 단계;Etching the conductive layer by a first etch back process to form a storage node contact plug in the storage node contact hole; 상기 스토리지노드콘택플러그를 포함한 전면에 희생막을 형성하는 단계;Forming a sacrificial layer on the entire surface including the storage node contact plug; 상기 희생막의 표면을 평탄화시키는 단계; 및Planarizing the surface of the sacrificial layer; And 상기 평탄화된 희생막을 제2에치백공정으로 제거하면서 상기 스토리지노드콘택플러그 주변의 절연막을 일부 제거하는 단계Partially removing the insulating layer around the storage node contact plug while removing the planarized sacrificial layer by a second etch back process; 를 포함하는 반도체소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 스토리지노드콘택플러그 주변의 절연막을 일부 제거하는 단계후에,After removing a portion of the insulating film around the storage node contact plug, 전면에 식각배리어막을 형성하는 단계;Forming an etching barrier layer on a front surface thereof; 상기 식각배리어막 상에 분리절연막을 형성하는 단계; Forming a separation insulating layer on the etching barrier layer; 상기 분리절연막을 식각하는 단계; 및Etching the separation insulating film; And 상기 식각배리어막을 식각하여 상기 스토리지노드콘택플러그의 표면을 노출시키는 단계Etching the etching barrier layer to expose a surface of the storage node contact plug. 를 더 포함하는 반도체소자의 제조 방법.Method of manufacturing a semiconductor device further comprising. 제1항에 있어서,The method of claim 1, 상기 희생막은, 스핀온코팅법으로 형성하는 반도체소자의 제조 방법.The sacrificial film is formed by a spin-on coating method. 제1항에 있어서,The method of claim 1, 상기 희생막과 절연막은 상기 제2에치백공정시 동일한 식각속도를 가지는 물질로 형성하는 반도체소자의 제조 방법.The sacrificial layer and the insulating layer are formed of a material having the same etching rate during the second etch back process. 제4항에 있어서,The method of claim 4, wherein 상기 희생막과 절연막은 산화막으로 형성하는 반도체소자의 제조 방법.And the sacrificial film and the insulating film are formed of an oxide film. 제5항에 있어서,The method of claim 5, 상기 절연막은, SOG(Spin On Glass)로 형성하는 반도체소자의 제조 방법.The insulating film is a semiconductor device manufacturing method of forming a spin on glass (SOG). 제4항에 있어서,The method of claim 4, wherein 상기 제2에치백공정은,The second etch back process, TCP(Transformer Coupled Plasma) 장비에서 진행하는 반도체소자의 제조 방법.Method of manufacturing a semiconductor device in a TCP (Transformer Coupled Plasma) equipment. 제7항에 있어서,The method of claim 7, wherein 상기 제2에치백공정은, The second etch back process, 바이어스파워(Bias power)는 50∼60W로 하고, 압력은 3∼5mTorr로 하며, 온도를 50∼60℃로 하여 진행하는 반도체소자의 제조 방법.A method of manufacturing a semiconductor device in which the bias power is set to 50 to 60 W, the pressure is set to 3 to 5 mTorr, and the temperature is set to 50 to 60 ° C. 제8항에 있어서,The method of claim 8, 상기 제2에치백공정시,In the second etch back process, 식각가스는 불소(Fluorine) 계열 가스를 메인가스로 사용하는 반도체소자의 제조 방법.Etching gas is a method for manufacturing a semiconductor device using a fluorine-based gas as the main gas. 제9항에 있어서,The method of claim 9, 상기 불소계 가스는 SF6 가스를 100sccm∼500sccm의 유량으로 사용하는 반도체소자의 제조 방법.The fluorine-based gas is a manufacturing method of a semiconductor device using SF 6 gas at a flow rate of 100sccm to 500sccm. 제9항에 있어서,The method of claim 9, 상기 제2에치백공정시 상기 메인가스에 질소(N2) 가스를 더 첨가하여 진행하는 반도체소자의 제조 방법.And further adding nitrogen (N 2 ) gas to the main gas during the second etch back process. 제1항에 있어서,The method of claim 1, 상기 희생막 표면을 평탄화시키는 단계는,Planarizing the sacrificial layer surface may include: 아르곤 스퍼터링으로 진행하는 반도체소자의 제조 방법.A manufacturing method of a semiconductor device which proceeds by argon sputtering. 제1항에 있어서,The method of claim 1, 상기 도전막은, 폴리실리콘막으로 형성하는 반도체소자의 제조 방법.The said conductive film is a manufacturing method of the semiconductor element formed from a polysilicon film.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106252218A (en) * 2016-09-30 2016-12-21 上海华虹宏力半导体制造有限公司 Trench MOSFET grid etch process

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JPH07221074A (en) * 1994-02-01 1995-08-18 Sony Corp Dry etching method
KR20020048627A (en) * 2000-12-18 2002-06-24 박종섭 Method for forming polysilicon plug in semiconductor device
KR20050068812A (en) * 2003-12-30 2005-07-05 주식회사 하이닉스반도체 Method for forming landing plug contact in semiconductor device
KR20060074979A (en) * 2004-12-28 2006-07-04 주식회사 하이닉스반도체 Method forming of landing plug contact in semiconductor device

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Publication number Priority date Publication date Assignee Title
JPH07221074A (en) * 1994-02-01 1995-08-18 Sony Corp Dry etching method
KR20020048627A (en) * 2000-12-18 2002-06-24 박종섭 Method for forming polysilicon plug in semiconductor device
KR20050068812A (en) * 2003-12-30 2005-07-05 주식회사 하이닉스반도체 Method for forming landing plug contact in semiconductor device
KR20060074979A (en) * 2004-12-28 2006-07-04 주식회사 하이닉스반도체 Method forming of landing plug contact in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106252218A (en) * 2016-09-30 2016-12-21 上海华虹宏力半导体制造有限公司 Trench MOSFET grid etch process

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