JP4085639B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4085639B2
JP4085639B2 JP2002017955A JP2002017955A JP4085639B2 JP 4085639 B2 JP4085639 B2 JP 4085639B2 JP 2002017955 A JP2002017955 A JP 2002017955A JP 2002017955 A JP2002017955 A JP 2002017955A JP 4085639 B2 JP4085639 B2 JP 4085639B2
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electrode
semiconductor device
insulating film
control electrode
main electrode
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JP2003218306A (en
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卓 梅垣
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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Description

【０００１】
【発明の属する技術分野】
この発明は、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）モジュールなどモジュールの構造をした半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
ＩＧＢＴモジュールなどのパワー半導体デバイス（半導体装置）は、図８に示すように、通常、配線基板６６に形成した銅配線６５上に、図７に示すＩＧＢＴチップなどの半導体チップ５１（以下、チップと称す）の裏面電極を全面ハンダ付けして固着し、チップ５１の表面電極である主電極５４とゲート電極５５は、１本ないし複数のアルミワイヤ７３、７４をボンディングすることによりエミッタ端子６８やゲート端子６９である外部導出端子とそれぞれ接続されている。通常、チップ５１はパッケージに複数個収納されている。
【０００３】
【発明が解決しようとする課題】
前記のアルミワイヤボンディングには次のような問題点がある。
１）チップ容量が大きくなると必要な電流容量を確保するために必要なワイヤ本数が増加し、ボンディング工数やワイヤボンダーの設備投資が増え、結果として高コストとなる。
２）ワイヤ７３や配線基板上の銅配線パターンの断面積を十分に確保することが構造上難しく、その結果、配線抵抗や配線インダクタンスの増加により、素子の発熱や、応答特性に問題が生じることがある。
３）ワイヤ７３の本数を低減するために使用するワイヤ７３の直径を太くしようとしても、太線をボンディングする接合条件が厳しくなり、チップを破損する恐れがあるので、太線化にも限界がある。
【０００４】
これらの問題を解決するために、ワイヤボンディングという方法でなく、図９に示すような、チップ５１の主電極５４や制御電極５５に銅のリードフレーム６８、６９を直接接合する構造などが開示されている。
しかしながら、図９のように、チップの主電極にリードフレーム６８、６９を接続する場合は、リードフレーム６８、６９によるチップ５１に発生する応力を緩和するために、リードフレーム６８、６９は円７４に示すように複雑な構造にする必要があり、製造コストが高くなる。この複雑な構造とするのは、リードフレーム６８、６９にフリキシビリティを持たせるためである。
【０００５】
また、配線回路基板に形成した銅配線をチップ表面の主電極や制御電極に直接、半田などで接合すると、半田の横方向への広がりや、チップ表面と配線回路基板との距離が極めて短くなることで、チップ表面に形成された主電極と制御電極との間の電気的絶縁性、主電極、制御電極と接続する銅配線と耐圧構造（ガードリングなど）との電気的絶縁性が低下する。
【０００６】
この発明の目的は、前記の課題を解決して、低コストで、主電極と制御電極との間、主電極、制御電極と接続する銅配線と耐圧構造との間の電気的絶縁性が良好な半導体装置およびその製造方法を提供することにある。
【０００７】
【課題を解決するための手段】
前記の目的を達成するために、半導体チップの同一平面上に形成した主電極と制御電極と、前記半導体チップに形成した耐圧構造と、前記主電極と接続する第１外部導出導体と、前記制御電極と接続する第２外部導出導体とを具備するモジュール構造の半導体装置において、
半導体チップ上全面に形成され、主電極と制御電極の箇所を開口した絶縁膜と、該絶縁膜の開口部で、固着材を介して、前記主電極と固着し、前記絶縁膜上に形成される第１外部導出導体と、前記制御電極と固着し、前記絶縁膜上に形成される第２外部導出導体とを有する構成とする。
【０００８】
また、前記絶縁膜が、有機絶縁膜であるとよい。
また、前記絶縁膜の厚さが５０〜１００μｍであるとよい。
また、前記、第１および第２外部導出導体が、リードフレームもしくは配線回路基板の配線であるとよい。
また、前記固着材が、ハンダもしくはハンダペーストであるとよい。
【０００９】
また、半導体チップの同一平面上に形成した主電極と制御電極と、前記半導体チップに形成した耐圧構造と、前記主電極と接続する第１外部導出導体と、前記制御電極と接続する第２外部導出導体とを具備するモジュール構造の半導体装置の製造方法において、
耐圧構造と活性領域を形成した半導体ウエハ上に主電極と制御電極とを形成する工程と、半導体ウエハ上全面に、主電極と制御電極の箇所を開口した絶縁膜を形成する工程と、該半導体ウエハを切断してチップ化する工程と、該チップ化された半導体チップに形成された主電極と制御電極とを、第１外部導出導体、第２外部導出導体に固着材でそれぞれ固着する工程とを含む製造方法とする。
【００１０】
【発明の実施の形態】
図１から図３は、この発明の第１実施例の半導体装置であり、図１は半導体チップの平面図、図２は絶縁シートの平面図、図３は半導体装置の要部断面図である。
図１から図３において、図１で示すＩＧＢＴチップ１上に、図２で示す、エミッタ電極４上とゲート電極５上に位置する箇所に開口部７、８を設けた絶縁シート６を貼着する。この絶縁シートの開口部７、８に位置するエミッタ電極４上、ゲート電極５上に、固着材である半田９、１０（ハンダペーストなど）を、絶縁シートの厚さより多少高めに付着させ、配線基板１３の表面に形成された銅配線１１、１２（第１、第２外部導出導体に相当する）とエミッタ電極４、ゲート電極５とを半田９、１０を介して固着する。ＩＧＢＴチップの裏面を半田１７を介して配線基板１６の表面に形成した銅配線１５とを固着する。この配線基板１６と銅ベース２１（冷却導体）とを半田１７で固着する。銅配線１１、１２、１５とエミッタ端子１８、ゲート端子１９、コレクタ端子１８を固着し、プラスチックケース２２を銅ベース２１に固着する。尚、配線基板１３と銅配線１１、１２で配線回路基板（Ｄｉｒｅｃｔ Ｂｏｎｄｉｎｇ Ｃｏｐｐｅｒ基板など）を構成する。
【００１１】
前記絶縁シート６の主な目的は、外部導出体である銅配線１１、１２とＩＧＢＴチップ外周部に設けられたガードリング３との間の電気的絶縁を確保するためであるので、その間に加わる電界に長期間劣化せずに耐えるものでなければならない。通常この間の電圧は数十Ｖ〜数ｋＶであるので、素子の定格に応じた絶縁厚さを選択すればよい。有機絶縁膜としてポリイミド樹脂フィルムを用いる場合、その耐電圧は通常１００ｋＶ／ｍｍ程度などで、５０μｍ程度の厚さがあればよい。
【００１２】
しかし、実際の絶縁膜の厚さとしては、フィルムの入手性や加工性などを考慮して決められるべきであり、実用上は５０〜１００μｍ程度が好ましい。１００μｍを超えるものはフィルム材としては、加工性も悪く、高コストとなるし、塗布法により１００μｍを超える膜厚を得ようとするのも困難である。また、５０μｍ未満の場合は、電気的絶縁の信頼性が十分に得られない可能性がある。
【００１３】
従って、絶縁シート６の材としては、５０μｍ〜１００μｍのポリイミド樹脂シートが望ましいが、厚さはこれに限定するものではない。また樹脂材質もポリイミド樹脂に限らず、要求される耐熱温度や絶縁耐力に応じて、ポリエチレンテレフタレート樹脂、ポリエーテルエーテルケトン樹脂、ポリエーテルイミド樹脂、ポリサルフォン樹脂などのエンジニアリングプラスチック樹脂シートなどの有機絶縁材が使用可能である。
【００１４】
また、貼着の方法は、工程上、熱融着可能な接着剤を用いるか、シート自体の熱融着性を利用することが望ましいが、熱硬化性の接着剤でも良い。
この絶縁シート６があることにより、エミッタ電極である主電極とゲート電極である制御電極の間での絶縁性が確保される。
また、絶縁シート６は、ガードリング部直上に接着された構造になっているため、エミッタ電極４に固着された銅配線１１と耐圧構造であるガードリング３は、この絶縁シート６により絶縁されている。
【００１５】
上述のように、開口部７、８を設けた絶縁シート６をＩＧＢＴチップ１表面に貼着することにより、半田９、１０の横方向への広がりが防止できて、エミッタ電極４である主電極とゲート電極５である制御電極の間の電気的絶縁性が確実に確保できる。また、絶縁シート６によって、エミッタ電極４、ゲート電極５にそれぞれ接続する銅配線１１、１２と耐圧構造であるガードリング３の間の電気的絶縁性が確実に確保できる。
【００１６】
この開口部７、８の寸法としては、主電極および制御電極をそれぞれ外部導出導体と接合するためのものであるので、主電極および制御電極の面積に相当する開口部面積であればよい。実用上は、主電極および制御電極面積の３０〜１００％の開口部面積でると好ましい。主電極が複数個のセルに分割されているような場合においては、主電極要の開口部は、それぞれのセルに対応した複数個の開口部であってもよい。
【００１７】
また、外部導出導体である銅配線１１、１２の構造を単純な平板状とすることができる（従来は図９の円７２に示すように複雑な屈曲構造となっている）。
このように、外部導出導体である銅配線１１、１２の形状を単純化することで、製造コストを低減することができる。
図４は、この発明の第２実施例の半導体装置の要部断面図である。第１実施例と異なる点は、絶縁シート６のような絶縁物を貼着する構造ではなく、厚膜の絶縁層２３をエミッタ電極４やゲート電極５を除いて、その他の箇所に形成する点である。絶縁層２３の材質としては、ＩＧＢＴチップ１表面にパターン形成できる硬化性樹脂（有機絶縁材）ならどのようなものでも良いが、望ましくは、エポキシ樹脂、ポリイミド樹脂、ビスマレイミド樹脂などの耐熱性熱硬化性樹脂が良い。
【００１８】
このパターンの形成は、スクリーン印刷やスピンコーティング、真空印刷などを用いることができる。
また、エミッタ電極４の開口部７を、単一ではなく、１つのエミッタ電極４に対して、複数個の開口部を作り込むと、半田９との接合部に加わる熱応力などのストレスを緩和することができる。
【００１９】
また、絶縁層２３形成に当たって、液状の絶縁材料を用いると複数個の開口部を設けた場合には、開口部の平面パターンの自由度が向上する。勿論、ゲート電極５の開口部８も複数個形成しても構わない。
この発明により、第１実施例と同様に、低コストで、エミッタ電極４とゲート電極５の間の絶縁性およびエミッタ電極４、ゲート電極５と接続する銅配線１１、１２とガードリング３の間の絶縁性を確実に確保できる。
【００２０】
図５は、この発明の第３実施例の半導体装置の製造方法であり、同図（ａ）から同図（ｄ）は工程順に示した工程断面図である。これは図４の半導体装置の製造方法である。
ｐ型拡散領域、ｎ型拡散領域を形成したＩＧＢＴユニットが多数集積したウェハ１００のエミッタ電極側の表面にエミッタ電極、ゲート電極が露出した絶縁層２３を形成する（同図（ａ））。
【００２１】
つぎに、ＩＧＢＴチップとするために切断線２４で、ウェハ１００を切断する（同図（ｂ））。
つぎに、開口部に半田９、１０を充填する（同図（ｃ））。
つぎに、図示しないエミッタ電極、ゲート電極と、配線基板１３に形成した銅配線１１、１２とを半田９、１０を介して固着する。一方、ＩＧＢＴチップ１の裏面も、図示しない半田を介して、配線基板１６に形成した銅配線１５と固着する（同図（ｄ））。
【００２２】
つぎに、図４のように、銅ベース２１、エミッタ端子１８、ゲート端子１９、コレクタ端子２０を固着し、プラスチックケース２２を被せて半導体装置とする。
このように、絶縁層２３の形成をチップ切断前のウェハ状態で一括して行うことで、絶縁層２３の形成のコストを大幅に低減できる。また、この絶縁層２３は図４で説明した方法で形成する。さらに、絶縁層２３の代わりに、図３で示した絶縁シート１３を貼着する方法もある。
【００２３】
図６は、この発明の第４実施例の半導体装置の要部断面図である。前記の実施例との違いは、配線基板に形成した銅配線の代わりに、リードフレームのような導体を用いた点である。図６は図３に相当する要部断面図である。この場合は、絶縁シート６の上にリードフレーム２４、２５（第１、第２外部導出導体に相当する）を配置するために、リードフレーム２４、２５の厚さは極めて薄くできる。そのために、図９のような屈曲した複雑な構造でなく平面的なリードフレームでよく、低コスト化を図ることができる。また、主電極と制御電極の絶縁性と、主電極、制御電極と耐圧構造の絶縁性を確実に確保できる。
【００２４】
【発明の効果】
この発明によれば、主電極および制御電極と外部導出導体の電気的接続を、半導体チップ上に形成した絶縁膜の開口部を介して行ない、この外部導出導体を絶縁膜上に形成することで、主電極と制御電極間の絶縁性および主電極、制御電極と接続する外部導出導体と耐圧構造間の絶縁性の確保が容易にできる。
【００２５】
また、絶縁膜上に薄い外部導出導体を形成するために、外部導出導体の形状を単純化できて、低コストを図ることができる。
【図面の簡単な説明】
【図１】この発明の第１実施例の半導体装置の半導体チップの平面図
【図２】この発明の第１実施例の半導体装置の絶縁シートの平面図
【図３】この発明の第１実施例の半導体装置の要部断面図
【図４】この発明の第２実施例の半導体装置の要部断面図
【図５】この発明の第３実施例の半導体装置の製造方法であり、（ａ）から（ｄ）は工程順に示した工程断面図
【図６】この発明の第４実施例の半導体装置の要部断面図
【図７】ＩＧＢＴチップの平面図
【図８】従来の半導体装置の要部断面図
【図９】従来の別の半導体装置の要部断面図
【符号の説明】
１ ＩＧＢＴチップ
２ 活性領域
３ ガードリング
４ エミッタ電極
５ ゲート電極
６ 絶縁シート
７、８ 開口部
９、１０、１４、１７ 半田
１１、１２、１５ 銅配線
１３、１６ 配線基板
１８ エミッタ端子
１９ ゲート端子
２０ コレクタ端子
２１ 銅ベース
２２ プラスチックケース
２３ 絶縁層
２４、２５ リードフレーム[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a module structure such as an IGBT (insulated gate bipolar transistor) module and a method for manufacturing the same.
[0002]
[Prior art]
As shown in FIG. 8, a power semiconductor device (semiconductor device) such as an IGBT module is usually provided on a copper wiring 65 formed on a wiring substrate 66 on a semiconductor chip 51 (hereinafter referred to as a chip) such as an IGBT chip shown in FIG. The main electrode 54 and the gate electrode 55, which are the front electrodes of the chip 51, are bonded to each other by bonding one or a plurality of aluminum wires 73 and 74 to the emitter terminal 68 and the gate. Each is connected to an external lead-out terminal which is a terminal 69. Usually, a plurality of chips 51 are housed in a package.
[0003]
[Problems to be solved by the invention]
The aluminum wire bonding has the following problems.
1) As the chip capacity increases, the number of wires required to secure the necessary current capacity increases, and the man-hours for bonding and wire bonder increase, resulting in higher costs.
2) It is structurally difficult to ensure a sufficient cross-sectional area of the copper wiring pattern on the wire 73 and the wiring board, and as a result, problems arise in heat generation of the element and response characteristics due to an increase in wiring resistance and wiring inductance. There is.
3) Even if an attempt is made to increase the diameter of the wire 73 used to reduce the number of wires 73, the bonding condition for bonding the thick wire becomes strict and the chip may be damaged, so there is a limit to increasing the thickness.
[0004]
In order to solve these problems, a structure in which copper lead frames 68 and 69 are directly bonded to the main electrode 54 and the control electrode 55 of the chip 51 as shown in FIG. ing.
However, when the lead frames 68 and 69 are connected to the main electrode of the chip as shown in FIG. 9, the lead frames 68 and 69 have a circle 74 in order to relieve the stress generated in the chip 51 by the lead frames 68 and 69. As shown in the figure, it is necessary to have a complicated structure, which increases the manufacturing cost. The reason for this complicated structure is that the lead frames 68 and 69 have flexibility.
[0005]
Also, if the copper wiring formed on the printed circuit board is joined directly to the main electrode or control electrode on the chip surface with solder or the like, the solder spreads in the lateral direction and the distance between the chip surface and the printed circuit board becomes extremely short. As a result, the electrical insulation between the main electrode formed on the chip surface and the control electrode, and the electrical insulation between the copper wiring connected to the main electrode and the control electrode and the withstand voltage structure (such as a guard ring) are reduced. .
[0006]
The object of the present invention is to solve the above-mentioned problems, at low cost, and to have good electrical insulation between the main electrode and the control electrode, and between the main electrode and the copper wiring connected to the control electrode and the pressure-resistant structure. And a method of manufacturing the same semiconductor device.
[0007]
[Means for Solving the Problems]
To achieve the above object, a main electrode and a control electrode formed on the same plane of a semiconductor chip, a breakdown voltage structure formed on the semiconductor chip, a first external lead conductor connected to the main electrode, and the control In a module-structured semiconductor device comprising a second external lead conductor connected to an electrode,
An insulating film is formed on the entire surface of the semiconductor chip and is opened on the main electrode and the control electrode, and is formed on the insulating film by being fixed to the main electrode through a fixing material at the opening of the insulating film. A first external lead conductor, and a second external lead conductor fixed to the control electrode and formed on the insulating film.
[0008]
The insulating film may be an organic insulating film.
The insulating film may have a thickness of 50 to 100 μm.
The first and second external lead conductors may be leads of a lead frame or a printed circuit board.
The fixing material may be solder or solder paste.
[0009]
In addition, a main electrode and a control electrode formed on the same plane of the semiconductor chip, a breakdown voltage structure formed in the semiconductor chip, a first external lead conductor connected to the main electrode, and a second external connected to the control electrode In a manufacturing method of a semiconductor device having a module structure comprising a lead-out conductor,
Forming a main electrode and a control electrode on a semiconductor wafer having a breakdown voltage structure and an active region; forming an insulating film having openings on the entire surface of the semiconductor wafer; a step of chips by cutting the wafer, and a main electrode and a control electrode formed on said chip semiconductor chip, a first outer lead conductor,, respectively Re its at fixing material to the second external lead conductors secured The manufacturing method including the process to do.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
1 to 3 show a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a plan view of a semiconductor chip, FIG. 2 is a plan view of an insulating sheet, and FIG. .
1 to 3, an insulating sheet 6 provided with openings 7 and 8 at positions located on the emitter electrode 4 and the gate electrode 5 shown in FIG. 2 is pasted on the IGBT chip 1 shown in FIG. 1. To do. Solder 9, 10 (solder paste, etc.), which is a fixing material, is attached on the emitter electrode 4 and the gate electrode 5 located in the openings 7 and 8 of the insulating sheet so as to be slightly higher than the thickness of the insulating sheet. Copper wirings 11 and 12 (corresponding to first and second external lead-out conductors) formed on the surface of the substrate 13 are fixed to the emitter electrode 4 and the gate electrode 5 via solders 9 and 10. The back surface of the IGBT chip is fixed to the copper wiring 15 formed on the surface of the wiring substrate 16 via the solder 17. The wiring board 16 and the copper base 21 (cooling conductor) are fixed with solder 17. The copper wirings 11, 12 and 15 are fixed to the emitter terminal 18, the gate terminal 19 and the collector terminal 18, and the plastic case 22 is fixed to the copper base 21. The wiring board 13 and the copper wirings 11 and 12 constitute a wiring circuit board (such as a Direct Bonding Copper board).
[0011]
The main purpose of the insulating sheet over DOO 6, since it is to ensure the electrical insulation between the guard ring 3 provided on the copper wiring 11, 12 and the IGBT chip peripheral portion is externally drawn body, while It must be able to withstand the electric field applied to the battery without long-term deterioration. Usually, the voltage during this period is several tens of volts to several kV, and therefore an insulation thickness corresponding to the rating of the element may be selected. When a polyimide resin film is used as the organic insulating film, the withstand voltage is usually about 100 kV / mm or the like, and only needs to have a thickness of about 50 μm.
[0012]
However, the actual thickness of the insulating film should be determined in consideration of the availability and workability of the film, and is practically about 50 to 100 μm. When the thickness exceeds 100 μm, the film material has poor processability and is expensive, and it is difficult to obtain a film thickness exceeding 100 μm by a coating method. Moreover, when it is less than 50 μm, there is a possibility that sufficient electrical insulation reliability cannot be obtained.
[0013]
Accordingly, the material of the insulating sheet 6 is preferably a polyimide resin sheet having a thickness of 50 μm to 100 μm, but the thickness is not limited to this. Also, the resin material is not limited to polyimide resin, and organic insulating materials such as engineering plastic resin sheets such as polyethylene terephthalate resin, polyether ether ketone resin, polyether imide resin, polysulfone resin, etc., depending on the required heat resistance temperature and dielectric strength Can be used.
[0014]
In addition, it is desirable to use an adhesive that can be heat-sealable in the process or use the heat-sealability of the sheet itself. However, a thermosetting adhesive may also be used.
The presence of the insulating sheet 6 ensures insulation between the main electrode that is the emitter electrode and the control electrode that is the gate electrode.
Further, since the insulating sheet 6 has a structure bonded directly above the guard ring portion, the copper wiring 11 fixed to the emitter electrode 4 and the guard ring 3 which is a withstand voltage structure are insulated by the insulating sheet 6. Yes.
[0015]
As described above, by sticking the insulating sheet 6 provided with the openings 7 and 8 to the surface of the IGBT chip 1, it is possible to prevent the solder 9 and 10 from spreading in the lateral direction, and the main electrode which is the emitter electrode 4. And the electrical insulation between the control electrode which is the gate electrode 5 can be ensured reliably. In addition, the insulating sheet 6 can ensure electrical insulation between the copper wirings 11 and 12 connected to the emitter electrode 4 and the gate electrode 5 and the guard ring 3 which is a withstand voltage structure.
[0016]
The dimensions of the openings 7 and 8 are for joining the main electrode and the control electrode to the external lead-out conductor, respectively, and may be any opening area corresponding to the area of the main electrode and the control electrode. Practically, the opening area is preferably 30 to 100% of the main electrode and control electrode area. In the case where the main electrode is divided into a plurality of cells, the main electrode opening may be a plurality of openings corresponding to each cell.
[0017]
In addition, the structure of the copper wirings 11 and 12 that are the external lead-out conductors can be a simple flat plate (conventionally has a complicated bent structure as shown by a circle 72 in FIG. 9).
Thus, the manufacturing cost can be reduced by simplifying the shapes of the copper wirings 11 and 12 which are the external lead-out conductors.
FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. The difference from the first embodiment is not a structure in which an insulator such as an insulating sheet 6 is adhered, but a thick insulating layer 23 is formed in other portions except the emitter electrode 4 and the gate electrode 5. It is. The material of the insulating layer 23 may be any curable resin (organic insulating material) that can be patterned on the surface of the IGBT chip 1, but preferably heat resistant heat such as epoxy resin, polyimide resin, bismaleimide resin, etc. Curable resin is good.
[0018]
This pattern can be formed by screen printing, spin coating, vacuum printing, or the like.
Also, if the openings 7 of the emitter electrode 4 are not single but a plurality of openings are made for one emitter electrode 4, stress such as thermal stress applied to the joint portion with the solder 9 is relieved. can do.
[0019]
In addition, when a liquid insulating material is used in forming the insulating layer 23, when a plurality of openings are provided, the degree of freedom of the planar pattern of the openings is improved. Of course, a plurality of openings 8 of the gate electrode 5 may be formed.
According to the present invention, as in the first embodiment, the insulation between the emitter electrode 4 and the gate electrode 5 and the distance between the copper wirings 11 and 12 connected to the emitter electrode 4 and the gate electrode 5 and the guard ring 3 are low. It is possible to reliably ensure the insulation.
[0020]
FIG. 5 shows a method of manufacturing a semiconductor device according to a third embodiment of the present invention. FIGS. 5A to 5D are process cross-sectional views shown in the order of processes. This is a method of manufacturing the semiconductor device of FIG.
An insulating layer 23 in which the emitter electrode and the gate electrode are exposed is formed on the surface on the emitter electrode side of the wafer 100 on which a large number of IGBT units in which the p-type diffusion region and the n-type diffusion region are formed are integrated (FIG. 1A).
[0021]
Next, in order to obtain an IGBT chip, the wafer 100 is cut along the cutting line 24 ((b) in the figure).
Next, the openings 9 and 10 are filled with solder 9 and 10 (FIG. 3C).
Next, an emitter electrode and a gate electrode (not shown) and the copper wirings 11 and 12 formed on the wiring board 13 are fixed through solders 9 and 10. On the other hand, the back surface of the IGBT chip 1 is also fixed to the copper wiring 15 formed on the wiring board 16 via solder (not shown) ((d) in the figure).
[0022]
Next, as shown in FIG. 4, the copper base 21, the emitter terminal 18, the gate terminal 19, and the collector terminal 20 are fixed, and a plastic case 22 is covered to obtain a semiconductor device.
Thus, by forming the insulating layer 23 in a lump in the wafer state before cutting the chip, the cost for forming the insulating layer 23 can be greatly reduced. The insulating layer 23 is formed by the method described with reference to FIG. Furthermore, there is also a method in which the insulating sheet 13 shown in FIG.
[0023]
FIG. 6 is a cross-sectional view of the main part of the semiconductor device according to the fourth embodiment of the present invention. The difference from the above embodiment is that a conductor such as a lead frame is used instead of the copper wiring formed on the wiring board. FIG. 6 is a cross-sectional view of the main part corresponding to FIG. In this case, since the lead frames 24 and 25 (corresponding to the first and second outer lead-out conductors) are arranged on the insulating sheet 6, the thickness of the lead frames 24 and 25 can be made extremely thin. Therefore, a flat lead frame may be used instead of the bent complicated structure as shown in FIG. 9, and the cost can be reduced. In addition, the insulation between the main electrode and the control electrode and the insulation between the main electrode, the control electrode and the pressure-resistant structure can be ensured.
[0024]
【The invention's effect】
According to this invention, the main electrode and the control electrode are electrically connected to the external lead-out conductor through the opening of the insulating film formed on the semiconductor chip, and the external lead-out conductor is formed on the insulating film. The insulation between the main electrode and the control electrode and the insulation between the external lead conductor connected to the main electrode and the control electrode and the pressure resistant structure can be easily ensured.
[0025]
In addition, since the thin outer lead conductor is formed on the insulating film, the shape of the outer lead conductor can be simplified, and the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor chip of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view of an insulating sheet of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a fragmentary cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a method of manufacturing a semiconductor device according to a third embodiment of the present invention. ) To (d) are cross-sectional views of the steps shown in the order of the steps. FIG. 6 is a cross-sectional view of the main part of the semiconductor device according to the fourth embodiment of the present invention. Cross-sectional view of relevant parts [FIG. 9] Cross-sectional view of relevant parts of another conventional semiconductor device [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 IGBT chip | tip 2 Active region 3 Guard ring 4 Emitter electrode 5 Gate electrode 6 Insulation sheet 7, 8 Opening 9, 10, 14, 17 Solder 11, 12, 15 Copper wiring 13, 16 Wiring board 18 Emitter terminal 19 Gate terminal 20 Collector terminal 21 Copper base 22 Plastic case 23 Insulating layers 24 and 25 Lead frame

Claims (6)

半導体チップの同一平面上に形成した主電極と制御電極と、前記半導体チップに形成した耐圧構造と、前記主電極と接続する第１外部導出導体と、前記制御電極と接続する第２外部導出導体とを具備するモジュール構造の半導体装置において、
半導体チップ上の前記耐圧構造直上部を覆い主電極と制御電極がある箇所がそれぞれ開口され、厚さが５０μｍ〜１００μｍである有機絶縁膜と、前記主電極と制御電極の面積に相当する面積を有する前記有機絶縁膜の開口部と、前記開口部で、該有機絶縁膜の膜厚より高く付着させた固着材を介して、前記主電極と固着し、前記有機絶縁膜上に形成される第１外部導出導体と、前記制御電極と固着し、前記絶縁膜上に形成される第２外部導出導体とを有することを特徴とする半導体装置。A main electrode and a control electrode formed on the same plane of the semiconductor chip, a breakdown voltage structure formed on the semiconductor chip, a first external lead conductor connected to the main electrode, and a second external lead conductor connected to the control electrode In a module-structured semiconductor device comprising:
Is the pressure-resistant structure directly above the cover there is a main electrode and a control electrode portions each opening on a semiconductor chip, and the organic insulating film is a thickness of 50 .mu.m to 100 .mu.m, the area corresponding to the area of the main electrode and the control electrode The organic insulating film has an opening, and the opening is formed on the organic insulating film by being fixed to the main electrode through a fixing material attached to the opening higher than the thickness of the organic insulating film. 1. A semiconductor device comprising: an outer lead conductor; and a second outer lead conductor fixed to the control electrode and formed on the insulating film. 前記有機絶縁膜は、あらかじめ前記開口が形成された樹脂シートであることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the organic insulating film is a resin sheet in which the opening is formed in advance. 前記有機絶縁膜は、前記開口をパターン形成できる硬化性樹脂であることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the organic insulating film is a curable resin capable of patterning the opening. 前記、第１および第２外部導出導体が、リードフレームもしくは配線回路基板の配線であることを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the first and second outer lead-out conductors are leads of a lead frame or a printed circuit board. 前記固着材が、ハンダもしくはハンダペーストであることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the fixing material is solder or solder paste. 半導体チップの同一平面上に形成した主電極と制御電極と、前記半導体チップに形成した耐圧構造と、前記主電極と接続する第１外部導出導体と、前記制御電極と接続する第２外部導出導体とを具備するモジュール構造の半導体装置の製造方法において、
耐圧構造と活性領域を形成した半導体ウエハ上に主電極と制御電極とを形成する工程と、半導体ウエハ上の前記耐圧構造直上部を覆い主電極と制御電極がある箇所がそれぞれ前記主電極と制御電極の面積に相当する面積で開口され、厚さが５０μｍ〜１００μｍである有機絶縁膜を形成する工程と、該半導体ウエハを切断してチップ化する工程と、該チップ化された半導体チップに形成された主電極と制御電極上の前記開口に、前記有機絶縁膜の膜厚より高く固着剤を付着させ、第１外部導出導体、第２外部導出導体に固着材でそれぞれ固着する工程とを含むことを特徴とする半導体装置の製造方法。A main electrode and a control electrode formed on the same plane of the semiconductor chip, a breakdown voltage structure formed on the semiconductor chip, a first external lead conductor connected to the main electrode, and a second external lead conductor connected to the control electrode In a manufacturing method of a semiconductor device having a module structure comprising:
A step of forming a main electrode and a control electrode on a semiconductor wafer on which a breakdown voltage structure and an active region are formed, and a portion where the main electrode and the control electrode are located on the semiconductor wafer and directly cover the breakdown voltage structure; Forming an organic insulating film having an area corresponding to the area of the electrode and having a thickness of 50 μm to 100 μm; cutting the semiconductor wafer into chips; and forming the chip on the semiconductor chip And a step of adhering a fixing agent to the opening on the main electrode and the control electrode which is higher than the thickness of the organic insulating film and fixing the first outer lead conductor and the second outer lead conductor with a fixing material. A method for manufacturing a semiconductor device.
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