JP2002026246A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2002026246A JP2002026246A JP2000199626A JP2000199626A JP2002026246A JP 2002026246 A JP2002026246 A JP 2002026246A JP 2000199626 A JP2000199626 A JP 2000199626A JP 2000199626 A JP2000199626 A JP 2000199626A JP 2002026246 A JP2002026246 A JP 2002026246A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- connection terminal
- terminal
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体装置に関
するもので、特に大電力用の半導体装置のボンディング
技術に係る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bonding technique for a high power semiconductor device.
【０００２】[0002]
【従来の技術】従来の半導体素子のモジュールにおい
て、半導体素子、この半導体素子を実装した実装基板、
及び外部電力端子等の相互間の接続はワイヤボンディン
グによって行われている。そして、特に大電力用半導体
素子のモジュールでは定格電流の増加に伴い、ボンディ
ングワイヤの電流容量の確保が重要となっている。2. Description of the Related Art In a conventional semiconductor device module, a semiconductor device, a mounting board on which the semiconductor device is mounted,
The connection between the external power terminals and the like is performed by wire bonding. In particular, with the increase in the rated current, it is important to secure the current capacity of the bonding wire in the module of the high power semiconductor element.
【０００３】従来の大電力用半導体素子のモジュールの
一例としてＩＧＢＴを例に挙げて説明する。図１２は従
来のＩＧＢＴモジュールの断面図である。An IGBT will be described as an example of a conventional high power semiconductor device module. FIG. 12 is a sectional view of a conventional IGBT module.
【０００４】図示するように、放熱板１００上には導電
性部材１２０−１を介して実装基板１１０が設けられ、
この実装基板１１０上に、ＩＧＢＴの形成された半導体
チップ１３０、１３０が、パターニングされた導体パタ
ーン１２０−２を介して搭載されている。また、実装基
板１１０上には導体パターン１２０−２と分離された導
体パターン１２０−３が設けられている。更に、放熱板
１００の端部には外部電力端子１６０−１〜３が設けら
れている。そして、導体パターン１２０−３と外部入力
端子１６０−２間、導体パターン１２０−３と半導体チ
ップ１３０間、及び半導体チップ１３０同士がボンディ
ングワイヤ１４０によって電気的に接続されている。ボ
ンディングワイヤ１４０には通常Ａｌが用いられる。Ａ
ｌは室温（２５℃）において電気抵抗率が２．７４μΩ
・ｃｍであり、非常に良好な電気伝導性の得られる材料
である。そして、全体を絶縁樹脂１９０が被覆すること
によりＩＧＢＴモジュールが構成されている。As shown in the figure, a mounting board 110 is provided on a heat sink 100 via a conductive member 120-1.
On this mounting substrate 110, semiconductor chips 130, 130 on which IGBTs are formed are mounted via patterned conductor patterns 120-2. Further, on the mounting substrate 110, a conductor pattern 120-3 separated from the conductor pattern 120-2 is provided. Further, external power terminals 160-1 to 160-3 are provided at the end of the heat sink 100. Then, between the conductor pattern 120-3 and the external input terminal 160-2, between the conductor pattern 120-3 and the semiconductor chip 130, and between the semiconductor chips 130 are electrically connected by bonding wires 140. Al is usually used for the bonding wire 140. A
1 has an electric resistivity of 2.74 μΩ at room temperature (25 ° C.)
Cm, a material with very good electrical conductivity. The IGBT module is formed by covering the whole with the insulating resin 190.
【０００５】しかしボンディングワイヤはその断面積に
より電流容量が制限される。そのためＩＧＢＴモジュー
ルの定格電流の増加に伴いボンディングワイヤ数を増や
す必要がある。すなわち、ワイヤボンディング工程が増
加して製造コストが上昇するという問題があった。However, the current capacity of a bonding wire is limited by its cross-sectional area. Therefore, it is necessary to increase the number of bonding wires as the rated current of the IGBT module increases. That is, there is a problem in that the number of wire bonding steps increases and the manufacturing cost increases.
【０００６】[0006]
【発明が解決しようとする課題】上記従来の大電力用半
導体素子のモジュールにおいては、電気的な接続はワイ
ヤボンディングによって行われている。このボンディン
グワイヤには通常、低抵抗材料であるＡｌが使用されて
おり、良好な電気伝導性が得られている。In the above-mentioned conventional high power semiconductor device module, electrical connection is made by wire bonding. Normally, Al, which is a low-resistance material, is used for this bonding wire, and good electrical conductivity is obtained.
【０００７】しかし、ボンディングワイヤはその断面積
により電流容量が制限される。そのためＩＧＢＴモジュ
ールの定格電流の増加に伴いボンディングワイヤ数を増
やす必要があり、工程が増加して製造コストが上昇する
という問題があった。However, the current capacity of the bonding wire is limited by its cross-sectional area. Therefore, it is necessary to increase the number of bonding wires with an increase in the rated current of the IGBT module, and there is a problem that the number of processes is increased and the manufacturing cost is increased.
【０００８】この発明は、上記事情に鑑みてなされたも
ので、その目的は、ワイヤボンディング工程を増やすこ
となく定格電流の増加に対応出来ることにより、製造工
程の負担を軽減して製造コストを低減できる半導体装置
を提供することにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to be able to cope with an increase in the rated current without increasing the wire bonding process, thereby reducing the load on the manufacturing process and reducing the manufacturing cost. It is an object of the present invention to provide a possible semiconductor device.
【０００９】[0009]
【課題を解決するための手段】この発明の請求項１記載
の半導体装置は、半導体素子が実装された実装基板と、
外部との電力の授受を行うための外部端子と、前記実装
基板と前記外部端子との間を電気的に接続し、前記半導
体素子の消費電力に十分な電力容量を有するリードフレ
ームとを具備することを特徴としている。According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a mounting board on which a semiconductor element is mounted;
An external terminal for transmitting and receiving electric power to and from the outside, and a lead frame that electrically connects the mounting substrate and the external terminal and has a power capacity sufficient for power consumption of the semiconductor element. It is characterized by:
【００１０】請求項２に記載したように、請求項１記載
の半導体装置において、前記リードフレームは、主とし
てＡｌと実質的に等しい若しくはＡｌ以下の電気抵抗率
を有する材質からなることを特徴としている。According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the lead frame is mainly made of a material having an electrical resistivity substantially equal to or less than Al. .
【００１１】請求項３に記載したように、請求項１また
は２記載の半導体装置において、前記リードフレーム
は、隣接するリードフレームと平行に、且つ電流が逆向
き流れるようにして近接配置されていることを特徴とし
ている。According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the lead frame is disposed in parallel with an adjacent lead frame and in close proximity so that a current flows in the opposite direction. It is characterized by:
【００１２】請求項４に記載したように、請求項１乃至
３いずれか１項記載の半導体装置において、前記実装基
板上に設けられ、前記半導体素子と電気的に接続される
接続端子を更に備え、前記接続端子と前記外部端子とが
前記リードフレームにより接続され、前記接続端子と前
記リードフレームとは溶接接合されていることを特徴と
している。According to a fourth aspect, in the semiconductor device according to any one of the first to third aspects, the semiconductor device further includes a connection terminal provided on the mounting substrate and electrically connected to the semiconductor element. The connection terminal and the external terminal are connected by the lead frame, and the connection terminal and the lead frame are welded to each other.
【００１３】請求項５に記載したように、請求項１乃至
３いずれか１項記載の半導体装置において、前記実装基
板上に設けられ、前記半導体素子と電気的に接続され、
一部が接続端子を構成する導電性部材を更に備え、前記
接続端子と前記外部端子とが前記リードフレームにより
接続され、前記接続端子と前記リードフレームとは溶接
接合されていることを特徴としている。According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the semiconductor device is provided on the mounting substrate and is electrically connected to the semiconductor element.
It further comprises a conductive member partially forming a connection terminal, wherein the connection terminal and the external terminal are connected by the lead frame, and the connection terminal and the lead frame are welded and joined. .
【００１４】請求項６に記載したように、請求項４記載
の半導体装置において、前記接続端子は、前記実装基板
に少なくともＡｌより低抵抗の材料によりロー付けされ
ていることを特徴としている。According to a sixth aspect of the present invention, in the semiconductor device according to the fourth aspect, the connection terminal is soldered to the mounting substrate with at least a material having a resistance lower than that of Al.
【００１５】請求項７に記載したように、請求項４乃至
６いずれか１項記載の半導体装置において、前記接続端
子は、少なくとも前記リードフレームと接触する領域に
設けられた錫または半田による皮膜を有することを特徴
としている。According to a seventh aspect of the present invention, in the semiconductor device according to any one of the fourth to sixth aspects, the connection terminal is formed of a film made of tin or solder provided at least in a region in contact with the lead frame. It is characterized by having.
【００１６】請求項８に記載したように、請求項１乃至
７いずれか１項記載の半導体装置において、異なる電位
を有する複数の前記リードフレームの少なくとも一部領
域はモールド樹脂により絶縁されていることを特徴とし
ている。According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to seventh aspects, at least a part of the plurality of lead frames having different potentials is insulated by a mold resin. It is characterized by.
【００１７】請求項９に記載したように、請求項８記載
の半導体装置において、前記絶縁基板上に設けられ、前
記実装基板及び半導体素子をモールドする絶縁樹脂を更
に備え、前記リードフレーム及び前記接続端子の少なく
とも一部は前記絶縁樹脂上に露出していることを特徴と
している。According to a ninth aspect of the present invention, the semiconductor device according to the eighth aspect further comprises an insulating resin provided on the insulating substrate for molding the mounting substrate and the semiconductor element, wherein the lead frame and the connection are provided. At least a part of the terminal is exposed on the insulating resin.
【００１８】請求項１０に記載したように、請求項１乃
至９いずれか１項記載の半導体装置において、前記リー
ドフレームは、少なくとも一部領域に波状の断面構造を
有する機械的緩衝構造であることを特徴としている。According to a tenth aspect of the present invention, in the semiconductor device according to any one of the first to ninth aspects, the lead frame has a mechanical buffer structure having a wavy cross-sectional structure in at least a partial region. It is characterized by.
【００１９】請求項１のような構造によれば、半導体素
子モジュール等において実装基板と外部端子との間の接
続をリードフレームにより行っている。そのため、半導
体素子の定格電流が増加しても、その電流容量に十分な
リードフレームを用いることにより対応できる。すなわ
ち、従来のワイヤボンディングでは、その電流容量がボ
ンディングワイヤの断面積により制限を受けるため、定
格電流の増加に伴いボンディングワイヤの使用数が増大
し、ワイヤボンディング工程が増加するという問題が生
じていた。しかし、十分な電気容量をもつリードフレー
ムを用いることで工程数を増やすことなくボンディング
を行うことが出来るので、半導体装置の製造コストを抑
えつつ信頼性及び性能を向上できる。According to the structure of the first aspect, the connection between the mounting board and the external terminals is made by the lead frame in the semiconductor element module or the like. Therefore, even if the rated current of the semiconductor element increases, it can be dealt with by using a lead frame sufficient for the current capacity. That is, in the conventional wire bonding, since the current capacity is limited by the cross-sectional area of the bonding wire, the number of bonding wires used increases with an increase in the rated current, and the problem that the wire bonding process increases. . However, by using a lead frame having a sufficient electric capacity, bonding can be performed without increasing the number of steps, so that reliability and performance can be improved while suppressing the manufacturing cost of the semiconductor device.
【００２０】請求項２のように、リードフレームにはＡ
ｌと実質的に等しい若しくはＡｌ以下の電気抵抗率を有
する材料を用いることで、ワイヤボンディングと同等若
しくはそれ以上の電気的特性を得ることが出来る。As described in claim 2, the lead frame has A
By using a material having an electrical resistivity substantially equal to 1 or less than Al, it is possible to obtain electrical characteristics equivalent to or better than wire bonding.
【００２１】請求項３のように、隣接するリードフレー
ム同士を平行に且つ電流の流れる向きが逆になるよう近
接配置することにより、寄生インダクタンスを抑制し、
電気的特性を向上できる。According to a third aspect of the present invention, the parasitic inductance is suppressed by arranging adjacent lead frames in parallel and close to each other so that the current flows in opposite directions.
Electrical characteristics can be improved.
【００２２】請求項４のように、実装基板上に接続端子
を設け、この接続端子とリードフレームとの溶接接合で
実装基板と外部端子とを電気的に接続することにより、
半導体装置の電気的特性及び信頼性を向上できる。According to a fourth aspect of the present invention, a connection terminal is provided on the mounting board, and the mounting board and the external terminal are electrically connected by welding the connection terminal and the lead frame.
The electrical characteristics and reliability of the semiconductor device can be improved.
【００２３】請求項５のように、接続端子は実装基板上
に設けた導電性部材により形成してもよく、この場合に
は更に半導体装置の製造工程を簡略化できる。The connection terminal may be formed by a conductive member provided on the mounting substrate. In this case, the manufacturing process of the semiconductor device can be further simplified.
【００２４】請求項６、７のように、接続端子を実装基
板にロー付けにより接続し、または接続端子のリードフ
レームと接触する領域に錫、半田などの皮膜を設けるこ
とにより、実装基板と外部端子との間の接触抵抗を軽減
し、電気的特性を向上できる。According to the sixth and seventh aspects, the connection terminal is connected to the mounting board by brazing, or a coating of tin, solder, or the like is provided on a region of the connection terminal which comes into contact with the lead frame, so that the mounting terminal is connected to the outside. The contact resistance between the terminals can be reduced, and the electrical characteristics can be improved.
【００２５】請求項８のように、複数のリードフレーム
の少なくとも一部を樹脂によりモールドすることによ
り、複数のリードフレームを部品として絶縁を保ちつつ
一体化でき、組み立て精度を向上できると共に、製造工
程を簡略化できる。By molding at least a part of the plurality of lead frames with resin as in claim 8, the plurality of lead frames can be integrated as a component while maintaining insulation, and the assembling accuracy can be improved and the manufacturing process can be improved. Can be simplified.
【００２６】請求項９のように、リードフレームの少な
くとも一部を樹脂によりモールドすることで、半導体素
子や実装基板をモールドする絶縁樹脂はそれらが十分に
絶縁される最低限の量に抑えることが出来る。すなわ
ち、リードフレーム全体を樹脂で多う必要がないため、
絶縁樹脂の使用量を低減でき、製造コストを削減でき
る。According to a ninth aspect of the present invention, at least a part of the lead frame is molded with a resin, so that the insulating resin for molding the semiconductor element and the mounting substrate can be suppressed to a minimum amount that can sufficiently insulate them. I can do it. That is, there is no need to fill the entire lead frame with resin,
The amount of the insulating resin used can be reduced, and the manufacturing cost can be reduced.
【００２７】請求項１０のように、リードフレームの特
に樹脂によりモールドされない領域の少なくとも一部に
機械的緩衝構造を設けることで、リードフレームの熱膨
張による悪影響を回避でき、半導体装置の信頼性を向上
できる。According to the tenth aspect, by providing a mechanical buffer structure in at least a part of a region of the lead frame which is not molded with resin, adverse effects due to thermal expansion of the lead frame can be avoided, and reliability of the semiconductor device can be reduced. Can be improved.
【００２８】[0028]
【発明の実施の形態】以下、この発明の実施形態を図面
を参照して説明する。この説明に際し、全図にわたり、
共通する部分には共通する参照符号を付す。Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.
【００２９】この発明の第１の実施形態に係る半導体装
置について、ＩＧＢＴモジュールを例に挙げて説明す
る。図１はＩＧＢＴモジュールの断面図である。The semiconductor device according to the first embodiment of the present invention will be described using an IGBT module as an example. FIG. 1 is a sectional view of the IGBT module.
【００３０】図示するように、放熱板１０上にはＡｌＮ
あるいはＳｉＮ等のセラミック板１１（実装基板）が搭
載されている。この実装基板１１の裏面には、室温（２
５℃）における電気抵抗率が１．７０μΩ・ｃｍのＣ
ｕ、あるいはＡｌといった金属等の導電性部材１２−１
が半田によって接続されている。また実装基板１１の表
面にも上記導電性部材が設けられており、この導電性部
材はいくつかの導体パターン１２−２、１２−３にパタ
ーニングされている。そして導体パターン１２−２上
に、ＩＧＢＴ等の半導体素子の形成された半導体チップ
１３、１３が実装されている。通常、ＩＧＢＴはその主
表面にエミッタ領域が形成され、裏面（半導体基板）に
コレクタ領域が形成される。そのためＩＧＢＴのエミッ
タ領域とのコンタクトを取るために、半導体チップ１３
の主表面と導体パターン１２−３との間はボンディング
ワイヤ１４によって接続されている。また導体パターン
１２−２、１２−３上には、例えばＣｕやＡｌと同等以
上の低電気抵抗率の金属あるいは金属複合材からなるコ
レクタ接続端子１５−１、エミッタ接続端子１５−２が
それぞれ設けられている。放熱板１０の端部にはモジュ
ール外部と電力の授受を行う外部電力端子１６−１〜３
が設けられ、外部電力端子１６−１、１６−２には、例
えばＣｕやＡｌと同等以上の低電気抵抗率の金属あるい
は金属複合材からなるコレクタ外部出力端子１７−１、
エミッタ外部出力端子１７−２がそれぞれ設けられてい
る。そしてコレクタ接続端子１５−１、エミッタ接続端
子１５―２はそれぞれコレクタリードフレーム１８−
１、エミッタリードフレーム１８−２によりコレクタ外
部出力端子１７−１、エミッタ外部出力端子１７−２
に、溶接接合により電気的に接続されている。更に、全
体をシリコーンゲル等の絶縁樹脂１９が覆うことにより
ＩＧＢＴモジュールが構成されている。なお、図のよう
にリードフレーム１８−１、１８−２は平行に且つ両リ
ードフレームに流れる電流の向きが逆になるようにして
近接配置される。As shown in FIG.
Alternatively, a ceramic plate 11 (mounting substrate) such as SiN is mounted. The rear surface of the mounting substrate 11 has a room temperature (2
5 ° C.) with an electric resistivity of 1.70 μΩ · cm
conductive member 12-1 such as a metal such as u or Al
Are connected by solder. The conductive member is also provided on the surface of the mounting board 11, and the conductive member is patterned into several conductor patterns 12-2 and 12-3. On the conductor pattern 12-2, semiconductor chips 13, 13 on which semiconductor elements such as IGBTs are formed are mounted. Usually, an IGBT has an emitter region formed on its main surface and a collector region formed on its back surface (semiconductor substrate). Therefore, in order to make contact with the emitter region of the IGBT, the semiconductor chip 13
Is connected by a bonding wire 14 to the conductor pattern 12-3. On the conductor patterns 12-2 and 12-3, a collector connection terminal 15-1 and an emitter connection terminal 15-2 made of a metal or a metal composite material having a low electrical resistivity equal to or higher than Cu or Al are provided, for example. Have been. External power terminals 16-1 to 3-3 for exchanging power with the outside of the module are provided at the ends of the heat sink 10.
The external power terminals 16-1 and 16-2 are provided with a collector external output terminal 17-1 made of a metal or a metal composite material having a low electrical resistivity equal to or higher than Cu or Al, for example.
An emitter external output terminal 17-2 is provided. The collector connection terminal 15-1 and the emitter connection terminal 15-2 are connected to the collector lead frame 18-, respectively.
1. The collector external output terminal 17-1 and the emitter external output terminal 17-2 by the emitter lead frame 18-2.
Are electrically connected by welding. Furthermore, the IGBT module is configured by covering the whole with an insulating resin 19 such as silicone gel. As shown in the drawing, the lead frames 18-1 and 18-2 are arranged close to each other in parallel and in such a manner that the directions of the currents flowing through both lead frames are reversed.
【００３１】図２は上記ＩＧＢＴモジュールの一部斜視
図であり、図１における特にコレクタ、エミッタ接続端
子１５−１、１５−２の構造を示しており、図３はリー
ドフレームと各端子との接合部分の拡大断面図である。FIG. 2 is a partial perspective view of the IGBT module, particularly showing the structure of the collector and emitter connection terminals 15-1 and 15-2 in FIG. 1. FIG. 3 shows the connection between the lead frame and each terminal. It is an expanded sectional view of a junction part.
【００３２】図２に示すように、導体パターン１２−
２、１２−３上にはそれぞれＬ字型をしたコレクタ接続
端子１５−１、エミッタ接続端子１５−２がそれぞれ設
けられているが、当然ながら導体パターン１２−２、１
２−３とコレクタ、エミッタ接続端子１５−１、１５−
２との間には接触抵抗が発生する。そのため、図３に示
すように、例えば電気抵抗率が１．６１μΩ・ｃｍのＡ
ｇ等の低電気抵抗率の金属２０によるロー付けで接続端
子１５を導体パターン１２上に接合している。また、こ
のロー付けに影響を及ぼさない範囲で、接続端子１５、
リードフレーム１８、及び出力端子１７の表面に、Ｓ
ｎ、半田といった金属の皮膜２１設けることにより、接
触面積を拡大させている。As shown in FIG. 2, the conductor pattern 12-
An L-shaped collector connection terminal 15-1 and an emitter connection terminal 15-2 are provided on each of the conductor patterns 12-2 and 12-3.
2-3 and collector and emitter connection terminals 15-1, 15-
A contact resistance is generated between the two. Therefore, as shown in FIG. 3, for example, A having an electrical resistivity of 1.61 μΩ · cm
The connection terminal 15 is joined to the conductor pattern 12 by brazing with a metal 20 having a low electrical resistivity such as g. In addition, as long as this does not affect the brazing, the connection terminals 15,
On the surfaces of the lead frame 18 and the output terminal 17, S
The contact area is increased by providing a metal film 21 such as n or solder.
【００３３】上記第１の実施形態によれば、従来ワイヤ
ボンディングにより行っていた外部端子と半導体チップ
との電気的な接続を、リードフレームを用いた溶接接合
により行っている。そのため、ＩＧＢＴ等の半導体素子
の定格電流が増加しても、その電流容量に十分なリード
フレームを用いることにより対応できる。すなわち、従
来のＡｌワイヤを用いたワイヤボンディングでは、その
電流容量がＡｌワイヤの断面積により制限を受けるた
め、定格電流の増加に伴いボンディングワイヤの使用数
が増大し、ワイヤボンディング工程が増加するという問
題が生じていた。しかし、本実施形態のようにリードフ
レームを用いることで工程数を増やすことなく十分な電
気容量をもつリードフレームにてボンディングを行うこ
とが出来るので、半導体装置の製造コストを抑えつつ信
頼性及び性能を向上できる。According to the first embodiment, the electrical connection between the external terminal and the semiconductor chip, which has been conventionally performed by wire bonding, is performed by welding using a lead frame. Therefore, even if the rated current of a semiconductor element such as an IGBT increases, it can be dealt with by using a lead frame sufficient for the current capacity. That is, in the conventional wire bonding using an Al wire, since the current capacity is limited by the cross-sectional area of the Al wire, the number of bonding wires used increases with an increase in the rated current, and the wire bonding process increases. There was a problem. However, by using a lead frame as in the present embodiment, bonding can be performed with a lead frame having a sufficient electric capacity without increasing the number of steps, so that reliability and performance can be reduced while suppressing the manufacturing cost of the semiconductor device. Can be improved.
【００３４】なお、リードフレーム材質にはＡｌまたは
Ｃｕを例に挙げて説明したが、少なくともＡｌより電気
抵抗率の低い材料を主としたものであればよく、例えば
Ａｕや、Ａｌ、Ｃｕ、Ａｕ等を主とする化合物、または
Ｃｕ／コバール／Ｃｕの３層構造を有するリードフレー
ムを用いてもかまわない。Although the description has been given by taking the lead frame material as an example of Al or Cu, any material having a lower electrical resistivity than at least Al may be used. For example, Au, Al, Cu, Au may be used. A lead frame having a three-layer structure of Cu / Kovar / Cu may be used.
【００３５】また本実施形態ではリードフレームを用い
て溶接接合する為に、導体パターン及び外部電力端子に
それぞれ接続端子及び出力端子を設ける必要がある。こ
の両者の間には通常接触抵抗が発生するが、本実施形態
では接触抵抗の発生する部分をＡｇ等の非常に電気抵抗
率の低い金属によるロー付けにより接合している。これ
により導体パターン及び外部電力端子と接続端子及び出
力端子との間の接触抵抗を軽減して電気的特性を向上で
きる。In the present embodiment, connection and output terminals need to be provided for the conductor pattern and the external power terminal, respectively, in order to perform welding by using a lead frame. Normally, a contact resistance is generated between the two, but in the present embodiment, a portion where the contact resistance is generated is joined by brazing with a metal having a very low electric resistivity such as Ag. Thereby, the contact resistance between the conductor pattern and the external power terminal and the connection terminal and the output terminal can be reduced, and the electrical characteristics can be improved.
【００３６】更に、隣接するリードフレーム同士を平行
に且つ電流の流れる向きが逆になるよう近接配置するこ
とにより、寄生インダクタンスを抑制し、電気的特性を
向上できる。Further, by arranging adjacent lead frames in parallel and close to each other so that current flows in opposite directions, parasitic inductance can be suppressed and electrical characteristics can be improved.
【００３７】また、リードフレームと接続端子及び出力
端子にはＳｎ、または半田等の皮膜を設けている。この
点について図４（ａ）、（ｂ）を用いて説明する。図４
（ａ）、（ｂ）はそれぞれ従来の方法、本実施形態の方
法によるリードフレームと端子との溶接接合の様子を示
している。図４（ａ）に示すように、通常の溶接接合に
では、溶接用のピックアップ２２が接触する部分のみ溶
接接合され、その他の部分は大きな抵抗となる。しか
し、上記皮膜２１を設けることで溶接時に金属皮膜の溶
融が発生して両者の接触面積を拡大できる。そのため接
触抵抗を最低限に抑えることが出来、ワイヤボンディン
グと同等の電気特性を得ることが出来る。The lead frame, the connection terminals, and the output terminals are provided with a film such as Sn or solder. This point will be described with reference to FIGS. FIG.
(A) and (b) show the state of welding connection between the lead frame and the terminal by the conventional method and the method of the present embodiment, respectively. As shown in FIG. 4A, in a normal welding connection, only a portion where the pickup 22 for welding contacts is welded, and the other portions have a large resistance. However, the provision of the coating 21 causes the metal coating to melt during welding, thereby increasing the contact area between the two. Therefore, contact resistance can be suppressed to the minimum, and electrical characteristics equivalent to wire bonding can be obtained.
【００３８】次にこの発明の第２の実施形態に係る半導
体装置について、第１の実施形態同様ＩＧＢＴモジュー
ルを例に挙げて、図５、図６を用いて説明する。図５、
図６ははＩＧＢＴモジュールの断面図、一部斜視図をそ
れぞれ示しており、図６は特にコレクタ、エミッタ接続
端子の構造を示している。Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 5 and 6, taking an IGBT module as an example as in the first embodiment. FIG.
6 shows a sectional view and a partial perspective view of the IGBT module, respectively, and FIG. 6 particularly shows the structure of the collector and emitter connection terminals.
【００３９】図示するように、本実施形態に係るＩＧＢ
Ｔモジュールは、第１の実施形態で説明したＩＧＢＴモ
ジュールにおいて、導体パターン１２−２、１２−３の
一部をそれぞれ用いてコレクタ、エミッタ接続端子１５
−１、１５−２を形成したものである。この場合、コレ
クタ、エミッタ接続端子１５−１、１５−２がチップ実
装及びボンディングに影響を与えない範囲で行うことが
必要である。As shown, the IGB according to this embodiment is
The T module is the same as the IGBT module described in the first embodiment, except that a part of each of the conductor patterns 12-2 and 12-3 is used to connect the collector and emitter connection terminals 15.
-1, 15-2. In this case, the collector and emitter connection terminals 15-1 and 15-2 need to be connected within a range that does not affect chip mounting and bonding.
【００４０】また、第１の実施形態と同様に、コレク
タ、エミッタ接続端子１５−１、１５−２及びリードフ
レーム１８−１、１８−２には錫や半田による皮膜を設
けてもよい。As in the first embodiment, the collector and emitter connection terminals 15-1 and 15-2 and the lead frames 18-1 and 18-2 may be provided with a coating of tin or solder.
【００４１】上記実施形態によれば、導体パターンの一
部を用いて、リードフレームとの溶接接合に必要なコレ
クタ接続端子、エミッタ接続端子を形成している。その
ため第１の実施形態による効果に加え、コレクタ接続端
子、エミッタ接続端子を実装基板上に設置する工程を経
ないため、製造工程を簡略化し製造コストの削減を図る
ことが出来る。また、第１の実施形態と異なり、実装基
板とコレクタ、エミッタ端子間における接触抵抗が発生
しないために、更に優れた電気的特性が得られる。According to the above embodiment, the collector connection terminal and the emitter connection terminal necessary for the welding connection with the lead frame are formed by using a part of the conductor pattern. Therefore, in addition to the effects of the first embodiment, since the process of setting the collector connection terminal and the emitter connection terminal on the mounting substrate is not performed, the manufacturing process can be simplified and the manufacturing cost can be reduced. Further, unlike the first embodiment, since no contact resistance occurs between the mounting substrate and the collector and emitter terminals, more excellent electrical characteristics can be obtained.
【００４２】次にこの発明の第３の実施形態に係る半導
体装置について、第１の実施形態同様ＩＧＢＴモジュー
ルを例に挙げて説明する。図７、図８はＩＧＢＴモジュ
ールの断面図、一部斜視図をそれぞれ示しており、図８
は特にコレクタ、エミッタ接続端子及びリードフレーム
周辺の構造を示している。Next, a semiconductor device according to a third embodiment of the present invention will be described using an IGBT module as an example, as in the first embodiment. 7 and 8 show a cross-sectional view and a partial perspective view of the IGBT module, respectively.
Especially shows the structure around the collector, emitter connection terminal and lead frame.
【００４３】図示するように本実施形態に係るＩＧＢＴ
モジュールの構造は第１、第２の実施形態で説明したも
のと同様であるが、リードフレーム１８−１、１８−２
の一部がモールド樹脂２３により封止されている。リー
ドフレーム１８−１、１８−２を被覆するモールド樹脂
２３は、このモールド樹脂を貫通するスルーホール２４
−１を有しており、またモールド樹脂２３に被覆された
リードフレーム１８−１にもスルーホール２４−２が、
スルーホール２４−１に対応する位置に設けられてい
る。このスルーホール２４−１内でリードフレーム１８
−２とエミッタ接続端子１５−２とが溶接接続されてい
るが、リードフレーム１８−１、１８−２をモールド樹
脂２３により被覆した後に、この溶接接続を行うために
リードフレーム１８−１にもスルーホール２４−２が必
要である。また図７及び図９のＩＧＢＴモジュールの一
部斜視図に示すように、絶縁樹脂１９はリードフレーム
１８−１、１８−２やコレクタ、エミッタ接続端子１５
−１、１５−２、外部電力端子１７−１、１７−２の全
ては覆っておらず、少なくとも半導体チップ１３及びボ
ンディングワイヤ１４を覆うようにして設けられてい
る。As shown, the IGBT according to this embodiment is
The structure of the module is the same as that described in the first and second embodiments, except that the lead frames 18-1 and 18-2 are used.
Are sealed by the mold resin 23. The molding resin 23 covering the lead frames 18-1 and 18-2 is provided with a through hole 24 penetrating the molding resin.
-1 and a through hole 24-2 is also formed in the lead frame 18-1 covered with the mold resin 23.
It is provided at a position corresponding to the through hole 24-1. The lead frame 18 is formed in the through hole 24-1.
-2 and the emitter connection terminal 15-2 are welded, but after the lead frames 18-1 and 18-2 are covered with the mold resin 23, the lead frame 18-1 is also connected to perform the welding connection. Through hole 24-2 is required. As shown in the partial perspective views of the IGBT module of FIGS. 7 and 9, the insulating resin 19 is connected to the lead frames 18-1 and 18-2 and the collector and emitter connection terminals 15.
-1, 15-2, and all of the external power terminals 17-1, 17-2 are not covered, and are provided so as to cover at least the semiconductor chip 13 and the bonding wires 14.
【００４４】上記のような構成によれば、複数のリード
フレームの少なくとも一部をモールド樹脂により絶縁し
ている。そのため、第１の実施形態で述べた効果に加え
て、複数のリードフレームを部品として絶縁を保ちつつ
一体化でき、組み立て精度を向上できると共に、製造工
程を簡略化できる。According to the above configuration, at least a part of the plurality of lead frames is insulated by the mold resin. Therefore, in addition to the effects described in the first embodiment, a plurality of lead frames can be integrated as a component while maintaining insulation, so that assembling accuracy can be improved and the manufacturing process can be simplified.
【００４５】また、リードフレームをモールド樹脂によ
り絶縁することにより、従来はＩＧＢＴモジュール全体
を被覆する必要があった絶縁樹脂を、少なくとも半導体
チップ及びチップ間のボンディングワイヤを被覆するよ
うに設ければよい。そのため、絶縁樹脂の使用量を低減
でき、製造コストを削減できる。Further, by insulating the lead frame with the mold resin, the insulating resin which has conventionally required to cover the entire IGBT module may be provided so as to cover at least the semiconductor chips and the bonding wires between the chips. . Therefore, the amount of the insulating resin used can be reduced, and the manufacturing cost can be reduced.
【００４６】図１０は本実施形態の第１の変形例に係る
ＩＧＢＴモジュールの断面図である。図示するように、
このＩＧＢＴモジュールは第２の実施形態で述べた構造
において、リードフレーム１８−１、１８−２をモール
ド樹脂２３で被覆したものであり、本構造によれば、上
記効果に加えて第２の実施形態で述べた効果を合わせて
得ることが出来る。FIG. 10 is a sectional view of an IGBT module according to a first modification of the present embodiment. As shown
This IGBT module has the structure described in the second embodiment in which the lead frames 18-1 and 18-2 are covered with the mold resin 23. According to this structure, in addition to the above effects, the second embodiment The effects described in the embodiments can be obtained together.
【００４７】図１１は本実施形態の第２の変形例に係る
ＩＧＢＴモジュールのリードフレームの構造について示
している。図示するように、本変形例ではモールド樹脂
２３から露出しているリードフレーム１８−１、１８−
２の一部（破線で囲まれた領域）を波状の構造としてい
る。リードフレームの材料としてのＣｕは熱膨張率が比
較的大きな材料である。そのため、リードフレームをモ
ールド樹脂２３により被覆した状態で接続端子１５−
１、１５−２及び１７−１、１７−２と溶接接合を行う
と、熱によりこの接合部分にストレスが発生する。しか
し、本変形例のようにリードフレームの一部に機械的緩
衝構造を持たせることにより、熱膨張率によるストレス
を解放でき、ＩＧＢＴモジュールの信頼性を向上でき
る。FIG. 11 shows a structure of a lead frame of an IGBT module according to a second modification of the present embodiment. As shown in the drawing, in this modification, the lead frames 18-1 and 18-
Part 2 (a region surrounded by a broken line) has a wavy structure. Cu as a material for the lead frame is a material having a relatively large coefficient of thermal expansion. Therefore, with the lead frame covered with the mold resin 23, the connection terminals 15-
When welding welding is performed with 1, 15-2 and 17-1 and 17-2, stress is generated in this joint by heat. However, by providing a part of the lead frame with a mechanical buffer structure as in the present modification, the stress due to the coefficient of thermal expansion can be released, and the reliability of the IGBT module can be improved.
【００４８】上記第１乃至第３の実施形態によれば、Ｉ
ＧＢＴ等の半導体素子モジュールにおいて、従来ワイヤ
ボンディングにより行っていた実装基板と外部電力端子
との間のボンディングをリードフレームを用いて行って
いる。従来のワイヤボンディングでは、ボンディングワ
イヤの定格電流がその断面積に制限を受けるため、半導
体素子の消費電流が増加した場合、それに応じてボンデ
ィングワイヤ数を増やす必要があった。しかし、この発
明のように半導体素子の消費電流に応じたリードフレー
ムを用いれば、工程を増加させることなくボンディング
を行うことが出来る。また、リードフレームの横幅を大
きく取ることにより断面積を大きくし、リードフレーム
の電気抵抗を低減できる。更に、リードフレームの材料
にはＡｌと実質的に等しい若しくはＡｌ以下の電気抵抗
率を有する材料を用いることで、ワイヤボンディングと
同等若しくはそれ以上の電気的特性を得ることが出来
る。更に、配線に大電流を流すと寄生インダクタンスが
発生する。しかし、この発明のようにボンディングワイ
ヤの代わりにリードフレームを用い、異なる電位のリー
ドフレームを平行に且つそれらに流れる電流の向きが逆
方向になるよう近接配置することで、この寄生インダク
タンスを抑制できる。このようにリードフレームを使っ
て実装基板と外部電力端子との間を溶接接合する場合、
リードフレームと実装基板との間を接続するための接続
端子が必要となる。するとこの接続端子とリードフレー
ム及び実装基板との間には接触抵抗が当然発生するた
め、電気的特性の悪化の原因となる。しかし実装基板と
接続端子との間をＡｇ等の低抵抗金属によりロー付け
し、且つ接続端子とリードフレームの接触部分に錫、半
田等の皮膜を設けて溶接接合することにより、接触抵抗
を低減し、電気的特性を向上できる。更には、複数のリ
ードフレームを樹脂により一体成形化することで、構造
的に堅牢な１つの部品として扱うことが出来、製造の際
の負荷を軽減できる。また、リードフレームを樹脂によ
り被覆することにより、実装基板や半導体チップを被覆
する絶縁樹脂量を低減できるため、製造コストを低減で
きる。According to the first to third embodiments, I
In a semiconductor device module such as a GBT, bonding between a mounting substrate and an external power terminal, which has been conventionally performed by wire bonding, is performed using a lead frame. In conventional wire bonding, the rated current of a bonding wire is limited by its cross-sectional area. Therefore, when the current consumption of a semiconductor element increases, the number of bonding wires must be increased accordingly. However, if a lead frame corresponding to the current consumption of the semiconductor element is used as in the present invention, bonding can be performed without increasing the number of steps. Also, by increasing the width of the lead frame, the cross-sectional area can be increased, and the electrical resistance of the lead frame can be reduced. Furthermore, by using a material having an electrical resistivity substantially equal to or less than Al as the material of the lead frame, it is possible to obtain electrical characteristics equivalent to or better than wire bonding. Furthermore, when a large current flows through the wiring, a parasitic inductance is generated. However, this parasitic inductance can be suppressed by using a lead frame instead of the bonding wire and arranging the lead frames of different potentials in parallel and in the proximity of each other so that the directions of the currents flowing through them are opposite to each other as in the present invention. . When welding between the mounting board and the external power terminal using the lead frame in this way,
A connection terminal for connecting between the lead frame and the mounting board is required. Then, a contact resistance is naturally generated between the connection terminal and the lead frame and the mounting substrate, which causes deterioration of the electrical characteristics. However, the contact resistance is reduced by soldering between the mounting board and the connection terminal with a low-resistance metal such as Ag, and providing a coating of tin, solder, etc. at the contact portion between the connection terminal and the lead frame and welding. And electrical characteristics can be improved. Furthermore, by integrally molding a plurality of lead frames with a resin, it can be handled as one structurally robust part, and the load during manufacturing can be reduced. In addition, by covering the lead frame with a resin, the amount of insulating resin covering the mounting substrate and the semiconductor chip can be reduced, so that the manufacturing cost can be reduced.
【００４９】なお、上記第１乃至第３の実施形態ではＩ
ＧＢＴモジュールを例に挙げて説明したが、半導体チッ
プに形成される半導体素子は当然ＩＧＢＴに限られるも
のではなく、ＭＯＳＦＥＴやバイポーラトランジスタ、
ダイオード等でも良く、複数の異なる半導体素子が形成
されたものでもかまわないことは言うまでもない。In the first to third embodiments, I
Although the description has been given by taking the GBT module as an example, the semiconductor element formed on the semiconductor chip is not limited to the IGBT, but may be a MOSFET, a bipolar transistor, or the like.
It goes without saying that a diode or the like may be used, and a plurality of different semiconductor elements may be formed.
【００５０】なお、本願発明は上記実施形態に限定され
るものではなく、実施段階ではその要旨を逸脱しない範
囲で種々に変形することが可能である。更に、上記実施
形態には種々の段階の発明が含まれており、開示される
複数の構成要件における適宜な組み合わせにより種々の
発明が抽出されうる。例えば、実施形態に示される全構
成要件からいくつかの構成要件が削除されても、発明が
解決しようとする課題の欄で述べた課題が解決でき、発
明の効果の欄で述べられている効果が得られる場合に
は、この構成要件が削除された構成が発明として抽出さ
れうる。It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified in an implementation stage without departing from the scope of the invention. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved and the effects described in the column of the effect of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.
【００５１】[0051]
【発明の効果】以上説明したように、この発明によれ
ば、ワイヤボンディング工程を増やすことなく定格電流
の増加に対応出来ることにより、製造工程の負担を軽減
して製造コストを低減できる半導体装置を提供出来る。As described above, according to the present invention, it is possible to cope with an increase in the rated current without increasing the wire bonding process, thereby reducing the load on the manufacturing process and reducing the manufacturing cost. Can be provided.
【図１】この発明の第１の実施形態に係るＩＧＢＴモジ
ュールの断面図。FIG. 1 is a sectional view of an IGBT module according to a first embodiment of the present invention.
【図２】この発明の第１の実施形態に係るＩＧＢＴモジ
ュールの一部斜視図。FIG. 2 is a partial perspective view of the IGBT module according to the first embodiment of the present invention.
【図３】この発明の第１の実施形態に係るＩＧＢＴモジ
ュールの各端子間の接続部分の拡大断面図。FIG. 3 is an enlarged sectional view of a connection portion between terminals of the IGBT module according to the first embodiment of the present invention.
【図４】この発明の第１の実施形態に係るＩＧＢＴモジ
ュールにおいて、リードフレームと接続端子との間の溶
接接合の方法について説明するための図であり、（ａ）
図は従来方法、（ｂ）図は本発明による方法。FIGS. 4A and 4B are diagrams for explaining a method of welding connection between the lead frame and the connection terminal in the IGBT module according to the first embodiment of the present invention, and FIG.
The figure shows the conventional method, and the figure (b) shows the method according to the present invention.
【図５】この発明の第２の実施形態に係るＩＧＢＴモジ
ュールの断面図。FIG. 5 is a sectional view of an IGBT module according to a second embodiment of the present invention.
【図６】この発明の第２の実施形態に係るＩＧＢＴモジ
ュールの一部斜視図。FIG. 6 is a partial perspective view of an IGBT module according to a second embodiment of the present invention.
【図７】この発明の第３の実施形態に係るＩＧＢＴモジ
ュールの断面図。FIG. 7 is a sectional view of an IGBT module according to a third embodiment of the present invention.
【図８】この発明の第３の実施形態に係るＩＧＢＴモジ
ュールの一部斜視図。FIG. 8 is a partial perspective view of an IGBT module according to a third embodiment of the present invention.
【図９】この発明の第３の実施形態に係るＩＧＢＴモジ
ュールの一部斜視図。FIG. 9 is a partial perspective view of an IGBT module according to a third embodiment of the present invention.
【図１０】この発明の第３の実施形態の第１の変形例に
係るＩＧＢＴモジュールの断面図。FIG. 10 is a cross-sectional view of an IGBT module according to a first modification of the third embodiment of the present invention.
【図１１】この発明の第３の実施形態の第２の変形例に
係るＩＧＢＴモジュールのリードフレームの構造を示す
図。FIG. 11 is a view showing a structure of a lead frame of an IGBT module according to a second modification of the third embodiment of the present invention.
【図１２】従来のＩＧＢＴモジュールの断面図。FIG. 12 is a sectional view of a conventional IGBT module.
１０、１００…放熱板 １１、１１０…実装基板 １２、１２−１〜３、１２０−１〜３…導体 １３、１３０…半導体チップ １４、１４０…ボンディングワイヤ １５、１５−１、１５−２…接続端子 １６、１６−１〜３、１６０−１〜３…外部電力端子 １７、１７−１、１７−２…外部出力端子 １８、１８−１、１８−２…リードフレーム １９、１９０…絶縁樹脂 ２０…低電気抵抗率金属 ２１…皮膜 ２２…溶接用ピックアップ ２３…モールド樹脂 ２４−１、２４−２…スルーホール 10, 100: heatsink 11, 110: mounting board 12, 12-1 to 3, 120-1 to 3 ... conductor 13, 130: semiconductor chip 14, 140: bonding wire 15, 15-1, 15-2: connection Terminal 16, 16-1 to 3, 160-1 to 3 ... External power terminal 17, 17-1, 17-2 ... External output terminal 18, 18-1, 18-2 ... Lead frame 19, 190 ... Insulating resin 20 ... Low electrical resistivity metal 21 ... Coating 22 ... Pickup for welding 23 ... Mold resin 24-1, 24-2 ... Through hole
Claims (10)
前記半導体素子の消費電力に十分な電力容量を有するリ
ードフレームとを具備することを特徴とする半導体装
置。1. A mounting board on which a semiconductor element is mounted, an external terminal for transmitting and receiving power to and from the outside, and electrically connecting the mounting board and the external terminal;
A lead frame having a power capacity sufficient for power consumption of the semiconductor element.
実質的に等しい若しくはＡｌ以下の電気抵抗率を有する
材質からなることを特徴とする請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein said lead frame is mainly made of a material having an electrical resistivity substantially equal to or less than Al.
フレームと平行に、且つ電流が逆向き流れるようにして
近接配置されていることを特徴とする請求項１または２
記載の半導体装置。3. The lead frame according to claim 1, wherein the lead frame is arranged in parallel with an adjacent lead frame so that a current flows in the opposite direction.
13. The semiconductor device according to claim 1.
素子と電気的に接続される接続端子を更に備え、 前記接続端子と前記外部端子とが前記リードフレームに
より接続され、 前記接続端子と前記リードフレームとは溶接接合されて
いることを特徴とする請求項１乃至３いずれか１項記載
の半導体装置。4. The semiconductor device according to claim 1, further comprising a connection terminal provided on the mounting substrate and electrically connected to the semiconductor element, wherein the connection terminal and the external terminal are connected by the lead frame. The semiconductor device according to claim 1, wherein the semiconductor device is welded to the lead frame.
素子と電気的に接続され、一部が接続端子を構成する導
電性部材を更に備え、 前記接続端子と前記外部端子とが前記リードフレームに
より接続され、 前記接続端子と前記リードフレームとは溶接接合されて
いることを特徴とする請求項１乃至３いずれか１項記載
の半導体装置。5. A conductive member provided on the mounting board, electrically connected to the semiconductor element, and partially forming a connection terminal, wherein the connection terminal and the external terminal are connected to the lead frame. The semiconductor device according to claim 1, wherein the connection terminal is connected to the lead frame by welding.
ともＡｌより低抵抗の材料によりロー付けされているこ
とを特徴とする請求項４記載の半導体装置。6. The semiconductor device according to claim 4, wherein said connection terminal is soldered to said mounting board with a material having a resistance lower than at least Al.
フレームと接触する領域に設けられた錫または半田によ
る皮膜を有することを特徴とする請求項４乃至６いずれ
か１項記載の半導体装置。7. The semiconductor device according to claim 4, wherein said connection terminal has a coating made of tin or solder provided at least in a region in contact with said lead frame.
レームの少なくとも一部領域はモールド樹脂により絶縁
されていることを特徴とする請求項１乃至７いずれか１
項記載の半導体装置。8. The semiconductor device according to claim 1, wherein at least a part of the plurality of lead frames having different potentials is insulated by a mold resin.
13. The semiconductor device according to claim 1.
板及び半導体素子をモールドする絶縁樹脂を更に備え、 前記リードフレーム及び前記接続端子の少なくとも一部
は前記絶縁樹脂上に露出していることを特徴とする請求
項８記載の半導体装置。9. An insulating resin provided on the insulating substrate and molding the mounting substrate and the semiconductor element, wherein at least part of the lead frame and the connection terminals are exposed on the insulating resin. 9. The semiconductor device according to claim 8, wherein:
部領域に波状の断面構造を有する機械的緩衝構造である
ことを特徴とする請求項１乃至９いずれか１項記載の半
導体装置。10. The semiconductor device according to claim 1, wherein the lead frame has a mechanical buffer structure having a wavy cross-sectional structure in at least a part of the region.
Priority Applications (1)
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|---|---|---|---|
| JP2000199626A JP2002026246A (en) | 2000-06-30 | 2000-06-30 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000199626A JP2002026246A (en) | 2000-06-30 | 2000-06-30 | Semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2002026246A true JP2002026246A (en) | 2002-01-25 |
Family
ID=18697611
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|---|---|---|---|
| JP2000199626A Pending JP2002026246A (en) | 2000-06-30 | 2000-06-30 | Semiconductor device |
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| Country | Link |
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| JP (1) | JP2002026246A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004097780A1 (en) * | 2003-04-28 | 2004-11-11 | Matsushita Electric Industrial Co., Ltd. | Plasma display device |
| JP2007266608A (en) * | 2006-03-29 | 2007-10-11 | Infineon Technologies Ag | Semiconductor module |
| CN100405423C (en) * | 2004-04-26 | 2008-07-23 | 株式会社日立制作所 | plasma display device |
| JP2008205058A (en) * | 2007-02-19 | 2008-09-04 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| JP2009130163A (en) * | 2007-11-26 | 2009-06-11 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| CN103594407A (en) * | 2013-11-25 | 2014-02-19 | 西安永电电气有限责任公司 | Half-bridge module three-time welding fixing tool |
-
2000
- 2000-06-30 JP JP2000199626A patent/JP2002026246A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004097780A1 (en) * | 2003-04-28 | 2004-11-11 | Matsushita Electric Industrial Co., Ltd. | Plasma display device |
| JP2004347622A (en) * | 2003-04-28 | 2004-12-09 | Matsushita Electric Ind Co Ltd | Plasma display panel |
| US7215085B2 (en) | 2003-04-28 | 2007-05-08 | Matsushita Electric Industrial Co., Ltd. | Plasma display device |
| CN100421136C (en) * | 2003-04-28 | 2008-09-24 | 松下电器产业株式会社 | Plasma display device |
| JP4661028B2 (en) * | 2003-04-28 | 2011-03-30 | パナソニック株式会社 | Plasma display device |
| CN100405423C (en) * | 2004-04-26 | 2008-07-23 | 株式会社日立制作所 | plasma display device |
| JP2007266608A (en) * | 2006-03-29 | 2007-10-11 | Infineon Technologies Ag | Semiconductor module |
| JP2008205058A (en) * | 2007-02-19 | 2008-09-04 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| JP2009130163A (en) * | 2007-11-26 | 2009-06-11 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| CN103594407A (en) * | 2013-11-25 | 2014-02-19 | 西安永电电气有限责任公司 | Half-bridge module three-time welding fixing tool |
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