JP4039258B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP4039258B2
JP4039258B2 JP2003024688A JP2003024688A JP4039258B2 JP 4039258 B2 JP4039258 B2 JP 4039258B2 JP 2003024688 A JP2003024688 A JP 2003024688A JP 2003024688 A JP2003024688 A JP 2003024688A JP 4039258 B2 JP4039258 B2 JP 4039258B2
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power semiconductor
surface electrode
semiconductor device
igbt
internal wiring
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JP2004235566A (en
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良成 池田
克彦 吉原
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
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    • H01L2924/351—Thermal stress

Description

【０００１】
【発明の属する技術分野】
本発明は、電力変換用インバータ装置に適用するＩＧＢＴモジュールなどを実施対象とした電力用半導体装置に関する。
【０００２】
【従来の技術】
頭記したＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）モジュールを例に、ケース内に２組のＩＧＢＴを内装し、ボンディングワイヤにより内部配線した電力用半導体装置の従来構成を図５（ａ）〜（ｃ）に示す。なお、（ａ）図は外囲ケースを省略した主要部の平面図、（ｂ）は外囲ケースと組合せた組立構造の断面側視図、（ｃ）は等価回路図である。
図において、１は放熱板兼用の金属ベース板、２は金属ベース板１の上に左右に並置搭載して半田接合した絶縁基板（図示の絶縁基板２は、絶縁板２ａの表裏両面に回路パターン２ｂ，裏面銅板２ｃを直接接合したＤｉｒｅｃｔ Ｂｏｎｄｉｎｇ Ｃｏｐｐｅｒ基板）、３は絶縁基板２の回路パターン２ｂに半田マウントしたＩＧＢＴ、４はＩＧＢＴ３に並置して並列接続したＦＷＤ（フリーホイーリングダイオード）、５は半田接合部、６は金属ベース板１に組合せた外囲ケース（樹脂ケース）、７は外囲ケース６に一体成形して外部に引き出した主回路の外部接続端子、８はＩＧＢＴ３の表面電極（エミッタ電極），ＦＷＤ４の表面電極（アノード電極）と絶縁基板２の回路パターン２ａとの間，左右に並ぶ絶縁基板２の回路パターン２ａの間，および回路パターン２ａと外部接続端子７との間に配線して主回路を形成するボンディングワイヤ（φ３００〜４００μｍのＡｌワイヤ）、９はゲート用の外部接続端子、１０はＩＧＢＴ３のゲート電極とゲート端子９との間を接続するボンディングワイヤである。なお、図示してないが外囲ケース６の内部にはシリコーンゲルなどを充填して回路部品を樹脂封止している。
【０００３】
一方、電力用半導体装置の内部配線構造について、パワー半導体チップの表面電極から外部接続端子を引出し、また内部配線用のボンディングワイヤを導体板に変更した上で、半田付けあるいは導電性樹脂（接着剤）により接合してモジュールの通電容量，放熱性の増大化および配線インダクタンスの低減化を図るようにした構成のパワー半導体装置も知られている（例えば、特許文献１，特許文献２参照。）。
【０００４】
【特許文献１】
特開平８−８３９５号公報
【特許文献２】
特開平１１−１７０８７号公報
【０００５】
【発明が解決しようとする課題】
最近の電力用半導体装置は、電流容量が増大化する傾向にある一方で、パワーサイクル試験の熱ストレスに対する耐久，信頼性の向上に加えて、組立性の改善，パッケージの小型化，コスト低減化が要求されている。
かかる点、特許文献１，特許文献２のように、主回路の配線部材としてジュール発熱が大きいワイヤを導電板に変更することにより、通電容量の増大化と併せて、図５に示したワイヤ配線方式に見られるワイヤ接合部の熱ストレスによる剥離，配線インダクタンスの増加を改善できる利点があるが、一方では組立性の面で次記のような問題点が残る。
【０００６】
すなわち、ワイヤボンディング方式（例えば超音波ボンディング法）は室温での接合が可能であるほか、接合に要する時間も僅か数百ｍｓｅｃ程度で済む。これに対して、配線部材の導体板を半田付け接合するには、パワー半導体チップを含む回路組立体を炉内温度２５０〜３００℃程度の加熱炉に搬入して半田付けを行う必要があり、実際の工程では半田付けに少なくとも１５分程度の時間が掛かって組立工程のスループットが低くなるほか、半田接合部に残留応力が残る問題もある。さらに、接合材に導電接着剤を使用すると、接合部の電気抵抗，熱抵抗が増大するほか、接合強度も低下する。
【０００７】
本発明は上記の点に鑑みなされたものであり、ワイヤを導電板に代えた内部配線方式の利点を生かしつつ、室温での接合，および接合作業時間の大幅な短縮化が図れ、しかも電気的，機械的に安定した接合が得られるような配線構造を採用した電力用半導体装置を提供することを目的とする。
【０００８】
【課題を解決するための手段】
上記目的を達成するために、本発明によれば、外囲ケースに組合せた金属ベース板の上に少なくとも一枚以上の絶縁基板を搭載し、該絶縁基板上に形成した回路パターンにパワー半導体チップをマウントした上で、パワー半導体チップ，絶縁基板の回路パターン，および外部接続端子の相互間に内部配線を施した組立構造になる電力用半導体装置において、
【０００９】
（１）金属ベース板上に並置搭載した複数枚の絶縁基板を有し、絶縁基板ごとにＩＧＢＴの表面電極とＦＷＤの表面電極とを接続する内部配線部材と、これらの絶縁基板の相互間でその回路パターンの間を接続する内部配線部材と、回路パターンとパワー半導体チップの表面電極との間を接続する内部配線部材とを備え、これら内部配線部材のいずれも、及び外部接続端子を含めて半導体装置の主回路を形成する各配線部材が導体板であり、該導体板を直接金属接合法により相手側部材に直接接合する（請求項１）。
【００１０】
上記のように半導体装置の主回路を形成する内部配線について、従来のボンディングワイヤを導体板に代えた上で、超音波接合法，あるいは熱圧着法などによる直接金属接合法を採用して導体板を相手部材に直接接合することにより、室温での接合が可能となって熱的な残留応力の発生も殆どなく、またその接合に要する時間も僅か数百ｍｓｅｃの短時間で高速接合できて、組立工程のスループットが向上する。しかも、半田付け，導電性接着剤による接合法のように接合箇所に接合部材が介在しないので接合部の電気抵抗が低くなり、また高い伝熱性も確保できて半導体装置の動作特性が向上する。
【００１１】
【発明の実施の形態】
以下、本発明の実施の形態を図１〜図５に示す参考例または実施例に基づいて説明する。なお、実施例の図中で図５に対応する部材には同一符号を付してその説明は省略する。
〔参考例１〕
図１は参考例を示すものである。この参考例においては、ＩＧＢＴ（パワー半導体チップ）３の表面電極（エミッタ）に、平角導体板で作られた外部接続端子１１を超音波接合あるいは熱圧着の直接金属接合法により直接接合して引き出している。
【００１２】
次に発明者等が行った外部接続端子１１の超音波接合について述べる。すなわち、最大定格５０Ａ，サイズ６ｍｍ□のＩＧＢＴ３に対して、外部接続端子１１を厚さ１ｍｍ，幅５ｍｍのＣｕ材で作られた平角導体板で形成し、先端に形成した脚部（５ｍｍ□）の接合面をＩＧＢＴ３の表面電極（厚さ５〜２０μｍのＡｌ電極膜で形成したエミッタ電極）に当てがい、ウエッジツールに加える周波数２０ＫＨｚ，押圧荷重４０Ｋｇｆ，接合時間０．３ｓｅｃの条件で超音波接合し、両者が電気的，機械的に安定よく接合できることを確認した。
また、前記の超音波接合法とは別に、ＩＧＢＴ３の表面電極および外部接続端子１１の接合面を表面粗さ１００ｎｍ程度までＣＭＰ（化学的機械的研磨）装置で研磨し、さらに不活性ガスの雰囲気内で活性化，清浄処理して表面粗さ１０ｎｍ以下の平滑面に仕上げた上で、ＩＧＢＴの表面電極面に外部接続端子の接合面を型ね合わせて加熱圧着することで、前記と同様にＩＧＢＴ３の表面電極に外部接続端子１１を直接金属接合できることを確認した。
【００１３】
この場合に、外部接続端子１１を半導体チップの表面電極と同じ金属材料とすれば、線膨張係数差による熱応力発生のない配線構造が可能となる。
なお、図示参考例では、絶縁基板２の回路パターン２ａに接合して引き出した外部接続端子（コレクタ端子）１１にについても、前記と同様に直接金属接合法により回路パターン２ａに接合している。
〔参考例２〕
図２は参考例を示すものである。この参考例においては、外囲ケース６に一体成形したケース端子構造になる主回路の外部接続端子（コレクタ端子）７とＩＧＢＴ３をマウントした絶縁基板２の回路パターン２ａとの間を接続する配線部材として、図５（ｂ）に示したボンディングワイヤ８の代わりに厚さ１ｍｍ，幅５ｍｍの導体板（Ｃｕ）１２を採用し、この導体板１２の両端接合面を相手側部材の上に重ね合わせて先記参考例１と同様に超音波接合あるいは熱圧着の直接金属接合法により直接接合して主回路を形成している。
【００１４】
なお、この参考例おいて、外部接続端子（エミッタ端子）１１は参考例１と同様に直接金属接合法によりＩＧＢＴ３の表面電極に直接接合している。
〔実施例１〕
次に、本発明の実施例として、図５（ｃ）に示したアーム回路を構成する２個組ＩＧＢＴモジュールの配線構造を図３，図４に示す。なお、図３は平面図、図４は図３の側視展開図である。
この実施例では、図５（ａ）と同様に金属ベース板１に２枚の絶縁基板２を左右に並置して搭載し、かつ各絶縁基板２の回路パターン２ａにはそれぞれＩＧＢＴ３，ＦＷＤ４をマウントした上で、その相互間を次記のように配線して外部接続端子９，１１を引き出している。なお、図中における各外部接続端子には、その端子記号Ｃ１，Ｃ２Ｅ１，Ｅ２，Ｇ１，Ｇ２を併記している。
【００１５】
すなわち、モジュールの主回路を形成する配線構造に関して、図示実施例では図５（ａ），（ｂ）の従来構造における主回路のボンディングワイヤ８を導体板１２に置き換えた上で、各導体板および外部接続端子を先記実施例と同様に超音波接合あるいは熱圧着の直接金属接合法により相手側部材に直接接合して回路を組立てるようにしている。すなわち、各枚の絶縁基板２ごとにＩＧＢＴ３の表面電極（エミッタ電極）とＦＷＤ４の表面電極（アノード電極）とを導体板１２により並列接続し、金属ベース板１の上に並置搭載した絶縁基板２の相互間では、導体板１２を介して回路パターン２ａの間を直列接続している。また、主回路の外部接続端子（Ｃ１），（Ｃ２Ｅ１）は絶縁基板２の回路パターン２ａに接合し、外部接続端子（Ｅ２）は導体板１２の上面に接合して引き出すようにしている。
【００１６】
上記の構成によれば、図５に示した従来のワイヤ配線方式と比べて、通電容量の増大，配線インダクタンスの低減のほか、パッケージの小型化も可能となる。また、先記の特許文献１に開示されている半田接合方式と比べて、接合時間の大幅な短縮、並びに室温での接合が可能で接合部に生じる残留応力を軽減できる。さらに、特許文献２に開示されている導電接着剤による接合と比べても、直接金属接合では接合部材を介さないので、電気抵抗，熱抵抗が低減し、接合強度が高まる。
【００１７】
【発明の効果】
以上述べたように、本発明によれば主回路の配線部材をワイヤから導体板に代えた上で、該導体板を直接金属接合法により相手側部材に接合したことにより、通電容量の増大，配線インダクタンスの低減化が図れるとともに、室温での接合が可能となって熱的な残留応力の発生も殆どなく、またその接合に要する時間も僅か数百ｍｓｅｃの短時間で接合できて組立工程のスループット性が向上する。しかも、半田付け，導電性接着剤による接合法のように接合箇所に接合部材が介在しないので接合部の電気抵抗が低く、高い伝熱性も確保できて半導体装置の動作特性の向上化が図れる。
【図面の簡単な説明】
【図１】 本発明の参考例１に対応する半導体装置の内部配線構造を表す断面図
【図２】 本発明の参考例２に対応する半導体装置の内部配線構造を表す断面図
【図３】 本発明の実施例１に対応する半導体装置の内部配線構造を表す平面図
【図４】 図３の側視展開図
【図５】 ワイヤ配線方式を採用した従来の半導体装置の内部配線構造を表す図で、（ａ）は外囲ケースを省略した平面図、（ｂ）は（ａ）の矢視Ｘ−Ｘ断面図、（ｃ）は等価回路図
【符号の説明】
１ 金属ベース板
２ 絶縁基板
２ａ 回路パターン
３ ＩＧＢＴ（パワー半導体チップ）
４ ＦＷＤ
６ 外囲ケース
１１ 主回路の外部接続端子
１２ 導体板（主回路の配線部材）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device in which an IGBT module or the like applied to an inverter device for power conversion is implemented.
[0002]
[Prior art]
5 (a) to 5 (c) show a conventional configuration of a power semiconductor device in which two IGBTs are housed in a case and internally wired with bonding wires, taking the IGBT (Insulated Gate Bipolar Transistor) module mentioned above as an example. Show. 1A is a plan view of a main part in which the outer case is omitted, FIG. 2B is a sectional side view of the assembly structure combined with the outer case, and FIG. 2C is an equivalent circuit diagram.
In the drawing, 1 is a metal base plate that also serves as a heat sink, 2 is an insulating substrate that is mounted side by side on the metal base plate 1 and solder-bonded (the insulating substrate 2 shown in the figure has circuit patterns on both sides of the insulating plate 2a). 2b, a Direct Bonding Copper board in which the back surface copper plate 2c is directly joined), 3 is an IGBT solder-mounted on the circuit pattern 2b of the insulating substrate 2, 4 is an FWD (free wheeling diode) that is juxtaposed in parallel with the IGBT 3, and 5 is Solder joints, 6 is an outer case (resin case) combined with the metal base plate 1, 7 is an external connection terminal of the main circuit formed integrally with the outer case 6 and drawn to the outside, and 8 is a surface electrode of the IGBT 3 ( Emitter electrode), the circuit pattern 2a of the insulating substrate 2 arranged on the left and right between the surface electrode (anode electrode) of the FWD 4 and the circuit pattern 2a of the insulating substrate 2 Bonding wires (Al wire of φ300 to 400 μm) which are wired between the circuit pattern 2a and the external connection terminal 7 to form a main circuit, 9 is an external connection terminal for gate, and 10 is a gate electrode of the IGBT 3 It is a bonding wire that connects between the gate terminal 9. Although not shown, the outer casing 6 is filled with silicone gel or the like to seal the circuit components with resin.
[0003]
On the other hand, with respect to the internal wiring structure of the power semiconductor device, the external connection terminal is drawn from the surface electrode of the power semiconductor chip, and the bonding wire for internal wiring is changed to a conductor plate, and then soldered or conductive resin (adhesive) ) Is also known (see, for example, Patent Document 1 and Patent Document 2) which are configured to increase the current-carrying capacity of the module, increase heat dissipation, and reduce wiring inductance.
[0004]
[Patent Document 1]
JP-A-8-8395 [Patent Document 2]
Japanese Patent Laid-Open No. 11-17087
[Problems to be solved by the invention]
While current power semiconductor devices tend to increase in current capacity, in addition to improving durability and reliability against thermal stress in power cycle testing, improvement in assembly, miniaturization of packages, and cost reduction Is required.
In this respect, as shown in Patent Document 1 and Patent Document 2, the wire wiring shown in FIG. 5 is combined with an increase in current-carrying capacity by changing a wire having a large Joule heat generation as a wiring member of the main circuit to a conductive plate. Although there is an advantage that it is possible to improve the separation due to the thermal stress of the wire joint portion and the increase of the wiring inductance, which are seen in the system, the following problems remain in terms of assembly.
[0006]
That is, the wire bonding method (for example, ultrasonic bonding method) can be bonded at room temperature, and the time required for bonding is only about several hundred msec. On the other hand, in order to solder and bond the conductor plate of the wiring member, the circuit assembly including the power semiconductor chip needs to be carried into a furnace having a furnace temperature of about 250 to 300 ° C. and soldered. In the actual process, the soldering process takes at least about 15 minutes, which lowers the throughput of the assembly process, and there is a problem that residual stress remains in the solder joint. Furthermore, when a conductive adhesive is used for the bonding material, the electrical resistance and thermal resistance of the bonded portion increase and the bonding strength also decreases.
[0007]
The present invention has been made in view of the above points, and while taking advantage of the internal wiring system in which the wire is replaced with the conductive plate, the bonding at room temperature and the bonding work time can be greatly shortened, and the electrical An object of the present invention is to provide a power semiconductor device that employs a wiring structure that can provide mechanically stable bonding.
[0008]
[Means for Solving the Problems]
To achieve the above object, according to the present invention, at least one insulating substrate is mounted on a metal base plate combined with an enclosing case, and a power semiconductor chip is formed on a circuit pattern formed on the insulating substrate. In a power semiconductor device having an assembly structure in which internal wiring is provided between a power semiconductor chip, a circuit pattern of an insulating substrate, and an external connection terminal after mounting
[0009]
(1) An internal wiring member that has a plurality of insulating substrates mounted in parallel on a metal base plate and connects the surface electrode of the IGBT and the surface electrode of the FWD for each insulating substrate, and between these insulating substrates An internal wiring member that connects between the circuit patterns, and an internal wiring member that connects between the circuit pattern and the surface electrode of the power semiconductor chip, each of these internal wiring members including an external connection terminal Each wiring member forming the main circuit of the semiconductor device is a conductor plate, and the conductor plate is directly joined to the mating member by a direct metal joining method.
[0010]
For the internal wiring that forms the main circuit of the semiconductor device as described above, the conventional bonding wire is replaced with a conductor plate, and then a direct metal bonding method such as an ultrasonic bonding method or a thermocompression bonding method is adopted. By joining directly to the mating member, it is possible to join at room temperature, there is almost no occurrence of thermal residual stress, and the time required for joining can be high-speed joined in only a few hundred msec, The throughput of the assembly process is improved. In addition, since no joining member is interposed at the joining location unlike the joining method using soldering or conductive adhesive, the electrical resistance of the joining portion is lowered, and high heat conductivity can be ensured to improve the operating characteristics of the semiconductor device.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described based on reference examples or examples shown in FIGS. In addition, in the figure of an Example, the same code | symbol is attached | subjected to the member corresponding to FIG. 5, and the description is abbreviate | omitted.
[ Reference Example 1 ]
FIG. 1 shows a reference example . In this reference example , an external connection terminal 11 made of a rectangular conductor plate is directly joined to a surface electrode (emitter) of an IGBT (power semiconductor chip) 3 by ultrasonic metal bonding or direct metal bonding method of thermocompression bonding. ing.
[0012]
Next, ultrasonic bonding of the external connection terminal 11 performed by the inventors will be described. That is, for the IGBT 3 having a maximum rating of 50 A and a size of 6 mm □, the external connection terminal 11 is formed of a rectangular conductor plate made of a Cu material having a thickness of 1 mm and a width of 5 mm, and a leg portion (5 mm □) formed at the tip. Is bonded to the surface electrode of the IGBT 3 (emitter electrode formed of an Al electrode film having a thickness of 5 to 20 μm), and ultrasonic bonding is performed under the conditions of a frequency applied to the wedge tool of 20 KHz, a pressing load of 40 Kgf, and a bonding time of 0.3 sec. It was confirmed that the two could be joined electrically and mechanically stably.
In addition to the ultrasonic bonding method described above, the surface electrode of the IGBT 3 and the bonding surface of the external connection terminal 11 are polished to a surface roughness of about 100 nm by a CMP (Chemical Mechanical Polishing) apparatus, and an inert gas atmosphere is further obtained. In the same way as described above, the surface of the external connection terminal is mated with the surface electrode surface of the IGBT and heat-pressed after the surface is activated and cleaned in the surface to finish a smooth surface with a surface roughness of 10 nm or less. It was confirmed that the external connection terminal 11 can be directly metal bonded to the surface electrode of the IGBT 3.
[0013]
In this case, if the external connection terminal 11 is made of the same metal material as that of the surface electrode of the semiconductor chip, a wiring structure that does not generate thermal stress due to the difference in linear expansion coefficient can be realized.
In the illustrated reference example , the external connection terminals (collector terminals) 11 bonded and drawn out to the circuit pattern 2a of the insulating substrate 2 are also directly bonded to the circuit pattern 2a by the metal bonding method as described above.
[ Reference Example 2 ]
FIG. 2 shows a reference example . In this reference example , a wiring member for connecting between the external connection terminal (collector terminal) 7 of the main circuit having a case terminal structure integrally formed with the surrounding case 6 and the circuit pattern 2a of the insulating substrate 2 on which the IGBT 3 is mounted. As shown in FIG. 5B, a conductor plate (Cu) 12 having a thickness of 1 mm and a width of 5 mm is used instead of the bonding wire 8 shown in FIG. 5B, and both end joining surfaces of the conductor plate 12 are superimposed on the mating member. In the same manner as in Reference Example 1, the main circuit is formed by direct bonding by ultrasonic metal bonding or thermocompression direct metal bonding.
[0014]
In this reference example , the external connection terminal (emitter terminal) 11 is directly bonded to the surface electrode of the IGBT 3 by a direct metal bonding method as in the first reference example .
Example 1
Next, as an embodiment of the present invention, FIG. 3 and FIG. 4 show a wiring structure of a double IGBT module constituting the arm circuit shown in FIG. 3 is a plan view, and FIG. 4 is a side view development view of FIG.
In this embodiment, similarly to FIG. 5A, two insulating substrates 2 are mounted side by side on the metal base plate 1 and IGBTs 3 and FWDs 4 are mounted on the circuit pattern 2a of each insulating substrate 2, respectively. In addition, the external connection terminals 9 and 11 are drawn out by wiring between them as follows. In addition, the terminal symbol C1, C2E1, E2, G1, G2 is written together in each external connection terminal in the figure.
[0015]
That is, with respect to the wiring structure for forming the main circuit of the module, in the illustrated embodiment, the bonding wires 8 of the main circuit in the conventional structure of FIGS. As in the previous embodiment, the external connection terminal is directly joined to the mating member by ultrasonic joining or thermocompression direct metal joining, and the circuit is assembled. That is, for each insulating substrate 2, the surface electrode (emitter electrode) of the IGBT 3 and the surface electrode (anode electrode) of the FWD 4 are connected in parallel by the conductor plate 12, and the insulating substrate 2 mounted in parallel on the metal base plate 1. Are connected in series between the circuit patterns 2 a via the conductor plate 12. The external connection terminals (C1) and (C2E1) of the main circuit are joined to the circuit pattern 2a of the insulating substrate 2, and the external connection terminal (E2) is joined to the upper surface of the conductor plate 12 and pulled out.
[0016]
According to the above configuration, it is possible to increase the energizing capacity and reduce the wiring inductance, as well as to reduce the size of the package, as compared with the conventional wire wiring system shown in FIG. Compared with the solder bonding method disclosed in the above-mentioned Patent Document 1, the bonding time can be greatly shortened, and bonding at room temperature can be performed, and the residual stress generated in the bonded portion can be reduced. Furthermore, even when compared with the bonding using the conductive adhesive disclosed in Patent Document 2, direct metal bonding does not involve a bonding member, so that the electrical resistance and thermal resistance are reduced and the bonding strength is increased.
[0017]
【The invention's effect】
As described above, according to the present invention, the wiring member of the main circuit is changed from a wire to a conductor plate, and then the conductor plate is directly joined to the mating member by a metal joining method, thereby increasing the current carrying capacity. The wiring inductance can be reduced, bonding at room temperature is possible, there is almost no generation of thermal residual stress, and the time required for bonding can be bonded in a short time of only a few hundred msec. Throughput is improved. In addition, since no joining member is interposed at the joining location as in the joining method using soldering or conductive adhesive, the electrical resistance of the joining portion is low, high heat conductivity can be ensured, and the operating characteristics of the semiconductor device can be improved.
[Brief description of the drawings]
1 is a cross-sectional view illustrating an internal wiring structure of a semiconductor device corresponding to Reference Example 1 of the present invention. FIG. 2 is a cross-sectional view illustrating an internal wiring structure of a semiconductor device corresponding to Reference Example 2 of the present invention. FIG. 4 is a plan view showing an internal wiring structure of a semiconductor device corresponding to Example 1 of the present invention. FIG. 4 is a side view of FIG. 3. FIG. 5 shows an internal wiring structure of a conventional semiconductor device adopting a wire wiring system. In the figure, (a) is a plan view with the outer case omitted, (b) is a cross-sectional view taken along the line XX of (a), and (c) is an equivalent circuit diagram.
DESCRIPTION OF SYMBOLS 1 Metal base board 2 Insulating substrate 2a Circuit pattern 3 IGBT (power semiconductor chip)
4 FWD
6 Enclosing case 11 External connection terminal of main circuit 12 Conductor plate (wiring member of main circuit)

Claims (3)

外囲ケースに組合せた金属ベース板の上に少なくとも一枚以上の絶縁基板を搭載し、該絶縁基板上に形成した回路パターンにパワー半導体チップをマウントした上で、パワー半導体チップ，絶縁基板の回路パターン，および外部接続端子の相互間に内部配線を施した組立構造になる電力用半導体装置において、
金属ベース板上に並置搭載した複数枚の絶縁基板を有し、絶縁基板ごとにＩＧＢＴの表面電極とＦＷＤの表面電極とを接続する内部配線部材と、これらの絶縁基板の相互間でその回路パターンの間を接続する内部配線部材と、回路パターンとパワー半導体チップの表面電極との間を接続する内部配線部材とを備え、これら内部配線部材のいずれも、及び外部接続端子を含めて半導体装置の主回路を形成する各配線部材が導体板であり、該導体板を直接金属接合法により相手側部材に直接接合したことを特徴とする電力用半導体装置。At least one insulating substrate is mounted on a metal base plate combined with an enclosing case, and a power semiconductor chip is mounted on a circuit pattern formed on the insulating substrate. In a power semiconductor device having an assembly structure in which internal wiring is provided between patterns and external connection terminals,
An internal wiring member having a plurality of insulating substrates mounted side by side on a metal base plate and connecting the IGBT surface electrode and the FWD surface electrode for each insulating substrate, and the circuit pattern between these insulating substrates An internal wiring member for connecting between the circuit pattern and an internal wiring member for connecting between the circuit pattern and the surface electrode of the power semiconductor chip, both of these internal wiring members including the external connection terminals of the semiconductor device A power semiconductor device, wherein each wiring member forming a main circuit is a conductor plate, and the conductor plate is directly joined to a mating member by a direct metal joining method. 前記ＩＧＢＴがアーム回路を構成することを特徴とする請求項１記載の電力用半導体装置。The power semiconductor device according to claim 1, wherein the IGBT constitutes an arm circuit. ＩＧＢＴの表面電極とＦＷＤの表面電極とを接続する前記内部配線部材が、該ＩＧＢＴの表面電極とＦＷＤの表面電極とを並列接続することを特徴とする請求項１記載の電力用半導体装置。2. The power semiconductor device according to claim 1, wherein the internal wiring member that connects the surface electrode of the IGBT and the surface electrode of the FWD connects the surface electrode of the IGBT and the surface electrode of the FWD in parallel.
JP2003024688A 2003-01-31 2003-01-31 Power semiconductor device Expired - Lifetime JP4039258B2 (en)

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