JPH01235261A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH01235261A
JPH01235261A JP6286588A JP6286588A JPH01235261A JP H01235261 A JPH01235261 A JP H01235261A JP 6286588 A JP6286588 A JP 6286588A JP 6286588 A JP6286588 A JP 6286588A JP H01235261 A JPH01235261 A JP H01235261A
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor chip
multilayer wiring
bump electrodes
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6286588A
Inventor
Shigeo Kuroda
Kanji Otsuka
Toshiya Saito
Kunizo Sawara
Takeo Yamada
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6286588A priority Critical patent/JPH01235261A/en
Publication of JPH01235261A publication Critical patent/JPH01235261A/en
Application status is Granted legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Abstract

PURPOSE:To enable a semiconductor chip to be packaged with a sealing package whose size is reduced, by covering the whole region where bump electrodes are provided only with silicon gel for sealing said region. CONSTITUTION:A semiconductor chip 3 to which a heat conducting area enlarging plate 2 for providing passages for conducting heat generated by a semiconductor chip 3 is attached by means of an adhesive 3b is flip-chip bonded to a multilayer wiring board 1 of ceramics through solder bump electrodes 3a, the multilayer wiring board 1 including predetermined interconnections and passive elements such as resistance or the like and having an externally connecting terminal 1a. A damming resin tape 4 of a polyimide resin for example is affixed around the external periphery between the multilayer wiring board 1 and the heat conducting area enlarging plate 2, by means of an adhesive of a silicone resin for example, whereby a cavity 5 is defined. Silicone gel 6 is injected into the cavity 5 and the region of the solder bump electrodes 3a is sealed thereby.
JP6286588A 1988-03-15 1988-03-15 Semiconductor device and manufacture thereof Granted JPH01235261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6286588A JPH01235261A (en) 1988-03-15 1988-03-15 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6286588A JPH01235261A (en) 1988-03-15 1988-03-15 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH01235261A true JPH01235261A (en) 1989-09-20

Family

ID=13212614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6286588A Granted JPH01235261A (en) 1988-03-15 1988-03-15 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH01235261A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0662732A1 (en) * 1994-01-11 1995-07-12 Sgs-Thomson Microelectronics Ltd. Circuit connection in an electrical assembly
WO1996009645A1 (en) * 1994-09-20 1996-03-28 Hitachi, Ltd. Semiconductor device and its mounting structure
US6133639A (en) * 1994-09-20 2000-10-17 Tessera, Inc. Compliant interface for semiconductor chip and method therefor
US6169328B1 (en) 1994-09-20 2001-01-02 Tessera, Inc Semiconductor chip assembly
US6403882B1 (en) 1997-06-30 2002-06-11 International Business Machines Corporation Protective cover plate for flip chip assembly backside
US7112879B2 (en) 1995-10-31 2006-09-26 Tessera, Inc. Microelectronic assemblies having compliant layers
JP2008171925A (en) * 2007-01-10 2008-07-24 Denso Corp Manufacturing method for bonding structure

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0662732A1 (en) * 1994-01-11 1995-07-12 Sgs-Thomson Microelectronics Ltd. Circuit connection in an electrical assembly
US5561594A (en) * 1994-01-11 1996-10-01 Sgs-Thomson Microelectronics Ltd. Circuit connection in an electrical assembly
WO1996009645A1 (en) * 1994-09-20 1996-03-28 Hitachi, Ltd. Semiconductor device and its mounting structure
US6133639A (en) * 1994-09-20 2000-10-17 Tessera, Inc. Compliant interface for semiconductor chip and method therefor
US6169328B1 (en) 1994-09-20 2001-01-02 Tessera, Inc Semiconductor chip assembly
US6521480B1 (en) 1994-09-20 2003-02-18 Tessera, Inc. Method for making a semiconductor chip package
US6525429B1 (en) 1994-09-20 2003-02-25 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US6723584B2 (en) 1994-09-20 2004-04-20 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US7112879B2 (en) 1995-10-31 2006-09-26 Tessera, Inc. Microelectronic assemblies having compliant layers
US6403882B1 (en) 1997-06-30 2002-06-11 International Business Machines Corporation Protective cover plate for flip chip assembly backside
JP2008171925A (en) * 2007-01-10 2008-07-24 Denso Corp Manufacturing method for bonding structure

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