JPH01235261A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01235261A JPH01235261A JP6286588A JP6286588A JPH01235261A JP H01235261 A JPH01235261 A JP H01235261A JP 6286588 A JP6286588 A JP 6286588A JP 6286588 A JP6286588 A JP 6286588A JP H01235261 A JPH01235261 A JP H01235261A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- silicone gel
- semiconductor chip
- chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 22
- 229920005989 resin Polymers 0.000 abstract description 19
- 239000011347 resin Substances 0.000 abstract description 19
- 238000007789 sealing Methods 0.000 abstract description 12
- 239000000853 adhesive Substances 0.000 abstract description 9
- 230000001070 adhesive effect Effects 0.000 abstract description 9
- 239000000919 ceramic Substances 0.000 abstract description 4
- 229920001721 polyimide Polymers 0.000 abstract description 4
- 239000009719 polyimide resin Substances 0.000 abstract description 4
- 229920002050 silicone resin Polymers 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005219 brazing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000000498 cooling water Substances 0.000 description 2
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052863 mullite Inorganic materials 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910018054 Ni-Cu Inorganic materials 0.000 description 1
- 229910018481 Ni—Cu Inorganic materials 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、フリップチップ型半導体装置に関し、特に、
小型のフリップチップ型半導体装置のパッケージ及びそ
のパッケージング技術に適用して有効な技術に関するも
のである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a flip-chip semiconductor device, and in particular,
The present invention relates to a package for a small flip-chip semiconductor device and a technology that is effective when applied to the packaging technology.
半導体装置において、そのパッケージは、半導体チップ
とぎりぎりに設けることが理想であるが、パッケージの
封止幅が必要である０例えば、半導体チップの周囲にシ
リコーンゲルを注入するためのダムを設けて樹脂注入後
、ダムに機械的保護のためのキャップを取り付けていた
。Ideally, in a semiconductor device, the package should be placed just as close as possible to the semiconductor chip, but the sealing width of the package is required. After injection, the dam was fitted with a cap for mechanical protection.
しかしながら、発明者の検討によれば、既存の技術では
、パッケージの小型化について配慮がされておらず、ダ
ムの大きさの分だけパッケージが大型化するという問題
があった。However, according to the inventor's study, the existing technology does not take into account miniaturization of the package, and there is a problem in that the package becomes larger by the size of the dam.
本発明の目的は、同一の半導体チップに対してその封止
用パッケージを小型にすることができる技術を提供する
ことにある。An object of the present invention is to provide a technique that can reduce the size of a sealing package for the same semiconductor chip.
本発明の他の目的は、半導体装置の実装密度を大きくす
ることができる技術を提供することにある。Another object of the present invention is to provide a technique that can increase the packaging density of semiconductor devices.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、フリップチップ型半導体装置において、少な
くともバンブ電極が設けられている全領域をシリコーン
ゲルのみで覆って封止したものである。That is, in a flip-chip semiconductor device, at least the entire area where bump electrodes are provided is covered and sealed with only silicone gel.
また、半導体チップにバンブ電極を形成する工程と、該
突起電極を配線基板に取り付ける工程と、前記配線基板
の周辺部の外側面全域又はその一部にダム用テープを設
ける工程と、該ダム用テープで囲んだ内部にシリコーン
ゲルを注入する工程と、該シリコーンゲルを加熱硬化す
る工程とからなる半導体装置の製造方法である。Further, a step of forming a bump electrode on a semiconductor chip, a step of attaching the protruding electrode to a wiring board, a step of providing a dam tape on the entire outer surface or a part of the peripheral part of the wiring board, This method of manufacturing a semiconductor device includes a step of injecting silicone gel into an interior surrounded by tape, and a step of curing the silicone gel by heating.
前述の手段によれば、少なくともバンブ電極が設けられ
ている全領域をシリコーンゲルのみで覆って封止するこ
とにより、従来のダムを設けて封止するパッケージに比
べて封止用の幅が不要となるので、同一の半導体チップ
に対してその封止用パッケージを小型にすることができ
る。これにより半導体装置の実装密度を大きくすること
ができる。According to the above-mentioned method, by covering and sealing at least the entire area where the bump electrode is provided with only silicone gel, there is no need for a sealing width compared to a conventional package that is sealed with a dam. Therefore, the sealing package for the same semiconductor chip can be made smaller. This allows the packaging density of semiconductor devices to be increased.
また、前記配線基板の周辺部の外側面全域又はその一部
にダム用テープを設け、該ダム用テープで囲んだ内部に
シリコーンゲルを注入し、該シリコーンゲルを加熱硬化
することにより、パッケージの寸法を大きくすることな
く、バンブ電極が設けられている全領域にシリコーンゲ
ルを容易に配置して封止することができる。In addition, a dam tape is provided on the entire outer surface or a part of the peripheral area of the wiring board, silicone gel is injected into the inside surrounded by the dam tape, and the silicone gel is heated and cured to form a package. Silicone gel can be easily placed and sealed in the entire region where the bump electrode is provided without increasing the dimensions.
以下、本発明の一実施例を図面に基づいて詳細に説明す
る。Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.
なお、実施例を説明するための企図において、同一機能
を有するものは同一符号を付け、その繰り返しの説明は
省略する。In addition, in an attempt to explain the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted.
〔実施例１〕
第１図は、本発明の実施例Ｉの半導体装置の外観概略構
成を示す斜視図であり、第２図は、第１図の■−■線で
切断した断面図である。[Example 1] FIG. 1 is a perspective view showing a schematic external configuration of a semiconductor device according to Example I of the present invention, and FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. .
本実施例Ｉの半導体は、第１図及び第２図において、所
定の配線及び抵抗等の受動素子を組み込んだ外部接続端
子１ａを持つセラミックから成る多層配線基板１に、半
導体チップ３から発生する熱の伝導路を形成するための
熱伝導面積拡大板２を接着剤３ｂで取り付けた半導体チ
ップ３が、半田バンブ電極（バンブ電極）３ａを介して
フリップチップ接続されている。In FIGS. 1 and 2, the semiconductor of this embodiment I is produced from a semiconductor chip 3 onto a multilayer wiring board 1 made of ceramic and having external connection terminals 1a incorporating predetermined wiring and passive elements such as resistors. A semiconductor chip 3 to which a heat conduction area expansion plate 2 for forming a heat conduction path is attached with an adhesive 3b is flip-chip connected via a solder bump electrode (bump electrode) 3a.
更に、多層配線基板１と熱伝導面積拡大板２との間の外
側部には、例えばポリイミド系樹脂からなるダム用樹脂
テープ４（以下、樹脂テープという）が、例えばシリコ
ーン系樹脂からなる接着剤４ａを介して張り渡されて、
キャビティ５が形成され、このキャビティ５の内部にシ
リコーンゲル６が注入され、半田バンブ電極３ａ部が封
止されている。Furthermore, a dam resin tape 4 (hereinafter referred to as resin tape) made of, for example, polyimide resin is placed on the outer side between the multilayer wiring board 1 and the heat conduction area expansion board 2, and an adhesive made of, for example, silicone resin is placed on the outer side between the multilayer wiring board 1 and the heat conduction area expansion board 2. Stretched through 4a,
A cavity 5 is formed, silicone gel 6 is injected into the cavity 5, and the solder bump electrode 3a is sealed.
前記多層配線基板１は、第３図に示すように。The multilayer wiring board 1 is as shown in FIG.
厚膜配線基板（約ｌ鳳ｗ）１０１と薄膜配線部１０２か
らなっている。厚膜配線基板１０１は１例えばムライト
セラミックスからなるグリンシート１０１ａに、例えば
タングステンかなる配線１０１ｂがメタライズされ、各
層間の配線１０１ｂは、スルーホール１０１ｃにより電
気的に接続され、積層された後焼結されて形成される。It consists of a thick film wiring board (approximately 1 inch) 101 and a thin film wiring section 102. The thick film wiring board 101 includes a green sheet 101a made of, for example, mullite ceramics, and a wiring 101b made of, for example, tungsten, which is metallized, and the wiring 101b between each layer is electrically connected by a through hole 101c, and is laminated and then sintered. and formed.
そして、この厚膜配線基板１０１の配線１０１ｂの上に
Ｎｉ−Ｂ１０１ｄをメツキし、その上に例えばアルミニ
ウムからなる第１層目配線１０２ａ（約４μｍ）が設け
られ、その上に例えばポリイミド系樹脂からなる絶縁膜
１０２ｂが設けられ、その上に例えばアルミニウムから
なる第２層目配線１０２ｃ（約４μｍ）が設けられる。Then, Ni-B 101d is plated on the wiring 101b of this thick film wiring board 101, and a first layer wiring 102a (approximately 4 μm) made of, for example, aluminum is provided on top of the Ni-B 101d. An insulating film 102b is provided thereon, and a second layer wiring 102c (approximately 4 μm) made of, for example, aluminum is provided thereon.
そして、第２層目配線１０２ｃと第１層目配線１０２ａ
とがスルーホール１０２ｄを介して電気的に接続される
。同様にして第３層目配線１０２ｅ、第４層目配線１０
２ｆが設けられる。第４層目配線１０２ｆの上にポリイ
ミド系樹脂からなる絶縁膜１０２ｂが設けられた後、ス
ルーホール１０２ｄが設けられ、スルーホール１０２ｄ
を介して第４層目配線１０２ｆの上にＣｒ層（約１ｕｍ
）１０２ｇが設けられ、その上にＮｉ−Ｃｕ層（約１μ
ｍ）１０２ｈが設けられ、その上に半田バンブ電極３ａ
が設けられる。この半田バンブ電極３ａと導体チップ３
の上に設けられている半田バンブ電極３ａとがリフロー
により電気的に接続される。Then, the second layer wiring 102c and the first layer wiring 102a
are electrically connected via the through hole 102d. Similarly, the third layer wiring 102e and the fourth layer wiring 10
2f is provided. After an insulating film 102b made of polyimide resin is provided on the fourth layer wiring 102f, a through hole 102d is provided.
A Cr layer (approximately 1 um thick
) 102g is provided, on which a Ni-Cu layer (approximately 1μ
m) 102h is provided, and a solder bump electrode 3a is provided on it.
is provided. This solder bump electrode 3a and conductor chip 3
The solder bump electrode 3a provided thereon is electrically connected by reflow.
前記熱伝導面積拡大板２は、例えば窒化アルミニウム（
Ａ Ｑ Ｎ）、炭化シリコン（Ｓ ｉ Ｃ：少量のベリ
リアが入っている）等の熱伝導の良い絶縁材料を用いる
。また、熱伝導面積拡大板２と半導体チップ３とを接着
するための接着剤３ｂとしては、例えばＰ ｂ ／ Ｓ
ｎ系（Ｐｂ９０／５ｎｌＯ）の半田、Ａｕ／Ｓｎ（共
晶：Ａｕ８０／５ｎ２０）等のろう材を用いる。The heat conduction area expansion plate 2 is made of, for example, aluminum nitride (
An insulating material with good thermal conductivity, such as silicon carbide (S i C: contains a small amount of beryllia), is used. Further, as the adhesive 3b for bonding the heat conduction area expansion plate 2 and the semiconductor chip 3, for example, P b /S
A brazing material such as n-based (Pb90/5nlO) solder and Au/Sn (eutectic: Au80/5n20) is used.
前記フリップチップ接続では、半田バンブ電極３ａに加
わるひずみがその寿命を低下させる原因となるが、多層
配線基板１と熱伝導面積拡大板２を結合している樹脂テ
ープ４は比較的薄いため、多層配線基板１及び熱伝導面
積拡大板２を引き離す方向の力はほとんど発生しないの
で、半田バンブ電極３ａの樹脂テープ４を取り付けたこ
とによる寿命低下を防止することができる。In the flip-chip connection, the strain applied to the solder bump electrodes 3a causes a reduction in their lifespan, but since the resin tape 4 that connects the multilayer wiring board 1 and the heat conduction area expansion board 2 is relatively thin, the multilayer Since almost no force is generated in the direction of separating the wiring board 1 and the heat conduction area expansion plate 2, it is possible to prevent a decrease in the life of the solder bump electrode 3a due to the attachment of the resin tape 4.
また、樹脂テープ４は、シリコーン系樹脂からなる接着
剤４ａにより目止めがされているため、硬化処理前の流
動性の高いシリコーンゲル６であっても外に漏れ出るこ
とがない、このシリコーンゲル６は脱泡処理後、硬化処
理するが、樹脂テープ４は耐熱性の高い材料であるため
、硬化処理時の高温にも耐えることができる。In addition, since the resin tape 4 is sealed with an adhesive 4a made of silicone resin, this silicone gel does not leak out even if the silicone gel 6 has high fluidity before curing treatment. The resin tape 6 is subjected to a curing process after the defoaming process, and since the resin tape 4 is made of a material with high heat resistance, it can withstand the high temperatures during the curing process.
また、樹脂テープ４は薄いため、多層配線基板１及び熱
伝導面積拡大板２の全周に渡って巻き付けである樹脂テ
ープ４の極一部にシリコーンゲル注入用注射針により穴
をあけてシリコーンゲルを容易に注入することができる
。In addition, since the resin tape 4 is thin, a hole is made in a very small part of the resin tape 4 that is wrapped around the entire circumference of the multilayer wiring board 1 and the heat conductive area expansion plate 2 using a syringe needle for injecting silicone gel. can be easily injected.
次に、本実施例Ｉの半導体装置の組立方法を簡単に説明
する。Next, a method for assembling the semiconductor device of Example I will be briefly described.
まず、半導体ウェハ状態で前記半田バンブ電極３ａが形
成される。その後ダイシングして半導体チップ３が分離
される。この半導体チップ３は、接着剤（ろう材）３ｂ
を３００〜３５０℃の温度で１０秒間熱処理することに
よって熱伝導面精拡大板２に接着される０次に、多層配
線基板１の上に設けられている半田バンブ電極３ａと半
導体チップ３の上に設けられている半田バンブ電極３ａ
とに例えばロジン系のフラックスが塗布された後、両者
の位置合せをして３００℃以上の温度で２分以下の時間
リフローされる。First, the solder bump electrodes 3a are formed on a semiconductor wafer. Thereafter, the semiconductor chips 3 are separated by dicing. This semiconductor chip 3 is made of adhesive (brazing material) 3b
Next, the solder bump electrodes 3a provided on the multilayer wiring board 1 and the semiconductor chip 3 are bonded to the heat conductive surface enlarged plate 2 by heat treatment at a temperature of 300 to 350°C for 10 seconds. Solder bump electrode 3a provided in
After a rosin-based flux is applied to both, the two are aligned and reflowed at a temperature of 300° C. or more for a time of 2 minutes or less.
次に、多層配線基板１と熱伝導面積拡大板２との間の外
側部に、例えばシリコーン系樹脂からなる接着剤４ａが
内側に塗布された、例えばポリイミド系樹脂からなる樹
脂テープ４が張り渡され、機械的に押し付けられて接着
される。この樹脂テープ４により形成されたキャビテイ
５内部に、注射針等でシリコーンゲル６が注入された後
、１５０℃の温度で３０分間ベークし、２００℃の温度
で２時間ポストベークされて半田バンブ電極３ａが封止
される。Next, a resin tape 4 made of, for example, polyimide resin is stretched on the outer side between the multilayer wiring board 1 and the heat conduction area expansion plate 2, and the adhesive 4a made of, for example, silicone resin is applied on the inside. and mechanically pressed and bonded. After silicone gel 6 is injected into the cavity 5 formed by this resin tape 4 using a syringe needle, etc., it is baked at a temperature of 150°C for 30 minutes, and then post-baked at a temperature of 200°C for 2 hours to form a solder bump electrode. 3a is sealed.
また、シリコーンゲル注入をより容易にするため、前記
樹脂テープ４を多層配線基板１及び熱伝導面積拡大板２
の全周に渡っては巻かず、一部を開口部としてもよい、
また、樹脂テープ４はキャビティ５内のシリコーンゲル
硬化後に取り外してもよい。In addition, in order to make silicone gel injection easier, the resin tape 4 is attached to the multilayer wiring board 1 and the heat conductive area expansion plate 2.
It may not be wrapped around the entire circumference, but a portion may be used as an opening.
Further, the resin tape 4 may be removed after the silicone gel in the cavity 5 has hardened.
そして、第４図に示すように、本実施例■の半導体装置
１００は、マルチチップモジュール２００の中に複数個
設けられる。半導体装置１００は、例えばムライト（３
Ａｎ、Ｏ，・２ＳｉＯ，）からなるモジュール基板（セ
ラミック基板）２０１の上に複数個搭載されている。ま
°た、半導体装［１００の熱伝導面積拡大板２の上面に
は、くし歯型下部放熱部材２０３とこれに嵌合するくし
歯型上部放熱部材２０４を介してモジュールキャップ２
０２により冷却されている。モジュールキャップ２０２
は例えば銅（Ｃｕ）とモリブデン（Ｍｏ）の合金からな
り、くし歯型下部放熱部材２０３及びくし歯型上部放熱
部材２０４は例えばアルミニウム（／Ｍｌ）からなって
いる、２０５はモジュールキャップ２０２に設けられて
いる流路であリ、この中を冷却水２０６が流れるように
なっている。モジュールキャップ２０２の側部は、例え
ば半田からなる封止接着剤（ろう材）２０７によってモ
ジュール基板２０１に取り付けられている。２０８はモ
ジュール基板２０１に設けられた入出力ピンである。As shown in FIG. 4, a plurality of semiconductor devices 100 of this embodiment (2) are provided in a multi-chip module 200. The semiconductor device 100 is made of, for example, mullite (3
A plurality of them are mounted on a module substrate (ceramic substrate) 201 made of (An, O, .2SiO,). In addition, the module cap 2 is attached to the upper surface of the heat conduction area expansion plate 2 of the semiconductor device [100] via a comb-shaped lower heat radiating member 203 and a comb-shaped upper heat radiating member 204 that fits therein.
It is cooled by 02. Module cap 202
is made of, for example, an alloy of copper (Cu) and molybdenum (Mo), the comb-shaped lower heat radiating member 203 and the comb-shaped upper heat radiating member 204 are made of, for example, aluminum (/Ml), and 205 is provided on the module cap 202. The cooling water 206 is designed to flow through this channel. The side portion of the module cap 202 is attached to the module substrate 201 with a sealing adhesive (brazing material) 207 made of, for example, solder. 208 is an input/output pin provided on the module board 201.
このマルチチップモジュール２００は、第５図に示した
ように、多層プリント基板３００上に多数実装される。A large number of multi-chip modules 200 are mounted on a multilayer printed circuit board 300, as shown in FIG.
マルチチップモジュール２００の多層プリント基板３０
０上への実装は、前記入出力ピン２０８を多層プリント
基板３００の穴（図示していない）に差し込むか、ある
いはプリント基板３００上に取り付けられたソケットに
入出力ピン２０８を差し込むことにより行う、３０１は
冷却パイプであり、この冷却パイプ３０１から前記モジ
ュールキャップ２０２の流路２０５に前記冷却水２０６
を流すことができるようになっている。Multilayer printed circuit board 30 of multichip module 200
Mounting on the 0 is performed by inserting the input/output pin 208 into a hole (not shown) in the multilayer printed circuit board 300, or by inserting the input/output pin 208 into a socket mounted on the printed circuit board 300. 301 is a cooling pipe, and the cooling water 206 is passed from this cooling pipe 301 to the flow path 205 of the module cap 202.
It is now possible to flow.
以上の説明かられかるように、本実施例によれば、半田
バンブ電極３ａが設けられている全領域をシリコーンゲ
ル６のみで覆って封止することにより、従来のダムを設
けて封止するパッケージに比べて封止用の幅が不要とな
るので、同一の半導体チップ３に対するパッケージを小
型にすることができる。これにより半導体装置の実装密
度を大きくすることができる。As can be seen from the above description, according to this embodiment, the entire area in which the solder bump electrode 3a is provided is covered and sealed only with the silicone gel 6, thereby sealing by providing a conventional dam. Since a sealing width is not required compared to a package, the package for the same semiconductor chip 3 can be made smaller. This allows the packaging density of semiconductor devices to be increased.
また、前記多層配線基板１の周辺部全域にダム用の樹脂
テープ４を張り渡してシリコーンゲル６の収容のための
キャビティ５を形成し、該キャビティ５の内部にシリコ
ーンゲル６を注入し、該シリコーンゲルを加熱硬化する
ことにより、半田バンブ電極３ａが設けられている全領
域に、容易にシリコーンゲル６を配置して封止すること
ができる。Further, a resin tape 4 for a dam is stretched over the entire peripheral area of the multilayer wiring board 1 to form a cavity 5 for accommodating the silicone gel 6, and the silicone gel 6 is injected into the cavity 5. By heating and curing the silicone gel, the silicone gel 6 can be easily placed and sealed in the entire area where the solder bump electrodes 3a are provided.
また、樹脂テープ４を多層配線基板１と半導体チップ３
の熱伝導面積拡大板２との間に張り渡して、シリコーン
ゲル収容用のキャビティ５を形成するため、半田バンブ
電極３ａに引張り応力がほとんどかからず、半田バンブ
電極３ａの劣化を招くことがない、また、パッケージ周
囲を樹脂テープ４で覆ってしまうため、シリコーンゲル
６のにじみ出し及びシリコーンゲルの汚染に対して有利
である。In addition, the resin tape 4 is attached to the multilayer wiring board 1 and the semiconductor chip 3.
Since the cavity 5 for accommodating the silicone gel is formed by extending the solder bump electrode 3a between the solder bump electrode 3a and the heat conduction area expansion plate 2, almost no tensile stress is applied to the solder bump electrode 3a, thereby preventing deterioration of the solder bump electrode 3a. Moreover, since the periphery of the package is covered with the resin tape 4, it is advantageous in preventing the silicone gel 6 from oozing out and contaminating the silicone gel.
これらのことから、半導体装置１００の信頼性を向上す
ることができる。For these reasons, the reliability of the semiconductor device 100 can be improved.
第６図は、本発明の実施例■の半導体装置の概略構成を
説明するための断面図である。FIG. 6 is a sectional view for explaining the schematic structure of a semiconductor device according to Example 2 of the present invention.
本実施例■は、第６図に示すように、前記実施例Ｉの熱
伝導面積拡大板２が取り外されたものである。In this embodiment (2), as shown in FIG. 6, the heat conduction area enlarging plate 2 of the above-mentioned embodiment I is removed.
すなわち、シリコーンゲル６を収容するためのキャビテ
ィ１０は、多層配線基板１の外周部に樹脂テープ４を張
りめぐらすことにより形成される。That is, the cavity 10 for accommodating the silicone gel 6 is formed by wrapping the resin tape 4 around the outer periphery of the multilayer wiring board 1.
このキャビティ１０は、半導体チップ３側に開口部を持
っているので、そのキャビティ１０にシリコーンゲル６
を容易に注入することができる。This cavity 10 has an opening on the semiconductor chip 3 side, so the silicone gel 6 is inserted into the cavity 10.
can be easily injected.
以上、本発明を実施例にもとづき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
は言うまでもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
少なくともバンブ電極が設けられている全領域をシリコ
ーンゲルのみで覆って封止することにより、従来のダム
を設けて封止するパッケージに比べて封止用の幅が不要
となるので、同一の半導体チップに対して、その封止用
パッケージを小型にすることができる。これにより半導
体装置の実装密度を大きくすることができる。By covering and sealing at least the entire area where the bump electrode is provided with silicone gel, there is no need for a sealing width compared to a conventional package that is sealed with a dam, so the same semiconductor The sealing package can be made smaller than the chip. This allows the packaging density of semiconductor devices to be increased.
第１図は、本発明の実施例Ｉの半導体装置の外観概略構
成を示す斜視図、
第２図は、第１図のｎ−ｎ線で切断した断面図、第３図
は、第１図に示す多層配線基板の概略構成を説明するた
めの断面図、
第４図は、第１図に示す半導体装置をマルチチップモジ
ュールに組み込んだ例を示す断面図、第５図は、第４図
に示すマルチチップモジュ−ルを多層プリント基板上に
多数実装した例を示す斜視図、
第６図は、本発明の実施例■の半導体装置の概略構成を
説明するための断面図である。
図中、１・・・多層配線基板、１ａ・・・外部接続端子
、２・・・熱伝導面積拡大板、３・・・半導体チップ、
３ａ・・・半田バンプ電極、４・・・樹脂テープ、３ｂ
、４ａ・・・接着剤、５，１０・・・キャビティ、６・
・・シリコーンゲルである。1 is a perspective view showing a schematic external structure of a semiconductor device according to Example I of the present invention, FIG. 2 is a sectional view taken along line nn in FIG. 1, and FIG. 4 is a sectional view showing an example in which the semiconductor device shown in FIG. 1 is incorporated into a multi-chip module, and FIG. FIG. 6 is a perspective view showing an example in which a large number of the multi-chip modules shown in FIG. 6 are mounted on a multilayer printed circuit board. FIG. In the figure, 1... Multilayer wiring board, 1a... External connection terminal, 2... Heat conduction area expansion plate, 3... Semiconductor chip,
3a...Solder bump electrode, 4...Resin tape, 3b
, 4a... adhesive, 5, 10... cavity, 6.
...It is silicone gel.
Claims (1)
バンプ電極が設けられている全領域をシリコーンゲルの
みで覆って封止したことを特徴とする半導体装置。 ２、フリップチップ型半導体装置において、半導体チッ
プの能動領域と反対の表面に熱伝導面積拡大板を設けた
ことを特徴とする特許請求の範囲第１項に記載の半導体
装置。 ３、半導体チップにバンプ電極を形成する工程と、該突
起電極を配線基板に取り付ける工程と、前記配線基板の
周辺部外側面全域又はその一部にダム用テープを設ける
工程と、該ダム用テープで囲んだ内部にシリコーンゲル
を注入する工程と、該シリコーンゲルを加熱硬化する工
程とからなることを特徴とする半導体装置の製造方法。[Scope of Claims] 1. A flip-chip semiconductor device, characterized in that at least the entire area where bump electrodes are provided is covered and sealed with only silicone gel. 2. A flip-chip semiconductor device according to claim 1, characterized in that a heat conduction area enlarging plate is provided on the surface of the semiconductor chip opposite to the active region. 3. A step of forming bump electrodes on a semiconductor chip, a step of attaching the protruding electrode to a wiring board, a step of providing a dam tape on the entire outer surface of the peripheral part of the wiring board or a part thereof, and the dam tape 1. A method for manufacturing a semiconductor device, comprising the steps of injecting silicone gel into the interior surrounded by the silicone gel, and curing the silicone gel by heating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6286588A JPH01235261A (en) | 1988-03-15 | 1988-03-15 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6286588A JPH01235261A (en) | 1988-03-15 | 1988-03-15 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01235261A true JPH01235261A (en) | 1989-09-20 |
Family
ID=13212614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6286588A Pending JPH01235261A (en) | 1988-03-15 | 1988-03-15 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01235261A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0662732A1 (en) * | 1994-01-11 | 1995-07-12 | STMicroelectronics Limited | Circuit connection in an electrical assembly |
| WO1996009645A1 (en) * | 1994-09-20 | 1996-03-28 | Hitachi, Ltd. | Semiconductor device and its mounting structure |
| KR19990040758A (en) * | 1997-11-19 | 1999-06-05 | 김영환 | Vigie package and its manufacturing method |
| US6133639A (en) * | 1994-09-20 | 2000-10-17 | Tessera, Inc. | Compliant interface for semiconductor chip and method therefor |
| US6169328B1 (en) | 1994-09-20 | 2001-01-02 | Tessera, Inc | Semiconductor chip assembly |
| US6403882B1 (en) | 1997-06-30 | 2002-06-11 | International Business Machines Corporation | Protective cover plate for flip chip assembly backside |
| KR100411810B1 (en) * | 1995-12-27 | 2004-03-31 | 앰코 테크놀로지 코리아 주식회사 | Chip size type semiconductor package using flip chip technique |
| KR100411809B1 (en) * | 1995-12-27 | 2004-03-31 | 앰코 테크놀로지 코리아 주식회사 | Chip size type semiconductor package |
| US7112879B2 (en) | 1995-10-31 | 2006-09-26 | Tessera, Inc. | Microelectronic assemblies having compliant layers |
| JP2008171925A (en) * | 2007-01-10 | 2008-07-24 | Denso Corp | Manufacturing method for bonding structure |
-
1988
- 1988-03-15 JP JP6286588A patent/JPH01235261A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561594A (en) * | 1994-01-11 | 1996-10-01 | Sgs-Thomson Microelectronics Ltd. | Circuit connection in an electrical assembly |
| EP0662732A1 (en) * | 1994-01-11 | 1995-07-12 | STMicroelectronics Limited | Circuit connection in an electrical assembly |
| US6723584B2 (en) | 1994-09-20 | 2004-04-20 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
| WO1996009645A1 (en) * | 1994-09-20 | 1996-03-28 | Hitachi, Ltd. | Semiconductor device and its mounting structure |
| US6133639A (en) * | 1994-09-20 | 2000-10-17 | Tessera, Inc. | Compliant interface for semiconductor chip and method therefor |
| US6169328B1 (en) | 1994-09-20 | 2001-01-02 | Tessera, Inc | Semiconductor chip assembly |
| US6521480B1 (en) | 1994-09-20 | 2003-02-18 | Tessera, Inc. | Method for making a semiconductor chip package |
| US6525429B1 (en) | 1994-09-20 | 2003-02-25 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
| KR100398714B1 (en) * | 1994-09-20 | 2003-11-14 | 가부시끼가이샤 히다치 세이사꾸쇼 | Semiconductor Device and Its Mounting Structure |
| US7112879B2 (en) | 1995-10-31 | 2006-09-26 | Tessera, Inc. | Microelectronic assemblies having compliant layers |
| KR100411810B1 (en) * | 1995-12-27 | 2004-03-31 | 앰코 테크놀로지 코리아 주식회사 | Chip size type semiconductor package using flip chip technique |
| KR100411809B1 (en) * | 1995-12-27 | 2004-03-31 | 앰코 테크놀로지 코리아 주식회사 | Chip size type semiconductor package |
| US6403882B1 (en) | 1997-06-30 | 2002-06-11 | International Business Machines Corporation | Protective cover plate for flip chip assembly backside |
| KR19990040758A (en) * | 1997-11-19 | 1999-06-05 | 김영환 | Vigie package and its manufacturing method |
| JP2008171925A (en) * | 2007-01-10 | 2008-07-24 | Denso Corp | Manufacturing method for bonding structure |
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