JP2006134990A - Semiconductor apparatus - Google Patents

Semiconductor apparatus Download PDF

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JP2006134990A
JP2006134990A JP2004320322A JP2004320322A JP2006134990A JP 2006134990 A JP2006134990 A JP 2006134990A JP 2004320322 A JP2004320322 A JP 2004320322A JP 2004320322 A JP2004320322 A JP 2004320322A JP 2006134990 A JP2006134990 A JP 2006134990A
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electrode
power semiconductor
metal bar
metal
conductor substrate
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JP4635564B2 (en
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Yoshinari Ikeda
良成 池田
Mitsuo Yamashita
満男 山下
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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Abstract

<P>PROBLEM TO BE SOLVED: To efficiently dissipate heat from the top face and underside of a package in the package adopting a laminated structure. <P>SOLUTION: A main electrode for a power semiconductor switching element and an electrode for a diode are brought into contact between a first conductor substrate and a second conductor substrate, respectively, and a first parallel connecting circuit is constituted. The main electrode for the power semiconductor switching element and the electrode for the diode are brought into contact between the second conductor substrate and a third conductor substrate, respectively, and a second parallel connecting circuit is constituted. The first parallel connecting circuit and the second parallel connecting circuit are connected in series through the second conductor substrate and sealed with a resin. The power semiconductor switching element and the diode and each conductor substrate are connected at the shrinkage pressure of the sealing resin. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、複数の縦型半導体素子を同一のパッケージに格納したパワー半導体モジュールなどの半導体装置に関する。   The present invention relates to a semiconductor device such as a power semiconductor module in which a plurality of vertical semiconductor elements are stored in the same package.

ＩＧＢＴ（Insulated Gate bipolar Transistor）やＦＷＤ（Free Wheel Diode）などのパワー半導体素子を複数個同一のパッケージに収納してなるパワー半導体モジュールでは、従来は樹脂ケースのパッケージ構造が主であった。
図５は、パワー半導体モジュールの従来例を示す断面図である。図５において、セラミック基板の両面に銅パターン２１ａ，２１ｂを接合してなる絶縁基板２１の一方の面の銅パターン２１ａ上に、パワー半導体素子としてＩＧＢＴ１１ａ，ＦＷＤ１１ｂ並びに外部導出端子２２を図示しないはんだで接合している。パワー半導体素子と外部導出端子との間は、銅パターン若しくはボンディングワイヤ２３で接続されている。このように、絶縁基板上にパワー半導体素子などを搭載した状態で樹脂ケース２４に格納し、必要に応じて内部に樹脂等の充填材（図示せず）を注入した後、樹脂の蓋２５で覆う。２６は絶縁基板の他方の面の銅パターン２１ｂに接合された放熱ベースである（特許文献１）。 Conventionally, a power semiconductor module in which a plurality of power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and FWDs (Free Wheel Diodes) are housed in the same package has mainly had a resin case package structure.
FIG. 5 is a cross-sectional view showing a conventional example of a power semiconductor module. In FIG. 5, the IGBT 11a, the FWD 11b and the external lead-out terminal 22 as power semiconductor elements are formed on the copper pattern 21a on one surface of the insulating substrate 21 formed by bonding the copper patterns 21a and 21b on both surfaces of the ceramic substrate with solder (not shown). It is joined. The power semiconductor element and the external lead-out terminal are connected by a copper pattern or a bonding wire 23. In this manner, the power semiconductor element and the like are mounted on the insulating substrate and stored in the resin case 24, and a filler (not shown) such as resin is injected into the inside as necessary, and then the resin lid 25 is used. cover. Reference numeral 26 denotes a heat dissipation base bonded to the copper pattern 21b on the other surface of the insulating substrate (Patent Document 1).

上記のパワー半導体モジュールをインバータ装置に組み込んで用いる場合、例えばインバータ装置の１相分に相当する部分をモジュールとして構成すると、図５の構成では、パワー半導体素子を平面的に配置するため、パワー半導体モジュールの底面積が大きくなってしまう。このような底面積の大きなパワー半導体モジュールはインバータ装置に組み込む際においても大きな取り付け面積を必要とするため、結果としてインバータ装置の大型化を招いてしまう。
そこで、パワー半導体モジュールの占有面積を縮小するために、パワー半導体素子を積層する構成が提案されている（特許文献２）。
図６は、パワー半導体モジュールの別の従来例を示す断面図である。図６において、３１は、セラミック基板の一方の面に銅パターン３１ａ，３１ｂが接合された絶縁基板であり、銅パターン３１ａ，３１ｂ上にはんだボール１４’を介してＩＧＢＴ１１Ｎａが、銅パターン３１ｂ上にはんだ１２を介してＦＷＤ１１Ｎｂがそれぞれ接合されている。銅パターン３１ａはＩＧＢＴ１１Ｎａのゲート電極に接続され、図示しない制御端子に接続されている。 When the above power semiconductor module is used by being incorporated in an inverter device, for example, if a portion corresponding to one phase of the inverter device is configured as a module, in the configuration of FIG. The bottom area of the module will increase. Such a power semiconductor module having a large bottom area requires a large mounting area even when incorporated in the inverter device, resulting in an increase in size of the inverter device.
Therefore, a configuration in which power semiconductor elements are stacked has been proposed in order to reduce the area occupied by the power semiconductor module (Patent Document 2).
FIG. 6 is a sectional view showing another conventional example of a power semiconductor module. In FIG. 6, reference numeral 31 denotes an insulating substrate in which copper patterns 31a and 31b are joined to one surface of a ceramic substrate. The IGBT 11Na is placed on the copper patterns 31b via solder balls 14 'on the copper patterns 31a and 31b. FWD11Nb is joined through the solder 12, respectively. The copper pattern 31a is connected to the gate electrode of the IGBT 11Na and is connected to a control terminal (not shown).

ＩＧＢＴ１１Ｎａ，ＦＷＤ１１Ｎｂの他方の面ははんだ１２を介して絶縁基板３２の一方の面に接合された銅パターン３２ｂに接続されている。絶縁基板３２の他方の面には銅パターン３２ａ，３２ｂが接合されていて、両面の銅パターン３２ｂは、絶縁基板３２の中央に形成されたスルーホール３２ｃを介して接続されている。
絶縁基板３２の他方の面に接合された銅パターン３２ａ，３２ｂにははんだボール１４’を介してＩＧＢＴ１１Ｐａが、同じく銅パターン３２ｂにははんだ１２を介してＦＷＤ１１Ｐｂがそれぞれ接合されている。銅パターン３２ａはＩＧＢＴ１１Ｐａのゲート電極に接続され、図示しない制御端子に接続されている。ＩＧＢＴ１１ＰａとＦＷＤ１１Ｐｂの他方の面ははんだ１２を介して金属配線板３３に接合されている。
このように、１相分の上下アームを積層することによって、占有面積を約１／２とすることができ、インバータ装置に組み込む際の取り付け面積を縮小し、インバータ装置を小型化することが可能となる。
特開平8-213547号公報 特開2004-22844号公報 The other surfaces of the IGBTs 11Na and FWD11Nb are connected to a copper pattern 32b bonded to one surface of the insulating substrate 32 via the solder 12. Copper patterns 32 a and 32 b are bonded to the other surface of the insulating substrate 32, and the copper patterns 32 b on both surfaces are connected via a through hole 32 c formed in the center of the insulating substrate 32.
IGBTs 11Pa are joined to the copper patterns 32a and 32b joined to the other surface of the insulating substrate 32 via solder balls 14 ', and FWD 11Pb is joined to the copper patterns 32b via the solder 12, respectively. The copper pattern 32a is connected to the gate electrode of the IGBT 11Pa, and is connected to a control terminal (not shown). The other surfaces of the IGBT 11Pa and the FWD 11Pb are joined to the metal wiring board 33 via the solder 12.
In this way, by stacking the upper and lower arms for one phase, the occupation area can be reduced to about ½, the mounting area when incorporated in the inverter device can be reduced, and the inverter device can be miniaturized. It becomes.
JP-A-8-213547 JP 2004-22844

ＩＧＢＴ等のパワー半導体チップは、スイッチングや導通により発熱するため、パワー半導体モジュールからの放熱対策が欠かせず、また、パワー半導体チップと回路パターンなどの他の部材との接合個所にはヒートサイクルやパワーサイクルに対する信頼性が求められる。
しかしながら、特許文献２に記載された構成では、ＩＧＢＴと絶縁基板の銅パターンとの間の接続にはんだボール１４’が用いられていて、さらに上下アーム（絶縁基板の両面間）の電気的接続を確保するために、絶縁基板内にスルーホール３２ｃを形成している。
このため、はんだボール１４’による接合個所並びに絶縁基板に形成されたスルーホールには、パワー半導体チップの発熱に伴い、パワー半導体チップと銅パターンあるいはセラミック基板との熱膨張係数の相違による応力が絶えず印加されることになり、はんだボール１４’の接合個所の亀裂，剥がれが生じる問題や、絶縁基板に亀裂が発生する問題がある。 Since power semiconductor chips such as IGBT generate heat due to switching or conduction, measures for heat dissipation from the power semiconductor module are indispensable, and heat cycle or Reliability for power cycle is required.
However, in the configuration described in Patent Document 2, the solder ball 14 'is used for connection between the IGBT and the copper pattern of the insulating substrate, and the electrical connection between the upper and lower arms (between both surfaces of the insulating substrate) is further performed. In order to ensure, a through hole 32c is formed in the insulating substrate.
For this reason, the stress due to the difference in thermal expansion coefficient between the power semiconductor chip and the copper pattern or the ceramic substrate is constantly generated in the joining hole by the solder ball 14 ′ and the through hole formed in the insulating substrate as the power semiconductor chip generates heat. As a result, there is a problem that a crack or peeling occurs at a joint portion of the solder ball 14 ′ or a crack occurs in the insulating substrate.

また、ＩＧＢＴと絶縁基板との間にはパッケージ全体を封止する樹脂（エポキシ系の樹脂など）が注入される。パワー半導体チップと絶縁基板との間のはんだボール１４’以外の部分には熱抵抗が大きい樹脂が注入されるため、パッケージの絶縁基板側からの放熱が制限され、十分な放熱を行うことができず、パワー半導体チップの能力を使い切ることができない。
特許文献２の構成では、積層構造を採用することによってパッケージ内の集積度が高まり発熱密度が上昇しているため、放熱（冷却）対策が必要不可欠であるにもかかわらず、十分な冷却ができないため、接合部の長期信頼性を確保することが難しいという課題がある。特にパワー半導体チップの両面をはんだ接合した場合、パワー半導体チップが拘束されることから、はんだ接合部へ印加される応力が大きくなって、接合個所の劣化が加速される。 Further, a resin (such as an epoxy resin) that seals the entire package is injected between the IGBT and the insulating substrate. Since a resin having a high thermal resistance is injected into a portion other than the solder ball 14 'between the power semiconductor chip and the insulating substrate, heat radiation from the insulating substrate side of the package is limited, and sufficient heat radiation can be performed. Therefore, the power semiconductor chip cannot be used up.
In the configuration of Patent Document 2, since the degree of integration in the package is increased and the heat generation density is increased by adopting the laminated structure, sufficient cooling cannot be performed even though a heat dissipation (cooling) measure is indispensable. Therefore, there is a problem that it is difficult to ensure long-term reliability of the joint. In particular, when both surfaces of the power semiconductor chip are solder-bonded, the power semiconductor chip is restrained, so that the stress applied to the solder joint portion is increased and the deterioration of the joint portion is accelerated.

この発明は、上記のパワー半導体モジュールにおける課題に鑑みてなされたものであって、積層構造を採用するパッケージにおいて、半導体チップの上下面における電気的な接続を良好に保ち、半導体チップの上下面並びにパッケージの上下面からの放熱を効率良く行って、半導体装置の信頼性を向上させることを課題とするものである。   The present invention has been made in view of the problems in the power semiconductor module described above, and in a package employing a laminated structure, the electrical connection between the upper and lower surfaces of the semiconductor chip is kept good, and the upper and lower surfaces of the semiconductor chip and It is an object to improve the reliability of a semiconductor device by efficiently radiating heat from the upper and lower surfaces of the package.

前記の課題を解決するため、この発明は、第１の導体基板と第２の導体基板との間にパワー半導体スイッチ素子の主電極ならびにダイオードの電極をそれぞれ接触させてなる第１の並列接続回路と、第２の導体基板と第３の導体基板との間にパワー半導体スイッチ素子の主電極ならびにダイオードの電極をそれぞれ接触させてなる第２の並列接続回路と、第１の並列接続回路と第２の並列接続回路とを、前記第２の導体基板を介して直列接続してなる直列接続回路と、前記第１，第３の導体基板に挟まれた領域であって前記パワー半導体素子ならびにダイオードが配置された部分を封止する封止樹脂と、からなり、前記第１，第３の導体基板を直流入力端子とし、該第２の導体基板を出力端子とするものである（請求項１）。
また、前記パワー半導体素子の主電極ならびにダイオードの電極と対向する導体基板との間の接触は、前記封止樹脂の硬化時の収縮圧力による加圧接触によるものであり（請求項２）、前記導体基板の前記パワー半導体素子の主電極ならびにダイオードの電極と対向する部分に突起が形成されているとよい（請求項３）。 In order to solve the above-described problems, the present invention provides a first parallel connection circuit in which a main electrode of a power semiconductor switch element and an electrode of a diode are brought into contact with each other between a first conductor substrate and a second conductor substrate. A second parallel connection circuit in which the main electrode of the power semiconductor switch element and the electrode of the diode are in contact with each other between the second conductor substrate and the third conductor substrate, a first parallel connection circuit, Two parallel connection circuits connected in series via the second conductor substrate, and a region sandwiched between the first and third conductor substrates, the power semiconductor element and the diode A sealing resin that seals a portion where the first and third conductor substrates are disposed, and the first and third conductor substrates serve as DC input terminals, and the second conductor substrate serves as an output terminal. ).
Further, the contact between the main electrode of the power semiconductor element and the conductive substrate facing the electrode of the diode is due to pressure contact due to contraction pressure during curing of the sealing resin (claim 2), A protrusion may be formed on a portion of the conductor substrate facing the main electrode of the power semiconductor element and the electrode of the diode.

さらに、前記導体基板の樹脂封止される領域であって前記パワー半導体素子ならびにダイオードが配置されていない部分に、前記封止樹脂と嵌合する凹部および／または凸部が形成されているものとし（請求項４）、前記パワー半導体素子およびダイオードの一方の面に形成された電極は、対向する対向する導体基板に接合された構成としてもよい（請求項５）。
ここで、前記第１，第２，第３の導体基板を金属板で構成するか、あるいは、前記第１，第３の導体基板をセラミック基板の両面に金属箔を接合した絶縁基板とし、第２の導体板を金属板で構成することができる。 Furthermore, a concave portion and / or a convex portion that fits with the sealing resin is formed in a portion of the conductor substrate that is resin-sealed and in which the power semiconductor element and the diode are not disposed. (Claim 4) The electrode formed on one surface of the power semiconductor element and the diode may be bonded to an opposing conductive substrate (Claim 5).
Here, the first, second, and third conductive substrates are made of metal plates, or the first and third conductive substrates are insulating substrates in which metal foils are bonded to both surfaces of a ceramic substrate. The two conductor plates can be made of a metal plate.

この発明のパワー半導体モジュールによれば、上下アームを構成するパワー半導体チップを金属バーや絶縁基板で挟み込み、パワー半導体チップの表面に形成された電極とを接触により接続することで、良好な電気的な接続を得るとともに、パッケージの面積を従来の１／２程度まで小型化することができる。また、パワー半導体チップの上下面並びにパッケージの上下面から高効率に放熱を行うことができ、信頼性の高い半導体デバイスの供給が可能となる。   According to the power semiconductor module of the present invention, the power semiconductor chip constituting the upper and lower arms is sandwiched between the metal bar and the insulating substrate, and the electrode formed on the surface of the power semiconductor chip is connected by contact, so that a good electrical In addition to providing a simple connection, the area of the package can be reduced to about half of the conventional size. Further, heat can be radiated with high efficiency from the upper and lower surfaces of the power semiconductor chip and the upper and lower surfaces of the package, and a highly reliable semiconductor device can be supplied.

以下にこの発明を、図に示す実施例に基づいて説明する。   The present invention will be described below based on the embodiments shown in the drawings.

図１はこの発明のパワー半導体モジュールの第１の実施例を示す断面図である。図１において、１１Ｐａ，１１ＮａはＩＧＢＴ、１１Ｐｂ，１１ＮｂはＦＷＤ、１２ははんだ、１３ａ〜１３ｃはパワー半導体モジュールの外部導出端子となる金属バー、１４は金属ボール１４である。金属バー１３の材質としてＣｕ，Ａｌ，Ｆｅあるいはこれらの合金などを用いる。金属バー１３ｂと１３ｃには、ＩＧＢＴ１１ａ，ＦＷＤ１１ｂの表面電極と接触するための突起１３ｂ−１，１３ｂ−２，１３ｃ−１，１３ｃ−２が形成されている。また、金属ボール１４ははんだ１２よりも融点の高い金属コアや、金属コアの周囲にはんだを被覆した金属コアはんだボール、あるいは単なるはんだボールを含む。金属コアを用いたものは、所望のはんだ厚を確保する点で有利である。以下において、これらを金属ボール１４と総称する。   FIG. 1 is a cross-sectional view showing a first embodiment of the power semiconductor module of the present invention. In FIG. 1, 11 Pa and 11 Na are IGBTs, 11 Pb and 11 Nb are FWDs, 12 is solder, 13 a to 13 c are metal bars serving as external lead terminals of the power semiconductor module, and 14 is a metal ball 14. As a material of the metal bar 13, Cu, Al, Fe, or an alloy thereof is used. Protrusions 13b-1, 13b-2, 13c-1, and 13c-2 are formed on the metal bars 13b and 13c to come into contact with the surface electrodes of the IGBTs 11a and FWD11b. The metal ball 14 includes a metal core having a melting point higher than that of the solder 12, a metal core solder ball in which the metal core is coated with solder, or a simple solder ball. The one using a metal core is advantageous in that a desired solder thickness is ensured. Hereinafter, these are collectively referred to as a metal ball 14.

ＩＧＢＴ１１Ｐａのコレクタ電極とＦＷＤ１１Ｐｂのカソード電極は金属バー１３ａにはんだ１２によって接合され、ＩＧＢＴ１１Ｐａエミッタ電極とＦＷＤ１１Ｐｂのアノード電極は金属バー１３ｂの突起１３ｂ−１，１３ｂ−２に接触している。このとき、上記はんだにはＳｎ系のはんだを用い、ＩＧＢＴ１１Ｐａのゲート電極は金属ボール１４を介して金属バー１３ｂ上のゲート配線（図示せず）に接続される。
ここで、金属ボールは、金属バー１３ｂ上のゲート配線に予めはんだ付けしておくのがが望ましい。通常、ＩＧＢＴ１１ａのゲートパッド面積は広くないため、金属バー１３ｂ上のゲート配線にはんだ接合で固定しておいた方が安定する。ただし、ＩＧＢＴ１１ａのゲートパッドにニッケルめっきなどのはんだ接合可能な表面処理がされていれば、金属ボールのゲートパッドへのはんだ付けも可能である。 The collector electrode of the IGBT 11Pa and the cathode electrode of the FWD 11Pb are joined to the metal bar 13a by the solder 12, and the IGBT 11Pa emitter electrode and the anode electrode of the FWD 11Pb are in contact with the protrusions 13b-1 and 13b-2 of the metal bar 13b. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Pa is connected to the gate wiring (not shown) on the metal bar 13b via the metal ball 14.
Here, it is desirable that the metal ball is previously soldered to the gate wiring on the metal bar 13b. Usually, since the gate pad area of the IGBT 11a is not large, it is more stable if it is fixed to the gate wiring on the metal bar 13b by soldering. However, if the IGBT 11a gate pad is subjected to a solderable surface treatment such as nickel plating, the metal ball can be soldered to the gate pad.

なお、上記のゲート配線は金属バー１３ｂの表面に例えばポリイミドなどの樹脂を塗布して２００μｍ程度絶縁層を形成し、該絶縁層上に銅箔等でパターニングして形成すればよい。なお、金属バー１３ｂとして薄板状のヒートパイプを用いてもよい。ヒートパイプを用いることにより、パワー半導体モジュール内部の熱を効果的に放出することができる。
また、ＩＧＢＴ１１Ｎａのコレクタ電極とＦＷＤ１１Ｎｂのカソード電極は金属バー１３ｂにはんだ接合され、エミッタ電極とアノード電極は金属バー１３ｃの突起１３ｃ−１，１３ｃ−２と接触している。このとき、上記はんだにはＳｎ系のはんだを用い、ＩＧＢＴ１１Ｎａのゲート電極は金属ボール１４を介して金属バー１３ｃ上のゲート配線（図示せず）にはんだ接続される。 The gate wiring may be formed by applying a resin such as polyimide on the surface of the metal bar 13b to form an insulating layer of about 200 μm and patterning the insulating layer with a copper foil or the like. In addition, you may use a thin plate-shaped heat pipe as the metal bar 13b. By using the heat pipe, the heat inside the power semiconductor module can be effectively released.
The collector electrode of the IGBT 11Na and the cathode electrode of the FWD 11Nb are soldered to the metal bar 13b, and the emitter electrode and the anode electrode are in contact with the protrusions 13c-1 and 13c-2 of the metal bar 13c. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Na is solder-connected to the gate wiring (not shown) on the metal bar 13c via the metal ball 14.

なお、上記ゲート配線は、上述の金属バー１３ｂの表面に形成したものと同様に、絶縁層を介して銅箔等で形成してもよいし、あるいは、ディスクリート製品で使用されているような金属板を打ち抜き加工したリードフレーム状の金属バー１３ｂを用いてもよい。ゲート配線に相当するパターンも打ち抜き加工されているので、金属バー１３ｂ上の絶縁層は不要である。後述の樹脂封止の後、所望の形状にアウターリード部を切断すればよい。
次に、組立方法について簡単に説明する。金属バー１３ａの所定個所にクリームはんだを塗布し、あるいははんだシートを介してＩＧＢＴ１１Ｐａ，ＦＷＤ１１Ｐｂを載置し、この積層体を加熱炉に投入してはんだを溶融・固化させて両者を接合する。はんだ溶融時にＩＧＢＴ１１ＰａやＦＷＤ１１Ｐｂがずれないよう、図示しない治具を用いるとよい。同様に金属バー１３ｂにＩＧＢＴ１１Ｎａ，ＦＷＤ１１Ｎｂを接合する。 The gate wiring may be formed of copper foil or the like through an insulating layer, similar to that formed on the surface of the metal bar 13b, or a metal used in discrete products. A lead frame-like metal bar 13b obtained by punching a plate may be used. Since the pattern corresponding to the gate wiring is also punched, an insulating layer on the metal bar 13b is unnecessary. What is necessary is just to cut | disconnect an outer lead part in a desired shape after the below-mentioned resin sealing.
Next, the assembly method will be briefly described. Cream solder is applied to a predetermined portion of the metal bar 13a, or IGBTs 11Pa and FWD11Pb are placed via a solder sheet, and this laminated body is put into a heating furnace to melt and solidify the solder to join them. A jig (not shown) may be used so that the IGBT 11Pa and FWD11Pb do not shift when the solder is melted. Similarly, IGBT11Na and FWD11Nb are joined to the metal bar 13b.

つづいて、金属バー１３ａに接合されたＩＧＢＴ１１Ｐａのゲート電極上に金属ボール１４を載置し、ＩＧＢＴ１１Ｐａのエミッタ電極，ＦＷＤ１１Ｐｂのアノード電極が金属バー１３ｂの突起１３ｂ−１，１３ｂ−２にそれぞれ接触するように、金属バー１３ｂを載置する。
同様に金属バー１３ｂに接合されたＩＧＢＴ１１Ｎａのゲート電極上に金属ボール１４を載置し、ＩＧＢＴ１１Ｎａのエミッタ電極，ＦＷＤ１１Ｎｂのアノード電極が金属バー１３ｃの突起１３ｃ−１，１３ｃ−２にそれぞれ接触するように、金属バー１３ｃを載置して、金属バーと金属バーに接合された半導体チップの積層体を形成する。このように、半導体チップの一方の面を予め金属バーに接合しておくことにより、積層体を形成する際の位置合わせが容易となり、次工程の樹脂封止を行う際、封止型への嵌装作業も容易となる。 Subsequently, the metal ball 14 is placed on the gate electrode of the IGBT 11Pa joined to the metal bar 13a, and the emitter electrode of the IGBT 11Pa and the anode electrode of the FWD 11Pb are in contact with the protrusions 13b-1 and 13b-2 of the metal bar 13b, respectively. In this manner, the metal bar 13b is placed.
Similarly, the metal ball 14 is placed on the gate electrode of the IGBT 11Na joined to the metal bar 13b so that the emitter electrode of the IGBT 11Na and the anode electrode of the FWD 11Nb are in contact with the protrusions 13c-1 and 13c-2 of the metal bar 13c, respectively. Then, the metal bar 13c is placed to form a stacked body of metal bars and semiconductor chips bonded to the metal bars. As described above, by bonding one surface of the semiconductor chip to the metal bar in advance, alignment when forming the laminated body becomes easy, and when performing resin sealing in the next process, The fitting work is also facilitated.

つづいて、上記の積層体を封止型に嵌装し、溶融したエポキシ樹脂などの封止樹脂１５を流し込む。樹脂１５は金属バー１３ａと１３ｃとの間であって、半導体チップが実装された領域を封止する。
封止樹脂は硬化時に収縮するため、封止樹脂の収縮に伴う収縮力が発生し、かかる収縮力は金属バー１３ａ，１３ｃをそれぞれモジュール内側へ引き寄せる方向に作用する。従って、半導体チップの電極には金属バーの突起が押圧されることになり、両者は加圧接触され、電気的，熱的に接続される。ちなみに、封止樹脂にエポキシ樹脂を用いた場合、硬化時の温度は２００℃程度であり、室温（２５℃）との間には１７５℃の温度差がある。エポキシ樹脂の線膨張係数を２０ｐｐｍ／℃，ヤング率を２０００ｋｇｆ／ｍｍ２（１９６１３Ｎ／ｍｍ２）とすると、硬化開始から室温までの温度差により、７ｋｇｆ／ｍｍ２（６８．６Ｎ／ｍｍ２）の圧縮応力が印加され、金属バーの突起が半導体チップの電極に押圧される。半導体チップの電極がアルミニウムで形成されている場合、この電極を損傷しないように、アルミニウムの弾性変形の範囲内の圧力とするのが望ましい。 Subsequently, the above laminate is fitted into a sealing mold, and a sealing resin 15 such as a molten epoxy resin is poured. The resin 15 is between the metal bars 13a and 13c and seals the region where the semiconductor chip is mounted.
Since the sealing resin contracts when cured, a contracting force is generated along with the contraction of the sealing resin, and the contracting force acts in the direction of pulling the metal bars 13a and 13c toward the inside of the module. Accordingly, the protrusion of the metal bar is pressed against the electrode of the semiconductor chip, and both are brought into pressure contact and are electrically and thermally connected. Incidentally, when an epoxy resin is used as the sealing resin, the temperature at the time of curing is about 200 ° C., and there is a temperature difference of 175 ° C. from room temperature (25 ° C.). The linear expansion coefficient of the epoxy resin 20 ppm / ° C., when the Young's modulus and 2000kgf / mm 2 (19613N / mm 2), the temperature difference between the curing initiation to room temperature, 7 kgf / mm 2 in (68.6N / mm 2) A compressive stress is applied, and the protrusion of the metal bar is pressed against the electrode of the semiconductor chip. When the electrode of the semiconductor chip is made of aluminum, it is desirable to set the pressure within the range of elastic deformation of aluminum so that the electrode is not damaged.

金属バー１３ｂ，１３ｃに形成された突起（１３ｂ−１，１３ｂ−２，１３ｃ−１，１３ｃ−２）は、対向する半導体チップの表面電極との接触を良好なものとし、かつ表面電極を損傷しないよう、平滑で平坦な形状とするのが好ましい。突起は、金属バー１３ｂ，１３ｃを形成する際にプレス加工によって形成してもよいし、エッチング技術によって所望の高さの突起としてもよい。なお、突起の高さは、半導体チップの電極部以外の表面保護膜を損傷せず、半導体チップの電極部以外の部分との所望の耐圧（沿面距離）を得るために選定すればよく、例えば１００μｍ程度の高さとすればよい。
このようにして、樹脂封止されたパワー半導体モジュールは、半導体チップの表面電極と金属バーが接触状態で積層され、封止樹脂の収縮圧力により加圧接触されている。従って、パワー半導体モジュールの運転（パワー半導体チップの駆動）に伴う発熱によって、モジュール内部の構造体が膨張しても、金属バーとパワー半導体チップとの間が接合されていないため、電極バーはパワー半導体チップの電極面上で収縮することができ、電極面へストレスがかかることがない。 The protrusions (13b-1, 13b-2, 13c-1, 13c-2) formed on the metal bars 13b, 13c make good contact with the surface electrode of the opposing semiconductor chip and damage the surface electrode. In order to avoid this, a smooth and flat shape is preferable. The protrusion may be formed by pressing when forming the metal bars 13b and 13c, or may be a protrusion having a desired height by an etching technique. The height of the protrusion may be selected in order to obtain a desired withstand voltage (creeping distance) with a portion other than the electrode portion of the semiconductor chip without damaging the surface protective film other than the electrode portion of the semiconductor chip. The height may be about 100 μm.
Thus, the resin-sealed power semiconductor module has the surface electrode of the semiconductor chip and the metal bar stacked in contact with each other, and is pressed and contacted by the shrinkage pressure of the sealing resin. Therefore, even if the structure inside the module expands due to heat generated by the operation of the power semiconductor module (drive of the power semiconductor chip), the metal bar and the power semiconductor chip are not joined, so the electrode bar is powered. It can shrink on the electrode surface of the semiconductor chip, and no stress is applied to the electrode surface.

ここで、上記の例では半導体チップの一方の面を予め金属バーに接合し、これを積層して積層体を形成したが、半導体チップと金属バーとの接合を省略し、順次積層して積層体を形成して封止型へ嵌装してもよい。この場合、金属バーの半導体チップの表面電極（エミッタ，コレクタ等）に接触する部分には、それぞれ突起を設けるのが好ましい。に接合工程を簡略化することにより生産性が向上する。また、接合にはんだ接合を用いた場合には、半導体チップと金属バーの熱膨張係数の相違によるひずみが接合部に残る場合があるが、このような熱履歴の影響も避けることができる。
また、封止に用いた樹脂に無機物（アルミナ，窒化アルミ，窒化けい素，炭化けい素など）の微粒子を添加すると、封止樹脂の熱伝導率が高くなり封止樹脂からの放熱に有効である。 Here, in the above example, one surface of the semiconductor chip is bonded to the metal bar in advance and laminated to form a stacked body. However, the bonding between the semiconductor chip and the metal bar is omitted, and the stacked layers are sequentially stacked. A body may be formed and fitted into a sealing mold. In this case, it is preferable to provide a protrusion on each portion of the metal bar that contacts the surface electrode (emitter, collector, etc.) of the semiconductor chip. Moreover, productivity is improved by simplifying the joining process. In addition, when solder bonding is used for bonding, distortion due to the difference in thermal expansion coefficient between the semiconductor chip and the metal bar may remain in the bonded portion, but the influence of such thermal history can also be avoided.
Adding inorganic particles (alumina, aluminum nitride, silicon nitride, silicon carbide, etc.) to the resin used for sealing increases the thermal conductivity of the sealing resin and is effective for heat dissipation from the sealing resin. is there.

上記の積層体を樹脂封止する際に、金属バー１３ａ，１３ｃの半導体チップが接続されていない面を露出するようにすると、半導体チップが発生する熱を露出面より放出しやすくなる。
このように、ＩＧＢＴ１１Ｐａ，ＦＷＤ１１ＰｂとＩＧＢＴ１１Ｎａ，ＦＷＤ１１Ｎｂとを金属バー１３ｂを介して金属バー１３ａ，１３ｃ間に積層し、ＩＧＢＴ１１ＰａとＦＷＤ１１Ｐｂで上（正極側）アーム，ＩＧＢＴ１１ＮａとＦＷＤ１１Ｎｂとで下（負極側）アームを構成し、金属バー１３ａを直流入力（正極），金属バー１３ｂを交流出力，金属バー１３ｃを直流入力（負極）とする１相分のパワー半導体モジュール（２個組み積層型パッケージ）を構成する。
このようなパッケージをインバータ装置などに組み込んで用いる場合は、金属バー１３ａ，１３ｃの露出面に絶縁性があり熱伝導性の高い放熱シート１６を介して放熱フィン１７を接合する。放熱シート１６に粘着性のものを用いれば、放熱フィン１７を容易に取り付けることができる。 When the above-described laminated body is resin-sealed, if the surfaces of the metal bars 13a and 13c that are not connected to the semiconductor chip are exposed, the heat generated by the semiconductor chip is easily released from the exposed surface.
As described above, the IGBT 11Pa and FWD11Pb and the IGBT 11Na and FWD11Nb are stacked between the metal bars 13a and 13c through the metal bar 13b, and the upper (positive electrode side) arm on the IGBT 11Pa and FWD11Pb, and the lower (negative electrode side) on the IGBT 11Na and FWD11Nb. A power semiconductor module (two-packed laminated package) for one phase is constructed, with the arm configured as a DC input (positive electrode) for the metal bar 13a, an AC output for the metal bar 13b, and a DC input (negative electrode) for the metal bar 13c. To do.
When such a package is used in an inverter device or the like, the exposed surfaces of the metal bars 13a and 13c are joined to the heat radiating fins 17 via the heat radiating sheet 16 having insulation and high thermal conductivity. If an adhesive thing is used for the heat-radiation sheet 16, the heat-radiation fin 17 can be attached easily.

ここでは、ＩＧＢＴのコレクタ電極とＦＷＤのカソード電極を金属バーにはんだ接合した構成を例に説明したが、ＩＧＢＴのエミッタ電極，ＦＷＤのアノード電極を金属バーにはんだ接合した構成としてもよい。
また、はんだ接合に替えて超音波接合によって接合してもよい。
図２は、金属バーの形状についての変形例であり、金属バー１３ｃを例に説明したものである。以下の構成は金属バー１３ｃに適用が限られるものではなく、同旨において金属バー１３ａ，１３ｂにも適用が可能であることは勿論である。
図２（ａ）は樹脂封止時の収縮圧力をパワー半導体チップと金属バーとの接触圧力として有効に活用するためのもの例である。図２（ａ）において、１０１は金属バー１３ｃの樹脂が充填される側の面に形成された凹部、１０２は金属バー１３ｃの側面であって封止樹脂によって覆われる部分に形成された凹部である。いずれも、金属バーと封止樹脂とが接する面積を増加させるためのものであり、硬化した封止樹脂が嵌合して強固な密着性を得ることができ、封止樹脂の硬化時の収縮力を効率的に電極面への押圧力とすることができる。 Here, the configuration in which the IGBT collector electrode and the FWD cathode electrode are soldered to the metal bar has been described as an example, but the IGBT emitter electrode and the FWD anode electrode may be soldered to the metal bar.
Moreover, you may join by ultrasonic joining instead of solder joining.
FIG. 2 is a modification example of the shape of the metal bar, and the metal bar 13c is described as an example. The following configuration is not limited to the metal bar 13c, and of course, can be applied to the metal bars 13a and 13b to that effect.
FIG. 2A is an example for effectively utilizing the contraction pressure at the time of resin sealing as the contact pressure between the power semiconductor chip and the metal bar. In FIG. 2A, 101 is a recess formed on the surface of the metal bar 13c that is filled with resin, and 102 is a recess formed on the side surface of the metal bar 13c that is covered with the sealing resin. is there. Both are for increasing the contact area between the metal bar and the sealing resin, and the cured sealing resin can be fitted to obtain strong adhesion, and the shrinkage when the sealing resin is cured The force can be efficiently used as a pressing force to the electrode surface.

凹部１０１は開口部に対して奥行き方向に広がる形状としておくことで密着性を高めることができ、凹部１０２は同様の形状もしくは、図２（ａ）に示すように、凹部のパワー半導体モジュール内側寄りの面が金属バーの側面と鈍角とならないような切り欠きであればよい。
上記の凹部はいずれも、金属バーに対して研削加工や引き抜き，プレスなどで形成することができる。凹部１０１のように開口部を狭くするには、上記のように凹部を形成した後、金属バーの側面から圧力を印加することで開口部を狭くすることが可能である。
図２（ｂ）は樹脂封止時の収縮圧力をパワー半導体チップと金属バーとの接触圧力として有効に活用するためのもの他の例である。図２（ｂ）において、１０３は略Ｔ字状のピンであり、金属バー１３ｃにはんだ１０４で接合されている。ピン１０３により、硬化した封止樹脂が嵌合して強固な密着性を得ることができ、封止樹脂の硬化時の収縮力を効率的に電極面への押圧力とすることができる。 The recess 101 has a shape that expands in the depth direction with respect to the opening, thereby improving the adhesion. The recess 102 has the same shape or a recess closer to the inside of the power semiconductor module as shown in FIG. As long as the surface of the metal bar is not obtuse with the side surface of the metal bar, it is sufficient.
Any of the above-mentioned recesses can be formed on the metal bar by grinding, drawing, pressing, or the like. In order to make the opening narrow like the recess 101, it is possible to make the opening narrow by applying pressure from the side surface of the metal bar after forming the recess as described above.
FIG. 2B is another example for effectively utilizing the contraction pressure at the time of resin sealing as the contact pressure between the power semiconductor chip and the metal bar. In FIG. 2B, reference numeral 103 denotes a substantially T-shaped pin, which is joined to the metal bar 13c by solder 104. By the pin 103, the cured sealing resin can be fitted to obtain strong adhesion, and the shrinkage force when the sealing resin is cured can be efficiently used as the pressing force to the electrode surface.

図２（ｃ）は、ＩＧＢＴのゲート電極と金属バー上に形成されたゲート配線との接続を確実に行うための変形である。金属バー１３ｃに凹部１０５を形成し、絶縁層を介してゲート配線を形成する（ともに図示せず）。凹部１０５に金属ボールが入り込み、ＩＧＢＴのゲート電極との位置決めを容易とし、確実な接続を行うものである。
図２に示した金属バーに対する変形は、適宜組み合わせて行ってもよい。 FIG. 2C is a modification for reliably connecting the gate electrode of the IGBT and the gate wiring formed on the metal bar. A recess 105 is formed in the metal bar 13c, and a gate wiring is formed through an insulating layer (both not shown). A metal ball enters the recess 105 to facilitate positioning with the gate electrode of the IGBT and to perform reliable connection.
The deformation of the metal bar shown in FIG. 2 may be appropriately combined.

図３はこの発明のパワー半導体モジュールの第２の実施例を示す断面図である。図１と同様の構成には同じ符号を付して説明を省略する。図３において、１８，１９はアルミナ，窒化アルミ，窒化けい素等を主材とするセラミック基板の両面に金属箔としての銅パターン１８ａ，１８ｂ，１９ａ，１９ｂが接合された絶縁基板である。絶縁基板１８，１９の一方の面の銅パターン１８ａ，１９ａは、回路パターンとして形成されている。セラミック基板と金属箔との接合には、直接接合を用いてもよいし、ロウ材を介して接合してもよい。
ＩＧＢＴ１１Ｐａのコレクタ電極，ＦＷＤ１１Ｐｂのカソード電極，直流入力端子（Ｐ）となる金属バー１３ｄは、絶縁基板１８の銅パターン１８ａにはんだ接合されている。ＩＧＢＴ１１Ｐａのエミッタ電極とＦＷＤ１１Ｐｂのアノード電極は金属バー１３ｂの突起１３ｂ−１，１３ｂ−２に第１の実施例と同様に接触している。このとき、上記はんだにはＳｎ系のはんだを用いる。
金属バー１３ｂには、ＩＧＢＴ１１Ｐａ，ＦＷＤ１１Ｐｂの表面電極と接触するための突起１３ｂ−１，１３ｂ−２が形成され、絶縁基板１９の銅パターン１９aにもＩＧＢＴ１１Ｎａ，ＦＷＤ１１Ｎｂの表面電極と接触するための突起１９ａ−１，１９ａ−２が形成されている。 FIG. 3 is a cross-sectional view showing a second embodiment of the power semiconductor module of the present invention. The same components as those in FIG. In FIG. 3, reference numerals 18 and 19 denote insulating substrates in which copper patterns 18a, 18b, 19a, and 19b as metal foils are bonded to both surfaces of a ceramic substrate mainly made of alumina, aluminum nitride, silicon nitride, or the like. Copper patterns 18a and 19a on one surface of insulating substrates 18 and 19 are formed as circuit patterns. Direct bonding may be used for bonding the ceramic substrate and the metal foil, or bonding may be performed via a brazing material.
The metal bar 13d that becomes the collector electrode of the IGBT 11Pa, the cathode electrode of the FWD 11Pb, and the DC input terminal (P) is soldered to the copper pattern 18a of the insulating substrate 18. The emitter electrode of the IGBT 11Pa and the anode electrode of the FWD 11Pb are in contact with the protrusions 13b-1 and 13b-2 of the metal bar 13b as in the first embodiment. At this time, Sn solder is used as the solder.
The metal bar 13b is formed with protrusions 13b-1 and 13b-2 for making contact with the surface electrodes of the IGBT 11Pa and FWD11Pb, and the protrusion for making contact with the surface electrode of the IGBT 11Na and FWD11Nb also on the copper pattern 19a of the insulating substrate 19. 19a-1 and 19a-2 are formed.

ＩＧＢＴ１１Ｐａのコレクタ電極とＦＷＤ１１Ｐｂのカソード電極は絶縁基板１８の銅パターン１８ａにはんだ１２によって接合され、ＩＧＢＴ１１Ｐａエミッタ電極とＦＷＤ１１Ｐｂのアノード電極は金属バー１３ｂの突起１３ｂ−１，１３ｂ−２に接触している。このとき、上記はんだにはＳｎ系のはんだを用い、ＩＧＢＴ１１Ｐａのゲート電極は金属ボール１４を介して金属バー１３ｂ上のゲート配線（図示せず）に接続される。このゲート配線は金属バー１３ｂの表面に例えばポリイミドなどの樹脂を塗布して２００μｍ程度絶縁層を形成し、該絶縁層上に銅箔等でパターニングして形成すればよい。なお、金属バー１３ｂとして薄板状のヒートパイプを用いてもよい。ヒートパイプを用いることにより、パワー半導体モジュール内部の熱を効果的に放出することができる。
また、ＩＧＢＴ１１Ｎａのコレクタ電極とＦＷＤ１１Ｎｂのカソード電極は金属バー１３ｂにはんだ接合され、エミッタ電極とアノード電極は金属バー１３ｃの突起１３ｃ−１，１３ｃ−２と接触している。このとき、上記はんだにはＳｎ系のはんだを用い、ＩＧＢＴ１１Ｎａのゲート電極は金属ボール１４を介して金属バー１３ｃ上のゲート配線（図示せず）接続される。 The collector electrode of IGBT11Pa and the cathode electrode of FWD11Pb are joined to the copper pattern 18a of the insulating substrate 18 by solder 12, and the IGBT11Pa emitter electrode and the anode electrode of FWD11Pb are in contact with the protrusions 13b-1 and 13b-2 of the metal bar 13b. . At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Pa is connected to the gate wiring (not shown) on the metal bar 13b via the metal ball 14. The gate wiring may be formed by applying a resin such as polyimide on the surface of the metal bar 13b to form an insulating layer of about 200 μm and patterning the insulating layer with a copper foil or the like. In addition, you may use a thin plate-shaped heat pipe as the metal bar 13b. By using the heat pipe, the heat inside the power semiconductor module can be effectively released.
The collector electrode of the IGBT 11Na and the cathode electrode of the FWD 11Nb are soldered to the metal bar 13b, and the emitter electrode and the anode electrode are in contact with the protrusions 13c-1 and 13c-2 of the metal bar 13c. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Na is connected to the gate wiring (not shown) on the metal bar 13c via the metal ball.

なお、ＩＧＢＴ１１Ｎａのゲートに対応する部分については、パワー半導体モジュール外への引き出し部の図示は省略するが、絶縁基板１９の回路パターンの形成により自在に引き出すことができ、リードフレームを用いた場合に比べ、設計の自由度が高い。
第２実施例のパワー半導体モジュールの組立方法について簡単に説明する。まず、絶縁基板１８の銅パターン１８ａ上にＩＧＢＴ１１Ｐａ，ＦＷＤ１１Ｐｂ，金属バー１３ｄを、をそれぞれ所定の位置に塗布したクリームはんだもしくははんだシートを介して載置し、この積層体をそれぞれ加熱炉に投入し、はんだを溶融・固化させて接合する。はんだ溶融時にＩＧＢＴ１１Ｐａ，ＦＷＤ１１Ｐｂ，金属バー１３ｄがすれないよう、図示しない治具を用いるとよい。同様に金属バー１３ｂにＩＧＢＴ１１Ｎａ，ＦＷＤ１１Ｎｂを接合し、絶縁基板１９の銅パターン１９ａには金属バー１３ｅを接合する。 The portion corresponding to the gate of the IGBT 11Na is not shown in the drawing of the lead-out portion to the outside of the power semiconductor module, but can be pulled out freely by forming a circuit pattern on the insulating substrate 19, and when a lead frame is used. Compared to it, the degree of freedom in design is high.
A method for assembling the power semiconductor module of the second embodiment will be briefly described. First, the IGBT 11Pa, FWD11Pb, and the metal bar 13d are placed on the copper pattern 18a of the insulating substrate 18 via cream solder or solder sheet respectively applied at predetermined positions, and this laminate is put into a heating furnace. The solder is melted and solidified to join. A jig (not shown) may be used so that the IGBT 11Pa, FWD11Pb, and the metal bar 13d are not smeared when the solder is melted. Similarly, IGBT11Na and FWD11Nb are joined to the metal bar 13b, and the metal bar 13e is joined to the copper pattern 19a of the insulating substrate 19.

つづいて、絶縁基板１８の銅パターン１８ａに接合されたＩＧＢＴ１１Ｐａのゲート電極上に金属ボール１４を載置し、ＩＧＢＴ１１Ｐａのエミッタ電極，ＦＷＤ１１Ｐｂのアノード電極が金属バー１３ｂの突起１３ｂ−１，１３ｂ−２にそれぞれ接触するように、金属バー１３ｂを載置する。
同様に金属バー１３ｂに接合されたＩＧＢＴ１１Ｎａのゲート電極上に金属ボール１４を載置し、ＩＧＢＴ１１Ｎａのエミッタ電極，ＦＷＤ１１Ｎｂのアノード電極が絶縁基板１９の銅パターン１９ａの突起１９ａ−１，１９ａ−２にそれぞれ接触するように、金属バー１３ｃを載置して、金属バーと金属バーに接合された半導体チップの積層体を形成する。このように、半導体チップの一方の面を予め金属バー，絶縁基板に接合しておくことにより、積層体を形成する際の位置合わせが容易となり、次工程の樹脂封止を行う際、封止型への嵌装作業も容易となる。 Subsequently, the metal ball 14 is placed on the gate electrode of the IGBT 11Pa joined to the copper pattern 18a of the insulating substrate 18, and the emitter electrode of the IGBT 11Pa and the anode electrode of the FWD 11Pb are the protrusions 13b-1 and 13b-2 of the metal bar 13b. The metal bar 13b is placed so as to come into contact with each other.
Similarly, the metal ball 14 is placed on the gate electrode of the IGBT 11Na joined to the metal bar 13b, and the emitter electrode of the IGBT 11Na and the anode electrode of the FWD 11Nb are formed on the protrusions 19a-1 and 19a-2 of the copper pattern 19a of the insulating substrate 19. A metal bar 13c is placed so as to be in contact with each other, and a stacked body of metal chips and a semiconductor chip bonded to the metal bars is formed. As described above, by bonding one surface of the semiconductor chip to the metal bar and the insulating substrate in advance, the alignment when forming the laminated body is facilitated, and the sealing is performed when the resin sealing is performed in the next process. The fitting work to the mold is also easy.

つづいて、上記の積層体を封止型に嵌装し、溶融したエポキシ樹脂などの封止樹脂１５を流し込む。樹脂１５は絶縁基板１８と１９との間であって、半導体チップが実装された領域を封止する。
封止樹脂は硬化時に収縮するため、封止樹脂の収縮に伴う収縮力が発生し、かかる収縮力は絶縁基板１８，１９をそれぞれモジュール内側へ引き寄せる方向に作用する。従って、半導体チップの電極には金属バー，銅パターンの突起が押圧されることになり、両者は加圧接触され、電気的，熱的に接続される。封止樹脂にエポキシ樹脂を用いた場合、硬化時にその体積が硬化開始時から室温までの温度差による収縮が押圧力となることは、実施例１で述べたとおりである。
金属バー１３ｂ，銅パターン１９ａに形成された突起（１３ｂ−１，１３ｂ−２，１９ａ−１，１９ａ−２）は、対向する半導体チップの表面電極との接触を良好なものとし、かつ表面電極を損傷しないよう、平滑で平坦な形状とするのが好ましい。突起は、金属バー１３ｂを形成する際にプレス加工によって形成してもよいし、エッチング技術によって所望の高さの突起としてもよい。また、プレスやエッチングなどで予め突起を形成した銅パターンをセラミック基板に接合してもよいし、セラミック基板に銅パターンを接合した後にエッチングによって形成してもよい。なお、突起の高さは、半導体チップの電極部以外の表面保護膜を損傷せず、半導体チップの電極部以外の部分との所望の耐圧（沿面距離）を得るために選定すればよく、例えば１００μｍ程度の高さとすればよい。 Subsequently, the above laminate is fitted into a sealing mold, and a sealing resin 15 such as a molten epoxy resin is poured. The resin 15 is between the insulating substrates 18 and 19 and seals the region where the semiconductor chip is mounted.
Since the sealing resin contracts upon curing, a contracting force is generated along with the contraction of the sealing resin, and the contracting force acts in a direction to draw the insulating substrates 18 and 19 toward the inside of the module. Accordingly, the metal bar and the protrusion of the copper pattern are pressed against the electrode of the semiconductor chip, and both are brought into pressure contact and are electrically and thermally connected. As described in Example 1, when an epoxy resin is used as the sealing resin, shrinkage due to a temperature difference from the start of curing to room temperature becomes a pressing force during curing.
The protrusions (13b-1, 13b-2, 19a-1, 19a-2) formed on the metal bar 13b and the copper pattern 19a make good contact with the surface electrode of the opposing semiconductor chip, and the surface electrode In order to prevent damage, it is preferable to have a smooth and flat shape. The protrusion may be formed by pressing when forming the metal bar 13b, or may be a protrusion having a desired height by an etching technique. Further, a copper pattern in which protrusions are formed in advance by pressing or etching may be bonded to the ceramic substrate, or may be formed by etching after bonding the copper pattern to the ceramic substrate. The height of the protrusion may be selected in order to obtain a desired withstand voltage (creeping distance) with a portion other than the electrode portion of the semiconductor chip without damaging the surface protective film other than the electrode portion of the semiconductor chip. The height may be about 100 μm.

このようにして、樹脂封止されたパワー半導体モジュールは、半導体チップの表面電極と金属バーが接触状態で積層され、封止樹脂の収縮圧力により加圧接触されている。従って、パワー半導体モジュールの運転（パワー半導体チップの駆動）に伴う発熱によって、モジュール内部の構造体が膨張しても、金属バーとパワー半導体チップとの間が接合されていないため、電極バーはパワー半導体チップの電極面上で収縮することができ、電極面へストレスがかかることがない。
ここで、上記の例では半導体チップの一方の面を予め絶縁基板の銅パターンならびに金属バーに接合し、これを積層して積層体を形成したが、半導体チップと銅パターン／金属バーとの接合を省略し、順次積層して積層体を形成して封止型へ嵌装してもよい。この場合、銅パターン／金属バーの半導体チップの表面電極（エミッタ，コレクタ等）に接触する部分には、それぞれ突起を設けるのが好ましい。接合工程を簡略化することにより生産性が向上する。また、接合にはんだ接合を用いた場合には、半導体チップと銅パターン／金属バーの熱膨張係数の相違によるひずみが接合部に残る場合があるが、このような熱履歴の影響も避けることができる。 Thus, the resin-sealed power semiconductor module has the surface electrode of the semiconductor chip and the metal bar stacked in contact with each other, and is pressed and contacted by the shrinkage pressure of the sealing resin. Therefore, even if the structure inside the module expands due to heat generated by the operation of the power semiconductor module (drive of the power semiconductor chip), the metal bar and the power semiconductor chip are not joined, so the electrode bar is powered. It can shrink on the electrode surface of the semiconductor chip, and no stress is applied to the electrode surface.
Here, in the above example, one surface of the semiconductor chip is previously bonded to the copper pattern and the metal bar of the insulating substrate, and this is laminated to form a laminate, but the bonding between the semiconductor chip and the copper pattern / metal bar is performed. May be omitted, and a laminated body may be formed sequentially and fitted into a sealing mold. In this case, it is preferable to provide a protrusion on each portion of the copper pattern / metal bar that contacts the surface electrode (emitter, collector, etc.) of the semiconductor chip. Productivity is improved by simplifying the joining process. In addition, when solder bonding is used for bonding, distortion due to the difference in thermal expansion coefficient between the semiconductor chip and the copper pattern / metal bar may remain in the bonded portion, but the influence of such thermal history can be avoided. it can.

また、封止に用いた樹脂に無機物（アルミナ，窒化アルミ，窒化けい素，炭化けい素など）の微粒子を添加すると、封止樹脂の熱伝導率が高くなり封止樹脂からの放熱に有効である。
上記の積層体を樹脂封止する際に、絶縁基板１８，１９の半導体チップが接続されていない面（銅パターン１８ｂ，１９ｂ）を露出するようにすると、半導体チップが発生する熱を露出面より放出しやすくなる。
このように、ＩＧＢＴ１１Ｐａ，ＦＷＤ１１ＰｂとＩＧＢＴ１１Ｎａ，ＦＷＤ１１Ｎｂとを金属バー１３ｂを介して絶縁基板１８，１９間に積層し、ＩＧＢＴ１１ＰａとＦＷＤ１１Ｐｂで上（正極側）アーム，ＩＧＢＴ１１ＮａとＦＷＤ１１Ｎｂとで下（負極側）アームを構成し、金属バー１３ｄを直流入力（正極），金属バー１３ｂを交流出力，金属バー１３ｅを直流入力（負極）とする１相分のパワー半導体モジュール（２個組み積層型パッケージ）を構成する。 Adding inorganic particles (alumina, aluminum nitride, silicon nitride, silicon carbide, etc.) to the resin used for sealing increases the thermal conductivity of the sealing resin and is effective for heat dissipation from the sealing resin. is there.
When the laminated body is resin-sealed, if the surfaces (copper patterns 18b and 19b) of the insulating substrates 18 and 19 to which the semiconductor chips are not connected are exposed, the heat generated by the semiconductor chips is exposed from the exposed surfaces. Easy to release.
In this way, IGBT11Pa, FWD11Pb and IGBT11Na, FWD11Nb are stacked between insulating substrates 18 and 19 via metal bar 13b, and the upper (positive electrode side) arm at IGBT11Pa and FWD11Pb, and the lower (negative electrode side) at IGBT11Na and FWD11Nb. A power semiconductor module (a two-layer stacked package) for one phase is configured, with the arm configured to have the metal bar 13d as a DC input (positive electrode), the metal bar 13b as an AC output, and the metal bar 13e as a DC input (negative electrode). To do.

絶縁基板を用いているため、絶縁基板の露出面（銅パターン１８ｂ，１９ｂ）は内部のとは絶縁が保たれている。このため、このようなパッケージをインバータ装置などに組み込んで用いる場合、第１の実施例で用いた放熱シートは不要である。放熱フィン１７の取り付けにあたっては、封止した樹脂部に放熱フィンの固定用のビス穴（図示せず）を設けてもよい。ビス穴内に金属管を圧入若しくは樹脂に一体に形成することで所望の強度を得ることができる。あるいは、絶縁基板１８側の放熱フィンと絶縁基板１９側の放熱フィンとでパワー半導体モジュールを挟み込み、放熱フィン同士を相互に固定してもよい。特に、２つの放熱フィンでモジュールを挟み込んで締め付ける構成とすれば、封止樹脂の収縮力に加えて、放熱フィンを固定する締め付け力が電極と突起の間に印加され、より良好な接続を得ることができる。   Since an insulating substrate is used, the exposed surfaces (copper patterns 18b and 19b) of the insulating substrate are kept insulated from the inside. For this reason, when using such a package by incorporating it in an inverter device or the like, the heat dissipation sheet used in the first embodiment is not necessary. When attaching the radiating fins 17, screw holes (not shown) for fixing the radiating fins may be provided in the sealed resin portion. A desired strength can be obtained by press-fitting a metal tube into the screw hole or integrally forming the resin tube. Alternatively, the power semiconductor module may be sandwiched between the radiating fins on the insulating substrate 18 side and the radiating fins on the insulating substrate 19 side, and the radiating fins may be fixed to each other. In particular, if the module is sandwiched and tightened by two heat dissipating fins, a tightening force for fixing the heat dissipating fins is applied between the electrode and the protrusion in addition to the shrinkage force of the sealing resin to obtain a better connection. be able to.

ここでは、ＩＧＢＴのコレクタ電極とＦＷＤのカソード電極を金属バーにはんだ接合した構成を例に説明したが、ＩＧＢＴのエミッタ電極，ＦＷＤのアノード電極を金属バーにはんだ接合した構成としてもよい。
また、はんだ接合に替えて超音波接合によって接合してもよい。
図４は、絶縁基板の形状についての変形例であり、絶縁基板１９を例に説明したものである。以下の構成は金属バー１３ｃに適用が限られるものではなく、同旨において絶縁基板１８にも適用が可能であることは勿論である。
図４（ａ）は樹脂封止時の収縮圧力をパワー半導体チップと金属バーとの接触圧力として有効に活用するためのもの例である。図２（ａ）において、２０１は絶縁基板１９の銅パターン１９ａの樹脂が充填される部分の面に形成された凹部である。銅パターンと封止樹脂とが接する面積を増加させるためのものであり、硬化した封止樹脂が嵌合して強固な密着性を得ることができ、封止樹脂の硬化時の収縮力を効率的に電極面への押圧力とすることができる。凹部２０１は開口部に対して奥行き方向に広がる形状としておくことで密着性を高めることができる。 Here, the configuration in which the IGBT collector electrode and the FWD cathode electrode are soldered to the metal bar has been described as an example, but the IGBT emitter electrode and the FWD anode electrode may be soldered to the metal bar.
Moreover, you may join by ultrasonic joining instead of solder joining.
FIG. 4 is a modified example of the shape of the insulating substrate, and the insulating substrate 19 is described as an example. The following configuration is not limited to the metal bar 13c, and can naturally be applied to the insulating substrate 18 to that effect.
FIG. 4A is an example for effectively utilizing the contraction pressure at the time of resin sealing as the contact pressure between the power semiconductor chip and the metal bar. In FIG. 2A, reference numeral 201 denotes a recess formed on the surface of the portion of the insulating substrate 19 where the copper pattern 19a is filled with resin. This is to increase the contact area between the copper pattern and the sealing resin. The hardened sealing resin can be fitted to obtain strong adhesion, and the shrinkage force when the sealing resin is cured is efficient. In particular, the pressing force can be applied to the electrode surface. Adhesion can be enhanced by forming the recess 201 in a shape that extends in the depth direction with respect to the opening.

凹部２０１は、銅パターン１９ａに対して研削加工や引き抜き，プレスなどで形成することができ，図４（ａ）のように開口部を狭くするには、上記のように凹部を形成した後、金属バーの側面から圧力を印加することで開口部を狭くすることが可能である。セラミック基板の破損を防ぐために、銅パターンのセラミック基板への接合前に凹部を形成しておくとよい。
図４（ｂ）は樹脂封止時の収縮圧力をパワー半導体チップと金属バーとの接触圧力として有効に活用するためのもの他の例である。図４（ｂ）において、２０３は略Ｔ字状のピンであり、銅パターン１９ａにはんだ２０４で接合されている。ピン２０３により、硬化した封止樹脂が嵌合して強固な密着性を得ることができ、封止樹脂の硬化時の収縮力を効率的に電極面への押圧力とすることができる。 The recess 201 can be formed on the copper pattern 19a by grinding, drawing, pressing, or the like. To narrow the opening as shown in FIG. 4A, after forming the recess as described above, The opening can be narrowed by applying pressure from the side of the metal bar. In order to prevent damage to the ceramic substrate, it is preferable to form a recess before bonding the copper pattern to the ceramic substrate.
FIG. 4B is another example for effectively utilizing the contraction pressure during resin sealing as the contact pressure between the power semiconductor chip and the metal bar. In FIG. 4B, reference numeral 203 denotes a substantially T-shaped pin, which is joined to the copper pattern 19a by solder 204. The pin 203 allows the hardened sealing resin to be fitted to obtain strong adhesion, and the shrinkage force when the sealing resin is hardened can be efficiently used as the pressing force to the electrode surface.

図４（ｃ）は、ＩＧＢＴのゲート電極と金属バー上に形成されたゲート配線との接続を確実に行うための変形である。銅パターン１９ａに凹部２０５を形成し、絶縁層を介してゲート配線を形成する（ともに図示せず）。凹部２０５に金属ボールが入り込み、ＩＧＢＴのゲート電極との位置決めを容易とし、確実な接続を行うものである。
図４に示した金属バーに対する変形は、適宜組み合わせて行ってもよい。 FIG. 4C is a modification for reliably connecting the gate electrode of the IGBT and the gate wiring formed on the metal bar. A recess 205 is formed in the copper pattern 19a, and a gate wiring is formed through an insulating layer (both not shown). A metal ball enters the recess 205 to facilitate positioning with the gate electrode of the IGBT and to perform reliable connection.
The deformation of the metal bar shown in FIG. 4 may be appropriately combined.

パワー半導体モジュールの第１の実施例を示す断面図である。It is sectional drawing which shows the 1st Example of a power semiconductor module. 金属バーの変形例を示す図である。It is a figure which shows the modification of a metal bar. パワー半導体モジュールの第２の実施例を示す断面図である。It is sectional drawing which shows the 2nd Example of a power semiconductor module. 金属バーの変形例を示す図である。It is a figure which shows the modification of a metal bar. 第１の従来例を示す断面図である。It is sectional drawing which shows a 1st prior art example. 第２の従来例を示す断面図である。It is sectional drawing which shows a 2nd prior art example.

符号の説明Explanation of symbols

１１ａ，１１Ｎａ，１１Ｐａ ＩＧＢＴ
１１ｂ，１１Ｎｂ，１１Ｐｂ ＦＷＤ
１２ はんだ
１３ａ，１３ｂ，１３ｃ，１３ｄ，１３ｅ 金属バー
１４ 金属
１５ 封止樹脂
１６ 放熱シート
１７ 放熱フィン
１８，１９，２１，３１，３２ 絶縁基板
２２ 外部導出端子
２３ ボンディングワイヤ
２４ 樹脂ケース
２５ 蓋
２６ 放熱ベース
２１ａ，２１ｂ，３１ａ，３１ｂ 銅パターン
３２ｃ スルーホール
３３ 金属配線板
１０１，１０２，１０５，２０１，２０５ 凹部
１０３，２０３ ピン 11a, 11Na, 11Pa IGBT
11b, 11Nb, 11Pb FWD
12 Solder 13a, 13b, 13c, 13d, 13e Metal bar 14 Metal 15 Sealing resin 16 Heat radiation sheet 17 Heat radiation fin 18, 19, 21, 31, 32 Insulating substrate 22 External lead-out terminal 23 Bonding wire 24 Resin case 25 Lid 26 Heat radiation Base 21a, 21b, 31a, 31b Copper pattern 32c Through hole 33 Metal wiring board 101, 102, 105, 201, 205 Recess 103, 203 Pin

Claims (5)

第１の導体基板と第２の導体基板との間にパワー半導体スイッチ素子の主電極ならびにダイオードの電極をそれぞれ接触させてなる第１の並列接続回路と、
第２の導体基板と第３の導体基板との間にパワー半導体スイッチ素子の主電極ならびにダイオードの電極をそれぞれ接触させてなる第２の並列接続回路と、
第１の並列接続回路と第２の並列接続回路とを、前記第２の導体基板を介して直列接続してなる直列接続回路と、
前記第１，第３の導体基板に挟まれた領域であって前記パワー半導体素子ならびにダイオードが配置された部分を封止する封止樹脂と、からなり、
前記第１，第３の導体基板を直流入力端子とし、該第２の導体基板を出力端子としたことを特徴とする半導体装置。 A first parallel connection circuit in which a main electrode of a power semiconductor switch element and an electrode of a diode are brought into contact with each other between a first conductor substrate and a second conductor substrate;
A second parallel connection circuit in which the main electrode of the power semiconductor switch element and the electrode of the diode are respectively contacted between the second conductor substrate and the third conductor substrate;
A series connection circuit formed by connecting a first parallel connection circuit and a second parallel connection circuit in series via the second conductor substrate;
A sealing resin that seals a portion where the power semiconductor element and the diode are arranged in a region sandwiched between the first and third conductive substrates,
A semiconductor device characterized in that the first and third conductor substrates are DC input terminals, and the second conductor substrate is an output terminal. 前記パワー半導体素子の主電極ならびにダイオードの電極と対向する導体基板との間の接触は、前記封止樹脂の硬化時の収縮圧力による加圧接触であることを特徴とする請求項１に記載の半導体装置。   2. The contact between the main electrode of the power semiconductor element and the conductive substrate facing the electrode of the diode is a pressure contact due to a contraction pressure when the sealing resin is cured. Semiconductor device. 前記導体基板の前記パワー半導体素子の主電極ならびにダイオードの電極と対向する部分に突起が形成されていることを特徴とする請求項１または請求項２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein a protrusion is formed on a portion of the conductor substrate facing the main electrode of the power semiconductor element and the electrode of the diode. 前記導体基板の樹脂封止される領域であって前記パワー半導体素子ならびにダイオードが配置されていない部分に、前記封止樹脂と嵌合する凹部および／または凸部が形成されていることを特徴とする請求項１乃至請求項３に記載の半導体装置。   A concave portion and / or a convex portion that fits with the sealing resin is formed in a portion of the conductor substrate that is resin-sealed and in which the power semiconductor element and the diode are not disposed. The semiconductor device according to claim 1. 前記パワー半導体素子およびダイオードの一方の面に形成された電極は、対向する対向する導体基板に接合されたものであることを特徴とする請求項１乃至請求項４に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein an electrode formed on one surface of the power semiconductor element and the diode is bonded to an opposing conductive substrate.
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