JP2010147053A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010147053A
JP2010147053A JP2008319392A JP2008319392A JP2010147053A JP 2010147053 A JP2010147053 A JP 2010147053A JP 2008319392 A JP2008319392 A JP 2008319392A JP 2008319392 A JP2008319392 A JP 2008319392A JP 2010147053 A JP2010147053 A JP 2010147053A
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conductive plate
semiconductor device
electrode
semiconductor element
linear expansion
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JP5218009B2 (en
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Yoshinari Ikeda
良成 池田
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability concerning electrical connection of a semiconductor device. <P>SOLUTION: The semiconductor device 1 includes a semiconductor element 20, a conductive plate 30 in contact with an electrode 20a of the semiconductor element 20, and a sealing resin 40 sealing the semiconductor element 20 and the conductive plate 30. The linear expansion coefficient of the sealing resin 40 is adjusted to be smaller than the linear expansion coefficient of the conductive plate 30. According to this semiconductor device 1, a compressive stress arises on the conductive plate 30 when the semiconductor element 20 generates heat. The compressive stress causes the conductive plate 30 and the electrode 20a to come into firm, close contact with each other. Hence the semiconductor device 1 highly reliable in electrical connection is provided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は半導体装置に関し、特にパワー半導体素子を備えた半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a power semiconductor element.

パワーモジュールでは、回路基板上に半導体素子（パワー半導体素子）を半田付けし、当該半導体素子の電極と回路基板の電気的な接続をワイヤボンディングにより実施するのが一般的である。   In a power module, a semiconductor element (power semiconductor element) is generally soldered on a circuit board, and electrical connection between the electrode of the semiconductor element and the circuit board is performed by wire bonding.

また、最近では、ワイヤボンディングによらず、配線経路としてリードフレームを半導体素子の電極、回路基板に半田付けする構成も提供されている（例えば、特許文献１参照）。この方法では、長時間にわたるワイヤボンディング工程を削除できるため、半導体装置の生産性が向上する。
特開２００５−１１６７０２号公報 In addition, recently, a configuration in which a lead frame is soldered to an electrode of a semiconductor element and a circuit board as a wiring path is provided without using wire bonding (see, for example, Patent Document 1). In this method, since the wire bonding process over a long time can be eliminated, the productivity of the semiconductor device is improved.
JP-A-2005-116702

しかしながら、上述したパワーモジュールを作動させると、半導体素子の昇降温が繰り返され、リードフレームの半田接合の部分に常時応力が印加されてしまう。このため、当該接合部分においては、クラックが発生したり、剥離が発生したりする場合もある。   However, when the power module described above is operated, the temperature of the semiconductor element is repeatedly raised and lowered, and stress is always applied to the solder joint portion of the lead frame. For this reason, in the said junction part, a crack generate | occur | produces and peeling may generate | occur | produce.

このように、パワーモジュールでは、半導体素子の電極とリードフレームとの電気的接続に関し、その信頼性が損なわれるという問題があった。
本発明はこのような点に鑑みてなされたものであり、信頼性の高い半導体装置を提供することを目的とする。 Thus, the power module has a problem that the reliability of the electrical connection between the electrode of the semiconductor element and the lead frame is impaired.
The present invention has been made in view of these points, and an object thereof is to provide a highly reliable semiconductor device.

上記課題を解決するために、半導体素子と、前記半導体素子の電極に接触する導電板と、前記半導体素子及び前記導電板とを封止する封止用部材と、を有し、前記封止用部材の線膨張係数が前記導電板の線膨張係数よりも小さいことを特徴とする半導体装置が提供される。   In order to solve the above-described problems, the semiconductor device includes a semiconductor element, a conductive plate that contacts an electrode of the semiconductor element, and a sealing member that seals the semiconductor element and the conductive plate. A semiconductor device is provided in which a member has a linear expansion coefficient smaller than that of the conductive plate.

上記手段によれば、電気的接続に関し、その信頼性の高い半導体装置が実現する。   According to the above means, a highly reliable semiconductor device can be realized with respect to electrical connection.

以下、本実施の形態に係る半導体装置を、図面を参照しながら詳細に説明する。
＜第１の実施の形態＞
図１は第１の実施の形態に係る半導体装置の要部断面模式図である。 Hereinafter, a semiconductor device according to the present embodiment will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a schematic cross-sectional view of an essential part of the semiconductor device according to the first embodiment.

図示する如く、半導体装置（半導体パッケージ）１においては、絶縁基板１０を基体とし、当該絶縁基板１０上に、錫（Ｓｎ）−銀（Ａｇ）系の鉛フリーの半田層１１を介して、少なくとも一つの半導体素子２０が搭載されている。   As shown in the drawing, in a semiconductor device (semiconductor package) 1, at least an insulating substrate 10 is used as a base, and a tin (Sn) -silver (Ag) -based lead-free solder layer 11 is provided on the insulating substrate 10. One semiconductor element 20 is mounted.

ここで、絶縁基板１０は、絶縁板１０ａと、絶縁板１０ａの下面にＤＣＢ（Direct Copper Bonding）法で形成された金属箔１０ｂと、絶縁板１０ａの上面に同じくＤＣＢ法で形成された金属箔１０ｃを備えている。即ち、金属箔１０ｂと金属箔１０ｃは、絶縁板１０ａを隔てて、当該絶縁板１０ａの上下の主面に選択的に配置されている。   Here, the insulating substrate 10 includes an insulating plate 10a, a metal foil 10b formed by a DCB (Direct Copper Bonding) method on the lower surface of the insulating plate 10a, and a metal foil formed by the DCB method on the upper surface of the insulating plate 10a. 10c. That is, the metal foil 10b and the metal foil 10c are selectively arranged on the upper and lower main surfaces of the insulating plate 10a with the insulating plate 10a interposed therebetween.

また、半導体素子２０としては、パワー半導体素子が用いられる。例えば、半導体素子２０として、ＩＧＢＴ（Insulated Gate Bipolar Transistor）素子、パワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等が使用される。また、半導体素子２０は、これらの素子に限られず、ＦＷＤ（Free Wheeling Diode）素子であってもよい。   Further, a power semiconductor element is used as the semiconductor element 20. For example, an IGBT (Insulated Gate Bipolar Transistor) element, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or the like is used as the semiconductor element 20. Further, the semiconductor element 20 is not limited to these elements, and may be an FWD (Free Wheeling Diode) element.

そして、半導体装置１においては、半導体素子２０の一方の電極（裏面電極）２０ｂが半田層１１を介して、金属箔１０ｃに接合している。
また、半導体装置１においては、半導体素子２０の電極２０ｂが配置されている主面とは反対側の主面に配置されている、もう一方の電極（表面電極）２０ａには、リードフレーム、或いはヒートスプレッダとして機能する導電板３０が密接している。 In the semiconductor device 1, one electrode (back electrode) 20 b of the semiconductor element 20 is bonded to the metal foil 10 c through the solder layer 11.
In the semiconductor device 1, the other electrode (surface electrode) 20a disposed on the main surface opposite to the main surface on which the electrode 20b of the semiconductor element 20 is disposed has a lead frame or The conductive plate 30 functioning as a heat spreader is in close contact.

尚、電極２０ｂは、例えば、パワー半導体素子のコレクタ（ドレイン）電極等の主電極が対応し、電極２０ａは、パワー半導体素子のエミッタ（ソース）電極等の主電極、或いはゲート電極等の制御用電極が対応する。   The electrode 20b corresponds to, for example, a main electrode such as a collector (drain) electrode of a power semiconductor element, and the electrode 20a is used for controlling a main electrode such as an emitter (source) electrode of the power semiconductor element or a gate electrode. The electrode corresponds.

また、導電板３０の一部は、ベントされ、当該導電板３０は、凸状（Ω字状）の屈曲部３０ａを備えている。尚、電極２０ａと導電板３０との間には、必要に応じて、導電ペーストを介在させてもよい。   Further, a part of the conductive plate 30 is vented, and the conductive plate 30 includes a convex (Ω-shaped) bent portion 30a. A conductive paste may be interposed between the electrode 20a and the conductive plate 30 as necessary.

また、半導体装置１においては、絶縁基板１０、半導体素子２０及び導電板３０の保護を目的として、絶縁基板１０の主面の少なくとも一部、半導体素子２０及び導電板３０の少なくとも一部を封止用部材である封止用樹脂４０により被覆している。   In the semiconductor device 1, at least a part of the main surface of the insulating substrate 10 and at least a part of the semiconductor element 20 and the conductive plate 30 are sealed for the purpose of protecting the insulating substrate 10, the semiconductor element 20, and the conductive plate 30. It is covered with a sealing resin 40 which is a member for use.

そして、半導体装置１においては、封止用樹脂４０の線膨張係数が導電板３０の線膨張係数よりも低く調整されている。
例えば、導電板３０の線膨張係数は、１６ｐｐｍ／℃以上であり、封止用樹脂４０の線膨張係数は、１５ｐｐｍ／℃以下である。 In the semiconductor device 1, the linear expansion coefficient of the sealing resin 40 is adjusted to be lower than the linear expansion coefficient of the conductive plate 30.
For example, the linear expansion coefficient of the conductive plate 30 is 16 ppm / ° C. or higher, and the linear expansion coefficient of the sealing resin 40 is 15 ppm / ° C. or lower.

このような導電板３０及び封止用樹脂４０の線膨張係数を調節することにより、半導体装置１においては、導電板３０と電極２０ａとの密接状態が維持されている。
そして、導電板３０と電極２０ａとの密接は、例えば、屈曲部３０ａを、例えば、治具（図示しない）等を用いて上方から下方に向かい押圧することによって、電極２０ａに対し導電板３０を加圧接触させながら、半導体素子２０及び導電板３０を封止用樹脂４０により封止することにより達成される。 By adjusting the linear expansion coefficients of the conductive plate 30 and the sealing resin 40 as described above, the close contact state between the conductive plate 30 and the electrode 20a is maintained in the semiconductor device 1.
The conductive plate 30 and the electrode 20a are brought into close contact with each other, for example, by pressing the bent portion 30a downward from above using a jig (not shown) or the like. This is achieved by sealing the semiconductor element 20 and the conductive plate 30 with the sealing resin 40 while making pressure contact.

このような構成であれば、半導体装置１を作動させて、半導体素子２０の発熱により導電板３０が膨張しても、封止用樹脂４０の線膨張係数が導電板３０の線膨張係数より低いことから、導電板３０には圧縮応力が発生する。即ち、半導体装置１の作動中において、導電板３０は、封止用樹脂４０から加圧されることになり、導電板３０と電極２０ａとの密接状態が維持される。   With such a configuration, even when the semiconductor device 1 is operated and the conductive plate 30 expands due to the heat generated by the semiconductor element 20, the linear expansion coefficient of the sealing resin 40 is lower than the linear expansion coefficient of the conductive plate 30. For this reason, compressive stress is generated in the conductive plate 30. That is, during the operation of the semiconductor device 1, the conductive plate 30 is pressurized from the sealing resin 40, and the conductive plate 30 and the electrode 20a are kept in close contact.

例えば、導電板３０としてアルミニウム（Ａｌ）を用いた場合、アルミニウムの線膨張係数は、その純度や用いられる温度範囲にもよるが、２４ｐｐｍ／℃〜２６ｐｐｍ／℃である。ここで、導電板３０が、線膨張係数２６ｐｐｍ／℃でヤング率７０００ｋｇｆ／ｍｍ2のアルミニウムであり、このような導電板３０の周りが、線膨張係数１５ｐｐｍ／℃でヤング率１０００ｋｇｆ／ｍｍ2の封止用樹脂４０で封止されている場合を想定する。この場合、導電板３０には、封止用樹脂４０との線膨張係数差、導電板３０の温度及びヤング率に応じた応力が掛かるようになる。今、温度上昇量が１００℃であると仮定すると、導電板３０と封止用樹脂４０との線膨張係数差が１１ｐｐｍ／℃であり、導電板３０のヤング率が７０００ｋｇｆ／ｍｍ2であることから、導電板３０に掛かる応力は、約８ｋｇｆ／ｍｍ2になる。導電板３０にこの程度の大きさの応力が掛かる場合には、導電板３０を封止用樹脂４０で有効に拘束することができ、導電板３０と電極２０ａとの密接状態を十分に維持することができる。 For example, when aluminum (Al) is used as the conductive plate 30, the linear expansion coefficient of aluminum is 24 ppm / ° C. to 26 ppm / ° C., although it depends on its purity and the temperature range used. Here, the conductive plate 30, a linear expansion coefficient 26 ppm / aluminum having a Young's modulus 7000kgf / mm 2 at ° C., around such conductive plate 30, the Young's modulus of 1000 kgf / mm 2 in the linear expansion coefficient of 15 ppm / ° C. The case where it seals with the resin 40 for sealing is assumed. In this case, the conductive plate 30 is subjected to stress corresponding to the difference in linear expansion coefficient from the sealing resin 40, the temperature of the conductive plate 30, and the Young's modulus. Assuming that the temperature rise is 100 ° C., the difference in linear expansion coefficient between the conductive plate 30 and the sealing resin 40 is 11 ppm / ° C., and the Young's modulus of the conductive plate 30 is 7000 kgf / mm 2. Therefore, the stress applied to the conductive plate 30 is about 8 kgf / mm 2 . When such a large amount of stress is applied to the conductive plate 30, the conductive plate 30 can be effectively restrained by the sealing resin 40, and the conductive plate 30 and the electrode 20a are sufficiently kept in close contact. be able to.

このように、導電板３０より低い線膨張係数の封止用樹脂４０を用いることにより、半導体素子２０の電極２０ａと導電板３０との電気的な接続は、半田材を用いて電極２０ａと導電板３０とを電気的に接続する方法に比べ、その接続信頼性が向上する。   As described above, by using the sealing resin 40 having a lower linear expansion coefficient than that of the conductive plate 30, the electrical connection between the electrode 20 a of the semiconductor element 20 and the conductive plate 30 is performed using a solder material. Compared with the method of electrically connecting the plate 30, the connection reliability is improved.

また、半導体素子２０の電極２０ａと導電板３０との電気的接続に関しては、リフロー処理を必要としない。従って、リフロー処理工程、半田材の使用を省略することができ、半導体装置１の低コスト化を実現することができる。   In addition, no reflow process is required for the electrical connection between the electrode 20a of the semiconductor element 20 and the conductive plate 30. Accordingly, the reflow process and the use of solder material can be omitted, and the cost of the semiconductor device 1 can be reduced.

また、上記電気的接続に係る半田のリフロー処理工程を省略できることから、半導体装置１の熱ダメージが防止される。
尚、上述した絶縁板１０ａの材質は、例えば、窒化珪素（ＳｉＮ）、アルミナ（Ａｌ2Ｏ3）、窒化アルミニウム（ＡｌＮ）の少なくとも何れかを含有するセラミック焼結体が適用される。 In addition, since the solder reflow process for electrical connection can be omitted, the semiconductor device 1 is prevented from being thermally damaged.
The material of the insulating plate 10a described above is, for example, a ceramic sintered body containing at least one of silicon nitride (SiN), alumina (Al 2 O 3 ), and aluminum nitride (AlN).

また、金属箔１０ｂ，１０ｃ、導電板３０の材質は、銅（Ｃｕ）を主成分とする金属が適用される。
また、半田層１１としては、上記の錫（Ｓｎ）−銀（Ａｇ）系の鉛フリーの半田の他に、錫（Ｓｎ）−アンチモン（Ｓｂ）系の鉛フリー半田を用いてもよい。 The metal foils 10b and 10c and the conductive plate 30 are made of a metal having copper (Cu) as a main component.
Further, as the solder layer 11, in addition to the above-described tin (Sn) -silver (Ag) -based lead-free solder, tin (Sn) -antimony (Sb) -based lead-free solder may be used.

また、封止用樹脂４０は、熱硬化性の樹脂であり、樹脂の材質は、例えば、エポキシ樹脂が該当する。
次に、半導体装置の変形例について説明する。尚、以下に例示する図面では、図１と同一の部材には、同一の符号を付している。 Further, the sealing resin 40 is a thermosetting resin, and the resin material corresponds to, for example, an epoxy resin.
Next, modified examples of the semiconductor device will be described. In the drawings exemplified below, the same members as those in FIG. 1 are denoted by the same reference numerals.

＜第２の実施の形態＞
図２及び図３は第２の実施の形態に係る半導体装置の要部断面模式図である。
半導体装置２においては、半導体素子２０の電極２０ａには、上述したように、導電板３０が密接している。また、導電板３０は、屈曲部３０ａを備えている。 <Second Embodiment>
2 and 3 are schematic cross-sectional views of the relevant part of the semiconductor device according to the second embodiment.
In the semiconductor device 2, the conductive plate 30 is in close contact with the electrode 20 a of the semiconductor element 20 as described above. Further, the conductive plate 30 includes a bent portion 30a.

また、半導体装置２においては、絶縁基板１０、半導体素子２０及び導電板３０の保護を目的として、絶縁基板１０の主面の少なくとも一部、半導体素子２０及び導電板３０の少なくとも一部を封止用樹脂４０により被覆している。   In the semiconductor device 2, at least a part of the main surface of the insulating substrate 10 and at least a part of the semiconductor element 20 and the conductive plate 30 are sealed for the purpose of protecting the insulating substrate 10, the semiconductor element 20, and the conductive plate 30. It is covered with resin 40 for use.

また、半導体装置２においては、上述したように、封止用樹脂４０の線膨張係数が導電板３０の線膨張係数よりも低く調整されている。
このような導電板３０及び封止用樹脂４０の線膨張係数を調節することにより、半導体装置２においては、導電板３０と電極２０ａとの密接状態が維持されている。 In the semiconductor device 2, as described above, the linear expansion coefficient of the sealing resin 40 is adjusted to be lower than the linear expansion coefficient of the conductive plate 30.
By adjusting the linear expansion coefficients of the conductive plate 30 and the sealing resin 40 as described above, in the semiconductor device 2, the close contact state between the conductive plate 30 and the electrode 20a is maintained.

そして、当該密接は、例えば、屈曲部３０ａを治具（図示しない）を用いて、上方から下方に向かい押圧することによって、電極２０ａに対し導電板３０を加圧接触させながら、半導体素子２０及び導電板３０を封止用樹脂４０により封止することにより達成される。   For example, the close contact is performed by pressing the bent portion 30a downward from above using a jig (not shown), thereby bringing the conductive plate 30 into pressure contact with the electrode 20a. This is achieved by sealing the conductive plate 30 with the sealing resin 40.

これにより、半導体素子２０の電極２０ａと導電板３０との電気的な接続は、半田材を用いて電極２０ａと導電板３０とを電気的に接続する方法に比べ、その接続信頼性が向上する。   Thereby, the electrical connection between the electrode 20a of the semiconductor element 20 and the conductive plate 30 is improved in connection reliability compared to the method of electrically connecting the electrode 20a and the conductive plate 30 using a solder material. .

また、半導体素子２０の電極２０ａと導電板３０との電気的接続に関しては、リフロー処理を必要としない。従って、リフロー処理工程、半田材の使用を省略することができ、半導体装置２の低コスト化を実現することができる。   In addition, no reflow process is required for the electrical connection between the electrode 20a of the semiconductor element 20 and the conductive plate 30. Therefore, the reflow process and the use of the solder material can be omitted, and the cost reduction of the semiconductor device 2 can be realized.

また、上記電気的接続に係る半田のリフロー処理工程を省略できることから、半導体装置２の熱ダメージが防止される。
特に、半導体装置２においては、電極２０ａに接触させる導電板３０の表面にディンプル加工を施し、導電板３０の当該表面に突起部３０ｂを配置している。即ち、電極２０ａに接触する導電板３０の部分に、突起部３０ｂが形成されている。そして、突起部３０ｂを電極２０ａに圧入している。 Further, since the solder reflow process step related to the electrical connection can be omitted, thermal damage of the semiconductor device 2 is prevented.
In particular, in the semiconductor device 2, dimple processing is performed on the surface of the conductive plate 30 that is in contact with the electrode 20 a, and the protrusion 30 b is disposed on the surface of the conductive plate 30. That is, the protrusion 30b is formed on the portion of the conductive plate 30 that contacts the electrode 20a. The protrusion 30b is press-fitted into the electrode 20a.

これにより、導電板３０と電極２０ａとの接触面積を第１の実施の形態に比べ増大させることができる。また、突起部３０ｂの電極２０ａへの圧入により、導電板３０と電極２０ａとの密接を第１の実施の形態に比べより向上させることができる。   As a result, the contact area between the conductive plate 30 and the electrode 20a can be increased as compared to the first embodiment. Further, the close contact between the conductive plate 30 and the electrode 20a can be improved as compared with the first embodiment by press-fitting the protrusion 30b into the electrode 20a.

このような構成であれば、半導体素子２０の電極２０ａと導電板３０との電気的接続に関し、その接続信頼性をより向上させることができる。
尚、突起部３０ｂの形状は、図２に例示する半球状の突起とは限らない。例えば、図３に例示する三角錐状の突起部３０ｃを導電板３０に備えてもよい。このような突起部３０ｃを導電板３０に備えても、突起部３０ｂを導電板３０に備えた場合と同様の効果が得られる。 With such a configuration, the connection reliability of the electrical connection between the electrode 20a of the semiconductor element 20 and the conductive plate 30 can be further improved.
The shape of the protrusion 30b is not limited to the hemispherical protrusion illustrated in FIG. For example, the conductive plate 30 may include a triangular pyramid-shaped protrusion 30 c illustrated in FIG. 3. Even if such a protrusion 30 c is provided on the conductive plate 30, the same effect as that obtained when the protrusion 30 b is provided on the conductive plate 30 can be obtained.

＜第３の実施の形態＞
図４は第３の実施の形態に係る半導体装置の要部断面模式図である。
半導体装置３においては、絶縁基板１０を基体とし、当該絶縁基板１０上に、半田層１１を介して、半導体素子２０，２１が搭載されている。 <Third Embodiment>
FIG. 4 is a schematic cross-sectional view of the relevant part of a semiconductor device according to the third embodiment.
In the semiconductor device 3, semiconductor elements 20 and 21 are mounted on the insulating substrate 10 via the solder layer 11 with the insulating substrate 10 as a base.

そして、半導体装置３においては、半導体素子２０，２１の一方の電極（裏面電極）２０ｂ，２１ｂが半田層１１を介して、金属箔１０ｃに接合している。
また、半導体素子２０，２１の電極２０ｂ，２１ｂが配置されている主面とは反対側の主面に配置されている、もう一方の電極（表面電極）２０ａ，２１ａには、導電板３０が架橋するように、当該電極２０ａ，２１ａに密接している。尚、導電板３０は、屈曲部３０ａを備えている。 In the semiconductor device 3, one electrode (back electrode) 20 b, 21 b of the semiconductor elements 20, 21 is bonded to the metal foil 10 c through the solder layer 11.
In addition, the conductive plate 30 is disposed on the other electrode (surface electrode) 20a, 21a disposed on the main surface opposite to the main surface on which the electrodes 20b, 21b of the semiconductor elements 20, 21 are disposed. It is in close contact with the electrodes 20a and 21a so as to crosslink. The conductive plate 30 includes a bent portion 30a.

ここで、半導体素子２１は、パワー半導体素子であり、例えば、ＩＧＢＴ素子、パワーＭＯＳＦＥＴ等が該当する。また、半導体素子２１は、ＦＷＤ素子であってもよい。
また、半導体装置３においては、導電板３０の屈曲部３０ａに、銅（Ｃｕ）を主成分とする外部端子３１が密接している。 Here, the semiconductor element 21 is a power semiconductor element, and corresponds to, for example, an IGBT element or a power MOSFET. The semiconductor element 21 may be an FWD element.
In the semiconductor device 3, the external terminal 31 mainly composed of copper (Cu) is in close contact with the bent portion 30 a of the conductive plate 30.

また、半導体装置３においては、絶縁基板１０、半導体素子２０，２１、導電板３０及び外部端子３１の保護を目的として、絶縁基板１０の主面の少なくとも一部、半導体素子２０，２１、導電板３０の少なくとも一部及び外部端子３１の少なくとも一部を封止用樹脂４０により被覆している。   In the semiconductor device 3, for the purpose of protecting the insulating substrate 10, the semiconductor elements 20 and 21, the conductive plate 30 and the external terminals 31, at least a part of the main surface of the insulating substrate 10, the semiconductor elements 20 and 21, the conductive plate At least a part of 30 and at least a part of the external terminal 31 are covered with a sealing resin 40.

また、半導体装置３においては、上述したように、封止用樹脂４０の線膨張係数が導電板３０及び外部端子３１の線膨張係数よりも低く調整されている。例えば、導電板３０及び外部端子３１の線膨張係数は、１６ｐｐｍ／℃以上であり、封止用樹脂４０の線膨張係数は、１５ｐｐｍ／℃以下である。   In the semiconductor device 3, as described above, the linear expansion coefficient of the sealing resin 40 is adjusted to be lower than the linear expansion coefficients of the conductive plate 30 and the external terminal 31. For example, the linear expansion coefficient of the conductive plate 30 and the external terminal 31 is 16 ppm / ° C. or higher, and the linear expansion coefficient of the sealing resin 40 is 15 ppm / ° C. or lower.

このような導電板３０、外部端子３１及び封止用樹脂４０の線膨張係数を調節することにより、半導体装置３においては、導電板３０と電極２０ａ，２１ａとの密接状態、導電板３０と外部端子３１との密接状態が維持されている。   By adjusting the linear expansion coefficients of the conductive plate 30, the external terminal 31, and the sealing resin 40, in the semiconductor device 3, the conductive plate 30 and the electrodes 20 a and 21 a are in close contact with each other. The close contact with the terminal 31 is maintained.

そして、これらの密接は、例えば、外部端子３１を用いて、屈曲部３０ａを上方から下方に向かい押圧することにより、電極２０ａ，２１ａに対し導電板３０を加圧接触させながら、半導体素子２０，２１、導電板３０及び外部端子３１を封止用樹脂４０により封止することにより達成される。   The close contact between the semiconductor element 20 and the semiconductor element 20 can be achieved by pressing the bent portion 30a downward from the upper side using the external terminal 31 to bring the conductive plate 30 into pressure contact with the electrodes 20a and 21a. 21, the conductive plate 30 and the external terminal 31 are sealed with a sealing resin 40.

このような構成であれば、半導体装置３を作動させて、半導体素子２０，２１の発熱により導電板３０及び外部端子３１が膨張しても、封止用樹脂４０の線膨張係数が導電板３０及び外部端子３１の線膨張係数より低いことから、導電板３０及び外部端子３１には圧縮応力が発生する。即ち、半導体装置３の作動中において、導電板３０及び外部端子３１は、封止用樹脂４０から加圧されることになる。その結果、導電板３０と電極２０ａ，２１ａとの密接状態が維持される。また、導電板３０と外部端子３１との密接状態が維持される。   With such a configuration, even when the semiconductor device 3 is operated and the conductive plate 30 and the external terminal 31 expand due to the heat generated by the semiconductor elements 20 and 21, the linear expansion coefficient of the sealing resin 40 is equal to the conductive plate 30. Since the expansion coefficient is lower than the linear expansion coefficient of the external terminal 31, compressive stress is generated in the conductive plate 30 and the external terminal 31. That is, during the operation of the semiconductor device 3, the conductive plate 30 and the external terminal 31 are pressurized from the sealing resin 40. As a result, the close contact between the conductive plate 30 and the electrodes 20a and 21a is maintained. Further, the close contact between the conductive plate 30 and the external terminal 31 is maintained.

これにより、半導体素子２０，２１の電極２０ａ，２１ａと導電板３０との電気的な接続は、半田材を用いて電極２０ａ，２１ａと導電板３０とを電気的に接続する方法に比べ、その接続信頼性が向上する。   As a result, the electrical connection between the electrodes 20a and 21a of the semiconductor elements 20 and 21 and the conductive plate 30 is greater than the method of electrically connecting the electrodes 20a and 21a and the conductive plate 30 using a solder material. Connection reliability is improved.

また、半導体素子２０，２１の電極２０ａ，２１ａと導電板３０との電気的接続に関しては、リフロー処理を要しない。従って、リフロー処理工程、半田材の使用を省略することができ、半導体装置３の低コスト化を実現することができる。   In addition, the electrical connection between the electrodes 20a and 21a of the semiconductor elements 20 and 21 and the conductive plate 30 does not require a reflow process. Therefore, the reflow process and the use of solder material can be omitted, and the cost of the semiconductor device 3 can be reduced.

また、上記電気的接続に係る半田のリフロー処理工程を省略できることから、半導体装置３の熱ダメージが防止される。
＜第４の実施の形態＞
図５は第４の実施の形態に係る半導体装置の要部断面模式図である。 Further, since the solder reflow process step related to the electrical connection can be omitted, the semiconductor device 3 is prevented from being thermally damaged.
<Fourth embodiment>
FIG. 5 is a schematic cross-sectional view of an essential part of a semiconductor device according to the fourth embodiment.

半導体装置４においては、絶縁基板１０を基体とし、当該絶縁基板１０上に、半田層１１を介して、半導体素子２０，２１が搭載されている。
半導体装置４においては、半導体素子２０，２１の電極２０ｂ，２１ｂが半田層１１を介して、金属箔１０ｃに接合している。また、半導体素子２０，２１の電極２０ａ，２１ａには、導電板３０が密接している。尚、導電板３０は、屈曲部３０ａを備えている。 In the semiconductor device 4, semiconductor elements 20 and 21 are mounted on the insulating substrate 10 via the solder layer 11 with the insulating substrate 10 as a base.
In the semiconductor device 4, the electrodes 20 b and 21 b of the semiconductor elements 20 and 21 are bonded to the metal foil 10 c through the solder layer 11. In addition, the conductive plate 30 is in close contact with the electrodes 20 a and 21 a of the semiconductor elements 20 and 21. The conductive plate 30 includes a bent portion 30a.

また、半導体装置４においては、導電板３０の屈曲部３０ａに、銅（Ｃｕ）を主成分とする外部端子３２が密接している。また、外部端子３２の端部３２ｅが屈曲部３０ａを挟持している。   In the semiconductor device 4, the external terminal 32 mainly composed of copper (Cu) is in close contact with the bent portion 30 a of the conductive plate 30. Further, the end portion 32e of the external terminal 32 holds the bent portion 30a.

そして、半導体装置４においては、絶縁基板１０の主面の少なくとも一部、半導体素子２０，２１、導電板３０の少なくとも一部及び外部端子３２の少なくとも一部を、封止用樹脂４０により被覆している。   In the semiconductor device 4, at least a part of the main surface of the insulating substrate 10, the semiconductor elements 20 and 21, at least a part of the conductive plate 30 and at least a part of the external terminal 32 are covered with a sealing resin 40. ing.

また、半導体装置４においては、上述したように、封止用樹脂４０の線膨張係数が導電板３０及び外部端子３２の線膨張係数よりも低く調整されている。例えば、導電板３０及び外部端子３２の線膨張係数は、１６ｐｐｍ／℃以上であり、封止用樹脂４０の線膨張係数は、１５ｐｐｍ／℃以下である。   In the semiconductor device 4, as described above, the linear expansion coefficient of the sealing resin 40 is adjusted to be lower than the linear expansion coefficients of the conductive plate 30 and the external terminal 32. For example, the linear expansion coefficient of the conductive plate 30 and the external terminal 32 is 16 ppm / ° C. or higher, and the linear expansion coefficient of the sealing resin 40 is 15 ppm / ° C. or lower.

このような導電板３０、外部端子３２及び封止用樹脂４０の線膨張係数を調節することにより、半導体装置４においては、導電板３０と電極２０ａ，２１ａとの密接状態、導電板３０と外部端子３２との密接状態が維持されている。   By adjusting the linear expansion coefficients of the conductive plate 30, the external terminal 32, and the sealing resin 40, in the semiconductor device 4, the conductive plate 30 and the electrodes 20 a and 21 a are in close contact, and the conductive plate 30 and the external The close contact with the terminal 32 is maintained.

これらの密接は、例えば、外部端子３２を用いて、屈曲部３０ａを上方から下方に向かい押圧することにより、電極２０ａ，２１ａに対し導電板３０を加圧接触させながら、半導体素子２０，２１、導電板３０及び外部端子３２を封止用樹脂４０により封止することにより達成される。   For example, the close contact of the conductive plate 30 with the electrodes 20a and 21a by pressing the bent portion 30a downward from the upper side using the external terminal 32, while the semiconductor elements 20, 21, This is achieved by sealing the conductive plate 30 and the external terminal 32 with the sealing resin 40.

これにより、半導体素子２０，２１の電極２０ａ，２１ａと導電板３０との電気的な接続は、半田材を用いて電極２０ａ，２１ａと導電板３０とを電気的に接続する方法に比べ、その接続信頼性が向上する。   As a result, the electrical connection between the electrodes 20a and 21a of the semiconductor elements 20 and 21 and the conductive plate 30 is greater than the method of electrically connecting the electrodes 20a and 21a and the conductive plate 30 using a solder material. Connection reliability is improved.

また、半導体素子２０，２１の電極２０ａ，２１ａと導電板３０との電気的接続に関しては、リフロー処理を要しない。従って、リフロー処理工程、半田材の使用を省略することができ、半導体装置４の低コスト化を実現することができる。   In addition, the electrical connection between the electrodes 20a and 21a of the semiconductor elements 20 and 21 and the conductive plate 30 does not require a reflow process. Therefore, the reflow process and the use of solder material can be omitted, and the cost of the semiconductor device 4 can be reduced.

また、上記電気的接続に係る半田のリフロー処理工程を省略できることから、半導体装置４の熱ダメージが防止される。
特に、半導体装置４においては、外部端子３２の端部３２ｅが屈曲部３０ａを挟持していることから、端部３２ｅが封止用樹脂４０により上下の方向から加圧される。これにより、屈曲部３０ａと端部３２ｅとの接触強度がより向上する。 Further, since the solder reflow process step related to the electrical connection can be omitted, thermal damage to the semiconductor device 4 is prevented.
In particular, in the semiconductor device 4, since the end portion 32 e of the external terminal 32 sandwiches the bent portion 30 a, the end portion 32 e is pressurized from above and below by the sealing resin 40. Thereby, the contact strength between the bent portion 30a and the end portion 32e is further improved.

＜第５の実施の形態＞
図６は第５の実施の形態に係る半導体装置の要部断面模式図である。
この図では、導電板３０と外部端子３１との接触状態が例示されている。図示するように、外部端子３１の端部３１ｅには、当該端部３１ｅから延在させた突起部３１ｂが複数本配置され、当該突起部３１ｂが屈曲部３０ａに形成された貫通孔３０ｈに貫通している。 <Fifth embodiment>
FIG. 6 is a schematic cross-sectional view of an essential part of a semiconductor device according to the fifth embodiment.
In this figure, the contact state between the conductive plate 30 and the external terminal 31 is illustrated. As shown in the figure, the end 31e of the external terminal 31 is provided with a plurality of protrusions 31b extending from the end 31e, and the protrusion 31b penetrates through a through hole 30h formed in the bent part 30a. is doing.

このような構成であれば、外部端子３１の端部３１ｅが封止用樹脂４０により加圧されると共に、外部端子３１の導電板３０に対する位置決めが確実になされる。従って、外部端子３１と導電板３０との電気的接続に関し、その信頼性がより向上する。   With such a configuration, the end portion 31 e of the external terminal 31 is pressurized by the sealing resin 40 and the positioning of the external terminal 31 with respect to the conductive plate 30 is ensured. Therefore, the reliability of the electrical connection between the external terminal 31 and the conductive plate 30 is further improved.

第１の実施の形態に係る半導体装置の要部断面模式図である。It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 1st Embodiment. 第２の実施の形態に係る半導体装置の要部断面模式図である（その１）。It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment (the 1). 第２の実施の形態に係る半導体装置の要部断面模式図である（その２）。It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment (the 2). 第３の実施の形態に係る半導体装置の要部断面模式図である。It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 3rd Embodiment. 第４の実施の形態に係る半導体装置の要部断面模式図である。It is a principal part cross-sectional view of the semiconductor device which concerns on 4th Embodiment. 第５の実施の形態に係る半導体装置の要部断面模式図である。It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 5th Embodiment.

符号の説明Explanation of symbols

１，２，３，４ 半導体装置
１０ 絶縁基板
１０ａ 絶縁板
１０ｂ，１０ｃ 金属箔
１１ 半田層
２０，２１ 半導体素子
２０ａ，２０ｂ，２１ａ，２１ｂ 電極
３０ 導電板
３０ａ 屈曲部
３０ｂ，３０ｃ，３１ｂ 突起部
３０ｈ 貫通孔
３１，３２ 外部端子
３１ｅ，３２ｅ 端部
４０ 封止用樹脂 1, 2, 3, 4 Semiconductor device 10 Insulating substrate 10a Insulating plate 10b, 10c Metal foil 11 Solder layer 20, 21 Semiconductor element 20a, 20b, 21a, 21b Electrode 30 Conductive plate 30a Bending portion 30b, 30c, 31b Protruding portion 30h Through hole 31, 32 External terminal 31e, 32e End 40 Sealing resin

Claims (5)

半導体素子と、
前記半導体素子の電極に接触する導電板と、
前記半導体素子及び前記導電板とを封止する封止用部材と、
を有し、前記封止用部材の線膨張係数が前記導電板の線膨張係数よりも小さいことを特徴とする半導体装置。 A semiconductor element;
A conductive plate in contact with the electrode of the semiconductor element;
A sealing member for sealing the semiconductor element and the conductive plate;
And a linear expansion coefficient of the sealing member is smaller than a linear expansion coefficient of the conductive plate. 前記電極に接触する前記導電板に、突起部が形成されていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein a protrusion is formed on the conductive plate in contact with the electrode. 前記封止用部材内において、前記導電板に外部端子が接触し、前記封止用部材の線膨張係数が前記外部端子の線膨張係数よりも小さいことを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein an external terminal is in contact with the conductive plate in the sealing member, and a linear expansion coefficient of the sealing member is smaller than a linear expansion coefficient of the external terminal. . 前記導電板が前記外部端子に挟持されていることを特徴とする請求項３記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the conductive plate is sandwiched between the external terminals. 前記導電板に接触する前記外部端子に、別の突起部が形成され、前記導電板に設けられた貫通孔に前記別の突起部が貫通していることを特徴とする請求項３記載の半導体装置。   4. The semiconductor according to claim 3, wherein another projection is formed on the external terminal that contacts the conductive plate, and the another projection penetrates a through hole provided in the conductive plate. apparatus.
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