JP2009076592A - Method of crimping electrode of semiconductor device and heat slinger - Google Patents

Method of crimping electrode of semiconductor device and heat slinger Download PDF

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JP2009076592A
JP2009076592A JP2007242718A JP2007242718A JP2009076592A JP 2009076592 A JP2009076592 A JP 2009076592A JP 2007242718 A JP2007242718 A JP 2007242718A JP 2007242718 A JP2007242718 A JP 2007242718A JP 2009076592 A JP2009076592 A JP 2009076592A
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electrode
lower electrode
crimping
jig
semiconductor elements
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Satoru Sasaki
悟 佐々木
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Toyota Motor Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of uniformly crimping one electrode of a semiconductor device and a heat slinger, while being able to prevent the semiconductor device from being damaged without using any spacer and any hole, when a plurality of the semiconductor devices are pinched by an upper electrode and a lower electrode and one electrode of the upper electrode and the lower electrode is crimped to the heat slinger. <P>SOLUTION: In a method of crimping one electrode of semiconductor devices 25, 26 and a heat slinger 21 wherein a plurality of the semiconductor devices 25, 26 are pinched by an upper electrode 27 and a lower electrode 23 and one electrode of the upper electrode 27 and the lower electrode 23 is crimped to the heat slinger 21, an auxiliary crimping jig 51 is inserted between the plurality of semiconductor devices 25, 26, and there is equipped a crimping jig 52 engaged with peripheries of one electrode and the auxiliary crimping jig 51 while forming and surrounding gaps between the plurality of semiconductor devices 25, 26 and the other electrode, and one electrode is crimped to the heat slinger 21 by pushing the crimping jig 52. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、複数の半導体素子を上部電極と下部電極とにより挟持し、上部電極および下部電極のうち何れか一方の電極を放熱板へ圧着する半導体素子の電極と放熱板との圧着方法に関する。   The present invention relates to a method for crimping a semiconductor element electrode and a radiator plate, wherein a plurality of semiconductor elements are sandwiched between an upper electrode and a lower electrode, and one of the upper electrode and the lower electrode is crimped to a radiator plate.

従来から、IGBT等のパワー半導体素子の上下に放熱板を配置して放熱性を向上させると共に、上下の放熱板の間にスペーサを設置してモールド型の型締めによる半導体素子の損傷を防止する半導体装置が知られている(例えば、特許文献1)。   2. Description of the Related Art Conventionally, a semiconductor device has been disclosed in which a heat sink is disposed above and below a power semiconductor element such as an IGBT to improve heat dissipation, and a spacer is provided between the upper and lower heat sinks to prevent damage to the semiconductor element due to mold clamping. Is known (for example, Patent Document 1).

図5は、従来の半導体装置の構成の一例を示した断面図である。この半導体装置1では、平行に配置した下側放熱板5および上側放熱板8の間に、半導体素子2および半導体素子3のそれぞれに近接して干渉しない位置に、円柱状等のスペーサ9を複数設けている。これらのスペーサ9は、下側および上側放熱板5、8の間に半導体素子2および3を挟んだ状態で、これらを樹脂モールドする際にそのモールド型の型締め力(圧縮力)を半導体素子2、3に代わって受けとめる受圧部(抵抗部)としての機能をなし、これによって半導体素子2、3の損傷を防ぎつつ、十分な型締め力を加えることができる。尚、図5において、6、7は電極ブロック、4は半田である。
特開2004−303900号公報
FIG. 5 is a cross-sectional view showing an example of the configuration of a conventional semiconductor device. In the semiconductor device 1, a plurality of spacers 9 such as a columnar shape are provided between the lower heat radiating plate 5 and the upper heat radiating plate 8 arranged in parallel at positions where they do not interfere with each of the semiconductor elements 2 and 3. Provided. When these spacers 9 are resin-molded with the semiconductor elements 2 and 3 sandwiched between the lower and upper radiator plates 5 and 8, the mold clamping force (compression force) of the mold die is applied to the semiconductor elements. It functions as a pressure receiving portion (resistor portion) that can be received instead of 2 and 3, whereby a sufficient clamping force can be applied while preventing damage to the semiconductor elements 2 and 3. In FIG. 5, 6 and 7 are electrode blocks, and 4 is solder.
JP 2004-303900 A

しかしながら、上記従来の半導体装置は、上下の放熱板5、8の間隙に複数のスペーサ9を挿入すると共に、上下の放熱板5、8にスペーサ9を嵌合して位置決めする穴(凹部)10、11を複数設置する必要がある。このため、再利用不可能な複数のスペーサ9と、上下の放熱板5、8の穴加工とが必要なる。したがって、上記従来の半導体装置の製造方法を、本発明の半導体素子の電極と放熱板との圧着方法に適用しようとすると、再利用不可能な複数のスペーサと、上部電極および下部電極の穴加工とが必要になり、作業が繁雑になると共に、コストが増加する。   However, in the above conventional semiconductor device, a plurality of spacers 9 are inserted into the gaps between the upper and lower heat sinks 5 and 8, and the holes (recesses) 10 for fitting and positioning the spacers 9 on the upper and lower heat sinks 5 and 8. , 11 need to be installed. For this reason, a plurality of spacers 9 that cannot be reused and the drilling of the upper and lower heat sinks 5 and 8 are required. Therefore, when the above-described conventional method for manufacturing a semiconductor device is applied to the method for crimping the electrode of the semiconductor element and the heat sink of the present invention, a plurality of non-reusable spacers and the drilling of the upper and lower electrodes And the work becomes complicated and the cost increases.

本発明は、上記の点に鑑みてなされたものであって、複数の半導体素子を上部電極と下部電極により挟持し、上部電極および下部電極のうち何れか一方の電極を放熱板へ圧着する際、スペーサや穴を用いることなく、半導体素子の損傷を防止できると共に、半導体素子の一方の電極と放熱板とを均一に圧着できる圧着方法を提供することを目的とする。   The present invention has been made in view of the above points. When a plurality of semiconductor elements are sandwiched between an upper electrode and a lower electrode, and one of the upper electrode and the lower electrode is pressure-bonded to a heat radiating plate. An object of the present invention is to provide a crimping method that can prevent damage to a semiconductor element without using a spacer or a hole, and that can uniformly crimp one electrode of the semiconductor element and a heat sink.

前記目的を達成するため、本発明は、複数の半導体素子を上部電極と下部電極とにより挟持し、前記上部電極および前記下部電極のうち何れか一方の電極を放熱板へ圧着する半導体素子の電極と放熱板との圧着方法において、
前記複数の半導体素子間に補助圧着治具を挿入し、前記複数の半導体素子および他方の電極と間隙を形成すると共に前記一方の電極の周縁および前記補助圧着治具に係合する圧着治具を装着し、前記圧着治具を押圧して前記一方の電極を前記放熱板へ圧着する。
In order to achieve the above object, the present invention provides an electrode of a semiconductor element in which a plurality of semiconductor elements are sandwiched between an upper electrode and a lower electrode, and one of the upper electrode and the lower electrode is crimped to a heat sink. In the method of crimping the heat sink and
An auxiliary crimping jig is inserted between the plurality of semiconductor elements to form a gap with the plurality of semiconductor elements and the other electrode, and a crimping jig is engaged with the peripheral edge of the one electrode and the auxiliary crimping jig. Attach and press the crimping jig to crimp the one electrode to the heat sink.

本発明によれば、複数の半導体素子および他方の電極と間隙を形成しつつ囲繞すると共に一方の電極の周縁および補助圧着治具に係合する圧着治具を押圧して、複数の半導体素子および他方の電極を押圧することなく、一方の電極の周縁および複数の半導体素子間を押圧することができる。これにより、スペーサや穴を用いることなく、半導体素子の損傷を防止できると共に、半導体素子の一方の電極と放熱板とを均一に圧着することができる。尚、補助圧着治具、圧着治具は、再利用できる。   According to the present invention, a plurality of semiconductor elements and a plurality of semiconductor elements and the other electrode are surrounded by forming a gap and pressing a crimping jig engaging with a peripheral edge of one electrode and an auxiliary crimping jig. Without pressing the other electrode, it is possible to press the periphery of one electrode and between a plurality of semiconductor elements. Accordingly, damage to the semiconductor element can be prevented without using a spacer or a hole, and one electrode of the semiconductor element and the heat radiating plate can be uniformly bonded. The auxiliary crimping jig and the crimping jig can be reused.

以下、図面を参照して、本発明を実施するための最良の形態の説明を行う。   The best mode for carrying out the present invention will be described below with reference to the drawings.

図1は、半導体装置の基本構成の一例を示した断面図である。   FIG. 1 is a cross-sectional view illustrating an example of a basic configuration of a semiconductor device.

この半導体装置の基本構成は、図1に示すように、放熱板21上に、絶縁シート22、下部電極23、第1半田層24a、第1半導体素子25(第2半導体素子26)、第2半田層24b、上部電極27を積層して構成される。つまり、第1半導体素子25、および第2半導体素子26(以下、半導体素子25、26)は、第1半田層24aおよび第2半田層24b(以下、半田層24a、24b)を介して、下部電極23と上部電極27とにより挟持されている。   As shown in FIG. 1, the basic configuration of this semiconductor device includes an insulating sheet 22, a lower electrode 23, a first solder layer 24 a, a first semiconductor element 25 (second semiconductor element 26), and a second on a heat sink 21. The solder layer 24b and the upper electrode 27 are laminated. In other words, the first semiconductor element 25 and the second semiconductor element 26 (hereinafter referred to as semiconductor elements 25 and 26) are disposed below the first solder layer 24a and the second solder layer 24b (hereinafter referred to as solder layers 24a and 24b). It is sandwiched between the electrode 23 and the upper electrode 27.

第1半導体素子25は、例えば、IGBT、パワーMOSFET等のパワー半導体素子である。第1半導体素子25は、IGBTの場合、下面にコレクタ電極(図示せず)を備え、上面にエミッタ電極(図示せず)、及びゲート電極(図示せず)を備える。   The first semiconductor element 25 is a power semiconductor element such as an IGBT or a power MOSFET, for example. In the case of an IGBT, the first semiconductor element 25 includes a collector electrode (not shown) on the lower surface, and an emitter electrode (not shown) and a gate electrode (not shown) on the upper surface.

エミッタ電極及びゲート電極は、IGBT25の上面の互いに隔離された領域に、Alを積層して形成される。エミッタ電極は、第2半田層24bを介して上部電極27へ電気的に接続されており、ゲート電極は、ボンディングワイヤ(図示せず)を介して外部電極(図示せず)へ電気的に接続されている。   The emitter electrode and the gate electrode are formed by laminating Al in regions isolated from each other on the upper surface of the IGBT 25. The emitter electrode is electrically connected to the upper electrode 27 via the second solder layer 24b, and the gate electrode is electrically connected to the external electrode (not shown) via a bonding wire (not shown). Has been.

コレクタ電極は、IGBT25の下面の全面にAlを積層して形成され、第1半田層24aを介して、下部電極23へ電気的に接続されている。   The collector electrode is formed by laminating Al on the entire lower surface of the IGBT 25, and is electrically connected to the lower electrode 23 via the first solder layer 24a.

IGBT25は、ゲート電極の電圧を制御することで、コレクタ電極からエミッタ電極へ流れる電流のオン、オフを制御することができる。   The IGBT 25 can control ON / OFF of the current flowing from the collector electrode to the emitter electrode by controlling the voltage of the gate electrode.

第2半導体素子26は、例えば、逆起電力による第1半導体素子(IGBT)25の損傷を防止する還流ダイオード素子である。第2半導体素子26の上面は、第2半田層24b、上部電極27、第2半田層24bを介して、第1半導体素子25のエミッタ電極へ電気的に接続されている。他方、第2半導体素子26の下面は、第1半田層24a、下部電極23、第1半田層24aを介して、第1半導体素子25のコレクタ電極へ電気的に接続されている。   The second semiconductor element 26 is, for example, a free-wheeling diode element that prevents damage to the first semiconductor element (IGBT) 25 due to back electromotive force. The upper surface of the second semiconductor element 26 is electrically connected to the emitter electrode of the first semiconductor element 25 via the second solder layer 24b, the upper electrode 27, and the second solder layer 24b. On the other hand, the lower surface of the second semiconductor element 26 is electrically connected to the collector electrode of the first semiconductor element 25 via the first solder layer 24a, the lower electrode 23, and the first solder layer 24a.

上部電極27、下部電極23は、導電性、放熱性に優れたAl又はCuで形成されている。   The upper electrode 27 and the lower electrode 23 are made of Al or Cu excellent in conductivity and heat dissipation.

この半導体装置は、上述した基本構成を6組備え、後述の電気回路を形成している。   This semiconductor device has six sets of the basic configuration described above and forms an electric circuit described later.

図2は、半導体装置の電気回路の一例を示した図である。この半導体装置は、6組のIGBT25、還流ダイオード26を3相ブリッジ結線して、直流電流を3相交流電流に変換する3相交流インバータ回路30を構成している。この3相交流インバータ回路30の出力部は、3相モータ31に結線されている。このため、IGBT25のオン、オフのスイッチング周波数を変更することで、3相モータ31の回転速度、出力トルクを容易に変更することができる。   FIG. 2 is a diagram illustrating an example of an electric circuit of the semiconductor device. This semiconductor device constitutes a three-phase AC inverter circuit 30 that converts a DC current into a three-phase AC current by connecting six sets of IGBTs 25 and a reflux diode 26 in a three-phase bridge connection. The output part of the three-phase AC inverter circuit 30 is connected to a three-phase motor 31. For this reason, the rotational speed and output torque of the three-phase motor 31 can be easily changed by changing the on / off switching frequency of the IGBT 25.

3相モータ31を駆動すべく、3相交流インバータ回路30に電流が流れると、半導体素子25、26で熱が発生する。半導体素子25、26は、過熱すると正常に作動しなくなるので、放熱板21が設置されている。   When a current flows through the three-phase AC inverter circuit 30 to drive the three-phase motor 31, heat is generated in the semiconductor elements 25 and 26. Since the semiconductor elements 25 and 26 do not operate normally when overheated, the heat sink 21 is installed.

放熱板21は、高熱伝導のAl又はCuで形成される。半導体素子25、26で発生した熱は、後述の絶縁シート22を経由して、放熱板21で放熱される。これにより、半導体素子25、26の過熱を防止し、半導体素子25、26の熱破壊を防止している。   The heat sink 21 is made of Al or Cu having high thermal conductivity. The heat generated in the semiconductor elements 25 and 26 is radiated by the heat radiating plate 21 via an insulating sheet 22 described later. This prevents overheating of the semiconductor elements 25 and 26 and prevents thermal destruction of the semiconductor elements 25 and 26.

絶縁シート22は、例えば、柔軟性、絶縁性に優れたエポキシ樹脂で形成される。この絶縁シート22の表面には、放熱板21との密着性を高め、放熱性を高めるべく、シリコングリスが塗布されてよい。シリコングリスは、下部電極23および放熱板21の微小な凹凸の隙間を充填し、下部電極23からの熱を素早く放熱板21に伝導する。   The insulating sheet 22 is formed of, for example, an epoxy resin that is excellent in flexibility and insulation. Silicon grease may be applied to the surface of the insulating sheet 22 in order to improve adhesion to the heat radiating plate 21 and enhance heat dissipation. The silicon grease fills the gaps between the concave and convex portions of the lower electrode 23 and the heat radiating plate 21, and quickly conducts heat from the lower electrode 23 to the heat radiating plate 21.

エポキシ樹脂は、放熱板21に比べて放熱性が低く、厚くなりすぎると、半導体素子25、26の熱が放熱板21に伝導し難くなるので、下部電極23と放熱板21との絶縁性を確保できる限り、薄くされる。   Epoxy resin has low heat dissipation compared to the heat sink 21, and if it is too thick, the heat of the semiconductor elements 25 and 26 is difficult to conduct to the heat sink 21, so that the insulation between the lower electrode 23 and the heat sink 21 is improved. As thin as possible.

このように絶縁シート22を下部電極23と放熱板21との間に挿入することにより、1つの下部電極23と、他の5つの下部電極23との絶縁性を確保している。下部電極23と放熱板21との圧着方法の詳細については後述する。   As described above, the insulating sheet 22 is inserted between the lower electrode 23 and the heat radiating plate 21 to ensure insulation between one lower electrode 23 and the other five lower electrodes 23. Details of the pressure bonding method between the lower electrode 23 and the heat sink 21 will be described later.

図3、図4は、本発明の圧着方法の一実施例を示した図であり、(a)は概略斜視図で、(b)は(a)のA−Aに沿った断面図である。本実施例の圧着方法は、下部電極23、半導体素子25、26、上部電極27を半田付けして積層する1工程(図3参照)と、絶縁シート22を介して、下部電極23と放熱板21とを圧着する第2工程(図4参照)とからなる。   3 and 4 are views showing an embodiment of the pressure-bonding method of the present invention, where (a) is a schematic perspective view, and (b) is a cross-sectional view taken along line AA of (a). . The crimping method of the present embodiment is such that the lower electrode 23, the semiconductor elements 25 and 26, and the upper electrode 27 are soldered and laminated, and the lower electrode 23 and the heat sink are interposed via the insulating sheet 22. 21 and the second step (see FIG. 4).

第1工程では、まず、図3(a)に示すように、下部電極23上に、柱状の補助位置決め治具41を設置する。   In the first step, first, a columnar auxiliary positioning jig 41 is installed on the lower electrode 23 as shown in FIG.

続いて、図3(b)に示すように、補助位置決め治具41を挟むように、下部電極23上に2枚の第1半田箔24aを配置し、それぞれの第1半田箔24a上に第1半導体素子25および第2半導体素子26のいずれか一方を載せる。つまり、柱状の補助位置決め治具41を挟むように、下部電極23上に矩形状の第1半導体素子25および第2半導体素子26が配置されている。   Subsequently, as shown in FIG. 3B, two first solder foils 24a are arranged on the lower electrode 23 so as to sandwich the auxiliary positioning jig 41, and the first solder foils 24a are arranged on the first solder foils 24a. One of the first semiconductor element 25 and the second semiconductor element 26 is mounted. That is, the rectangular first semiconductor element 25 and the second semiconductor element 26 are disposed on the lower electrode 23 so as to sandwich the columnar auxiliary positioning jig 41.

続いて、半導体素子25、26上に、第2半田箔24bを介して、上部電極27を設置する。   Subsequently, the upper electrode 27 is installed on the semiconductor elements 25 and 26 via the second solder foil 24b.

尚、補助位置決め治具41の高さ方向寸法は、第1半田箔24a、半導体素子25、26、第2半田箔24bの総高さ方向寸法より小さく、下部電極23と上部電極27との間隙より小さくなっている。   The height-direction dimension of the auxiliary positioning jig 41 is smaller than the total height-direction dimension of the first solder foil 24a, the semiconductor elements 25, 26, and the second solder foil 24b, and the gap between the lower electrode 23 and the upper electrode 27. It is getting smaller.

続いて、枠形状の位置決め治具42を装着する。位置決め治具42の開口部43は、平面視四角形の形状であって、高さ方向に沿って下から上に行くほど面積が3段階で小さくなる構造を有する。各段階の開口部43a、43b、43cは、それぞれ、下部電極23、半導体素子25、26、上部電極27の外周面が略反転された形状の中空を形成している。   Subsequently, a frame-shaped positioning jig 42 is attached. The opening 43 of the positioning jig 42 has a quadrangular shape in plan view, and has a structure in which the area decreases in three steps from the bottom to the top along the height direction. The openings 43a, 43b, 43c at the respective stages form cavities in which the outer peripheral surfaces of the lower electrode 23, the semiconductor elements 25, 26, and the upper electrode 27 are substantially inverted.

この位置決め治具42を下側の開口部43aから装着させていくと、開口部43aは、上部電極27、半導体素子25、26、下部電極23を順次内側に収納していく。また、開口部43aに続く開口部43bは、上部電極27、半導体素子25、26を順次内側に収納していく。最終的に位置決め治具42の装着が完了すると、大きな開口部43aで下部電極23を、小さな開口部43bで半導体素子25、26を、さらに小さな開口部43cで上部電極27を所定の位置に位置決めすることができる。また、位置決めが完了した状態で、補助位置決め治具41は、位置決め治具42の左右一対の側面に形成された溝部44a、44bに係合され、第1半導体素子25と第2半導体素子26とを所定間隔で保持している。このようにして、下部電極23、半導体素子25、26、上部電極27は、位置決めされる。   When the positioning jig 42 is mounted from the lower opening 43a, the opening 43a sequentially stores the upper electrode 27, the semiconductor elements 25 and 26, and the lower electrode 23 inside. The opening 43b following the opening 43a sequentially houses the upper electrode 27 and the semiconductor elements 25 and 26 inside. When the mounting of the positioning jig 42 is finally completed, the lower electrode 23 is positioned in the large opening 43a, the semiconductor elements 25 and 26 are positioned in the small opening 43b, and the upper electrode 27 is positioned in the predetermined position in the smaller opening 43c. can do. Further, in the state where the positioning is completed, the auxiliary positioning jig 41 is engaged with the groove portions 44 a and 44 b formed on the pair of left and right side surfaces of the positioning jig 42, and the first semiconductor element 25, the second semiconductor element 26, Are held at predetermined intervals. In this way, the lower electrode 23, the semiconductor elements 25 and 26, and the upper electrode 27 are positioned.

最後に、補助位置決め治具41、位置決め治具42を装着したまま雰囲気炉で加熱処理し、第1半田箔24a、第2半田箔24bを溶融して、下部電極23、半導体素子25、26、上部電極27を半田付けする。半田付けは、半導体素子25、26が熱破壊されない比較的低温で行われ、例えば、180℃〜300℃で行われる。   Finally, heat treatment is performed in an atmospheric furnace with the auxiliary positioning jig 41 and the positioning jig 42 attached, and the first solder foil 24a and the second solder foil 24b are melted to form the lower electrode 23, the semiconductor elements 25, 26, The upper electrode 27 is soldered. Soldering is performed at a relatively low temperature at which the semiconductor elements 25 and 26 are not thermally destroyed, for example, at 180 ° C. to 300 ° C.

半田箔24a、24aには、例えば、Sn−Pb合金、Sn−Ag−Cu合金、Sn−Zn−Bi合金、Sn−Zn−Al合金を用いることができる。   For the solder foils 24a and 24a, for example, a Sn—Pb alloy, a Sn—Ag—Cu alloy, a Sn—Zn—Bi alloy, or a Sn—Zn—Al alloy can be used.

半田付けして金属接合することにより、第1半田層24a、上部電極27、第1半田層24aを介して、第1半導体素子(IGBT)25のエミッタ電極と、第2半導体素子(還流ダイオード)26のアノード側とが導通される。また、第2半田層24b、下部電極23、第2半田層24bを介して、第1半導体素子(IGBT)25のコレクタ電極と、第2半導体素子(還流ダイオード)26のカソード側とが導通される。   By soldering and metal bonding, the emitter electrode of the first semiconductor element (IGBT) 25 and the second semiconductor element (freewheeling diode) via the first solder layer 24a, the upper electrode 27, and the first solder layer 24a. 26 is electrically connected to the anode side. In addition, the collector electrode of the first semiconductor element (IGBT) 25 and the cathode side of the second semiconductor element (reflux diode) 26 are conducted through the second solder layer 24b, the lower electrode 23, and the second solder layer 24b. The

第1の工程で用いられる、補助位置決め治具41、位置決め治具42は、溶融半田との濡れ性が悪く、耐熱性が高いセラミックスで形成される。これにより、補助位置決め治具41および位置決め治具42と溶融半田との融着を防止することができ、半田付け後であっても、補助位置決め治具41および位置決め治具42を取り外し、再利用することができる。尚、補助位置決め治具41、位置決め治具42は、金属で形成して、金属の表面にセラミックスの微粒子を塗布することにより、離型性を確保しても良い。   The auxiliary positioning jig 41 and the positioning jig 42 used in the first step are formed of ceramics having poor wettability with molten solder and high heat resistance. Thereby, it is possible to prevent the auxiliary positioning jig 41 and the positioning jig 42 from being fused to the molten solder, and the auxiliary positioning jig 41 and the positioning jig 42 are removed and reused even after soldering. can do. The auxiliary positioning jig 41 and the positioning jig 42 may be made of metal, and the mold releasability may be ensured by applying ceramic fine particles to the surface of the metal.

また、補助位置決め治具41、位置決め治具42を形成するセラミックスには、安価なAlを用いても良いが、Alより熱伝導率の高いAlN、Si、SiCを用いてもよい。補助位置決め治具41、位置決め治具42の熱伝導率を高くすることで、半田付けのための熱処理をする際、昇温時間の短縮化および均熱化を図ることができ、熱処理時間を短縮化することができると共に、良好な半田付けを行うことができる。 In addition, although inexpensive Al 2 O 3 may be used for the ceramic forming the auxiliary positioning jig 41 and the positioning jig 42, AlN, Si 3 N 4 , SiC having higher thermal conductivity than Al 2 O 3. May be used. By increasing the thermal conductivity of the auxiliary positioning jig 41 and the positioning jig 42, when performing heat treatment for soldering, the temperature raising time can be shortened and the temperature can be equalized, and the heat treatment time can be shortened. And good soldering can be performed.

また、補助位置決め治具41、位置決め治具42は、熱膨張係数の比較的小さなセラミックスで形成されるため、熱膨張係数の比較的大きなAl又はCuで形成される上部電極27、下部電極23との熱膨張差が大きい。したがって、半田付けの際、補助位置決め治具41、位置決め治具42が上部電極27、半導体素子25、26、下部電極23の熱膨張を抑圧して損傷させないように、十分なクリアランスが設定されている。   Further, since the auxiliary positioning jig 41 and the positioning jig 42 are formed of ceramics having a relatively small thermal expansion coefficient, the upper electrode 27 and the lower electrode 23 formed of Al or Cu having a relatively large thermal expansion coefficient The difference in thermal expansion is large. Therefore, when soldering, a sufficient clearance is set so that the auxiliary positioning jig 41 and the positioning jig 42 do not damage the upper electrode 27, the semiconductor elements 25, 26, and the lower electrode 23 by suppressing thermal expansion. Yes.

第2工程では、第1工程で半田付けされた下部電極23、半導体素子25、26、上部電極27を、絶縁シート22を介して、放熱板21に圧着する。   In the second step, the lower electrode 23, the semiconductor elements 25 and 26, and the upper electrode 27 soldered in the first step are pressure-bonded to the heat sink 21 via the insulating sheet 22.

第2工程では、まず、図4(a)に示すように、第1工程で半田付けされた下部電極23、半導体素子25、26、上部電極27の下部電極23側に、絶縁シート22を介して放熱板21を配置する。   In the second step, first, as shown in FIG. 4A, an insulating sheet 22 is interposed on the lower electrode 23 side, the semiconductor elements 25 and 26, and the upper electrode 27 soldered in the first step. The heat sink 21 is arranged.

続いて、図4(b)に示すように、下部電極23、半導体素子25、26、および上部電極27で囲まれた断面四角形状の中空部に断面四角形の柱状の補助圧着治具51を挿入する。補助圧着治具51は、補助位置決め治具41と兼用して良い。補助位置決め治具41と兼用する場合、第1工程後に補助位置決め治具41を取り外すことなく、そのまま第2工程に着手でき、作業を簡略化できるだけでなく、補助圧着治具51の挿入による半導体素子25、26、半田層24a、24bの損傷を防止できる。   Subsequently, as shown in FIG. 4B, a columnar auxiliary crimping jig 51 having a quadrangular cross section is inserted into a hollow section having a quadrangular cross section surrounded by the lower electrode 23, the semiconductor elements 25 and 26, and the upper electrode 27. To do. The auxiliary crimping jig 51 may also be used as the auxiliary positioning jig 41. When the auxiliary positioning jig 41 is also used, the second positioning process can be started without removing the auxiliary positioning jig 41 after the first process, and the work can be simplified. 25, 26 and the solder layers 24a and 24b can be prevented from being damaged.

この補助圧着治具51は、セラミックスで形成しても、金属で形成しても良いが、破壊靱性の高い金属が好ましく、例えば、鋳鉄、ステンレス鋼で形成される。   The auxiliary crimping jig 51 may be formed of ceramics or metal, but is preferably a metal having high fracture toughness, for example, cast iron or stainless steel.

また、補助圧着治具51は、下面に突起(図示せず)を備えてよい。後述の圧着治具52が押圧されると、下面の突起で下部電極23を放熱板21へ圧着できる。   Further, the auxiliary crimping jig 51 may be provided with a protrusion (not shown) on the lower surface. When a later-described crimping jig 52 is pressed, the lower electrode 23 can be crimped to the heat radiating plate 21 by the protrusion on the lower surface.

続いて、枠形状の圧着治具52を装着する。圧着治具52は、位置決め治具42と兼用して良い。位置決め治具42と兼用する場合、第1工程後に位置決め治具42を取り外すことなく、第2工程に着手でき、作業を簡略化できる。   Subsequently, a frame-shaped crimping jig 52 is mounted. The crimping jig 52 may also be used as the positioning jig 42. When the positioning jig 42 is also used, the second process can be started without removing the positioning jig 42 after the first process, and the work can be simplified.

この圧着治具52は、セラミックスで形成しても、金属で形成しても良いが、破壊靱性の高い金属が好ましく、例えば、鋳鉄、ステンレス鋼で形成される。   The crimping jig 52 may be formed of ceramics or metal, but is preferably a metal having high fracture toughness, for example, cast iron or stainless steel.

これらの補助圧着治具51、圧着治具52は、圧着時の弾性変形により、上部電極27、半導体素子25、26、下部電極23を圧迫して損傷しないように、十分なクリアランスが設定されている。   The auxiliary crimping jig 51 and the crimping jig 52 have a sufficient clearance so that the upper electrode 27, the semiconductor elements 25 and 26, and the lower electrode 23 are not pressed and damaged by elastic deformation during crimping. Yes.

この圧着治具52を下側の開口部53aから装着させていくと、位置決め治具42と同様に、開口部53aは、上部電極27、半導体素子25、26、下部電極23を順次内側に収納していく。また、開口部53aに続く開口部53bは、上部電極27、半導体素子25、26を順次内側に収納していく。圧着治具52の装着が完了すると、大きな開口部53aで下部電極23を、小さな開口部53bで半導体素子25、26を、さらに小さな開口部53cで上部電極27を収納する。   When the crimping jig 52 is mounted from the lower opening 53a, the opening 53a stores the upper electrode 27, the semiconductor elements 25 and 26, and the lower electrode 23 sequentially inward as in the positioning jig 42. I will do it. The opening 53b following the opening 53a sequentially stores the upper electrode 27 and the semiconductor elements 25 and 26 inside. When the mounting of the crimping jig 52 is completed, the lower electrode 23 is stored in the large opening 53a, the semiconductor elements 25 and 26 are stored in the small opening 53b, and the upper electrode 27 is stored in the smaller opening 53c.

圧着治具52の装着完了の状態で、圧着治具52は、大きな開口部53aと小さな開口部53bとの段差部55で、下部電極23の上面の周縁と当接すると共に、半導体素子25、26、上部電極27と間隙を形成しつつ、囲繞している。   When the crimping jig 52 is completely mounted, the crimping jig 52 is in contact with the peripheral edge of the upper surface of the lower electrode 23 at the stepped portion 55 between the large opening 53a and the small opening 53b, and the semiconductor elements 25, 26. The upper electrode 27 is surrounded while forming a gap.

また、この状態で、補助圧着治具51は、圧着治具52の側面に形成された左右一対の溝部54a、54bの上端部と下部電極23とで挟持されている。つまり、補助圧着治具51は、その上面が圧着治具52の溝部54a、54bの上端部に当接すると共に、その下面が下部電極23に当接している。   Further, in this state, the auxiliary crimping jig 51 is sandwiched between the upper ends of the pair of left and right grooves 54 a and 54 b formed on the side surface of the crimping jig 52 and the lower electrode 23. That is, the auxiliary crimping jig 51 has an upper surface in contact with the upper ends of the grooves 54 a and 54 b of the crimping jig 52 and a lower surface in contact with the lower electrode 23.

続いて、圧着治具52を押圧すると、圧着治具52の段差部55で下部電極23の周縁を押圧することができると共に、半導体素子25、26間に配置された補助圧着治具51で下部電極23の中央付近を押圧することができる。これにより、下部電極23の周縁と中央付近を押圧することができ、下部電極23と放熱板21とを均一に圧着することができる。   Subsequently, when the crimping jig 52 is pressed, the peripheral edge of the lower electrode 23 can be pressed by the stepped portion 55 of the crimping jig 52, and the lower part is pressed by the auxiliary crimping jig 51 disposed between the semiconductor elements 25 and 26. The vicinity of the center of the electrode 23 can be pressed. Thereby, the periphery and the center vicinity of the lower electrode 23 can be pressed, and the lower electrode 23 and the heat sink 21 can be crimped | compressed uniformly.

ここで、圧着治具52は、半導体素子25、26と間隙を形成しているため、押圧されても、半導体素子25、26を直接圧迫しない。また、圧着治具52は、上部電極27とも間隙を形成しているため、押圧されても、上部電極27を介して半導体素子25、26を圧迫しない。したがって、半導体素子25、26の損傷を防止することができる。   Here, since the crimping jig 52 forms a gap with the semiconductor elements 25 and 26, even if pressed, the crimping jig 52 does not directly press the semiconductor elements 25 and 26. In addition, since the crimping jig 52 forms a gap with the upper electrode 27, it does not press the semiconductor elements 25 and 26 via the upper electrode 27 even when pressed. Therefore, damage to the semiconductor elements 25 and 26 can be prevented.

続いて、下部電極23、絶縁シート22、放熱板21を圧着した状態で、下部電極23と放熱板21とをネジ締結することにより、下部電極23、絶縁シート22、放熱板21の圧着状態を維持することができる。ネジ締結後、補助圧着治具51、圧着治具52は、取り外され、再利用される。   Subsequently, the lower electrode 23, the insulating sheet 22, and the heat radiating plate 21 are crimped, and the lower electrode 23 and the heat radiating plate 21 are screwed to each other, so that the lower electrode 23, the insulating sheet 22, and the heat radiating plate 21 are pressed. Can be maintained. After the screw fastening, the auxiliary crimping jig 51 and the crimping jig 52 are removed and reused.

このように形成された半導体装置の基本構成6組を絶縁性のゲルと共に1つの樹脂パッケージ(図示せず)の内部に封止することにより、図2の電気回路を有する半導体装置が製造される。この樹脂パッケージは、周囲が放熱板21と接着されており、外部に入出力端子を備える。   A semiconductor device having the electric circuit of FIG. 2 is manufactured by sealing six basic configurations of the semiconductor device thus formed together with an insulating gel in one resin package (not shown). . The periphery of the resin package is bonded to the heat sink 21 and includes input / output terminals outside.

このように、本実施例の圧着方法によれば、圧着治具52を押圧して、圧着治具52の段差部55で下部電極23の周縁を押圧することができると共に、半導体素子25、26間に挿入された補助圧着治具51で下部電極23の中央付近を押圧することができ、下部電極23と放熱板21とを均一に圧着することができる。また、圧着治具52を押圧しても、半導体素子25、26および上部電極27を押圧することがなく、上部電極27と下部電極23とで挟持された半導体素子25、26の損傷を防ぐことができる。また、再使用可能な補助圧着治具51および圧着治具52を用いて、上部電極27および下部電極23に穴加工することなく、下部電極23を放熱板21に圧着することができる。   As described above, according to the crimping method of this embodiment, the crimping jig 52 can be pressed to press the peripheral edge of the lower electrode 23 with the stepped portion 55 of the crimping jig 52, and the semiconductor elements 25, 26. The vicinity of the center of the lower electrode 23 can be pressed by the auxiliary crimping jig 51 inserted therebetween, and the lower electrode 23 and the heat sink 21 can be uniformly crimped. Further, even if the crimping jig 52 is pressed, the semiconductor elements 25 and 26 and the upper electrode 27 are not pressed, and the semiconductor elements 25 and 26 sandwiched between the upper electrode 27 and the lower electrode 23 are prevented from being damaged. Can do. Further, the reusable auxiliary crimping jig 51 and the crimping jig 52 can be used to crimp the lower electrode 23 to the heat radiating plate 21 without drilling holes in the upper electrode 27 and the lower electrode 23.

尚、仮に、本実施例の第2工程後に、本実施例の第1工程を行うとすると、下部電極23の全面を押圧することができ、下部電極23と放熱板21とを均一に圧着できる。しかしながら、第2工程で下部電極23と放熱板21との間に配置された樹脂製の絶縁シート22が、第1工程の熱処理によって損傷されることになり、絶縁性を確保できなくなる。したがって、本実施例の第2工程後に、本実施例の第1工程を行うことはできない。   If the first step of the present embodiment is performed after the second step of the present embodiment, the entire surface of the lower electrode 23 can be pressed, and the lower electrode 23 and the radiator plate 21 can be uniformly bonded. . However, the resin insulating sheet 22 disposed between the lower electrode 23 and the heat sink 21 in the second step is damaged by the heat treatment in the first step, and insulation cannot be ensured. Therefore, the first step of this embodiment cannot be performed after the second step of this embodiment.

以上、本発明の好ましい実施例について詳説したが、本発明は、上述した実施例に制限されることはなく、本発明の範囲を逸脱することなく、上述した実施例に種々の変形及び置換を加えることができる。   The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

例えば、本実施例の半導体素子25、26は、第1半導体素子25と第2半導体素子26とからなるとしたが、複数の半導体素子間に補助圧着治具51を挿入して下部電極23を押圧できる限り、下部電極23と上部電極27との間に配置される半導体素子の数に制限はない。   For example, although the semiconductor elements 25 and 26 of the present embodiment are composed of the first semiconductor element 25 and the second semiconductor element 26, the auxiliary crimping jig 51 is inserted between the plurality of semiconductor elements to press the lower electrode 23. As many as possible, there is no limit to the number of semiconductor elements disposed between the lower electrode 23 and the upper electrode 27.

また、本実施例では、半導体素子25、26の下部電極23と放熱板21とを圧着するとしたが、放熱板21が上部電極27側に配置される場合には、半導体素子25、26の上部電極27と放熱板21とを圧着しても良い。半導体素子25、26の上部電極27であっても、下部電極23の場合と同様に放熱板21と圧着することができる。   In the present embodiment, the lower electrode 23 and the heat sink 21 of the semiconductor elements 25 and 26 are crimped. However, when the heat sink 21 is disposed on the upper electrode 27 side, the upper portions of the semiconductor elements 25 and 26 are disposed. The electrode 27 and the heat sink 21 may be pressure-bonded. Even the upper electrode 27 of the semiconductor elements 25 and 26 can be pressure-bonded to the heat radiating plate 21 as in the case of the lower electrode 23.

また、本実施例では、絶縁シート22を下部電極23と放熱板21との間に挿入することにより、1つの下部電極23と、他の5つの下部電極23との絶縁性を確保するとしたが、複数の下部電極23の電位を常に同一に制御する限り、複数の下部電極23を互いに連結して導通させても良い。例えば、図2の3相交流インバータ回路では、3つの下部電極23を互いに連結して導通させることができる。   Further, in this embodiment, the insulating sheet 22 is inserted between the lower electrode 23 and the heat radiating plate 21 to ensure insulation between one lower electrode 23 and the other five lower electrodes 23. As long as the potentials of the plurality of lower electrodes 23 are always controlled to be the same, the plurality of lower electrodes 23 may be connected to each other to be conducted. For example, in the three-phase AC inverter circuit of FIG. 2, the three lower electrodes 23 can be connected to each other to be conducted.

また、本実施例では、下部電極23と放熱板21とを絶縁シート22を介してネジ締結したが、粘着性の絶縁シート22を用いて、下部電極23と放熱板21とを粘着固定しても良い。いずれの場合であっても、補助圧着治具51、圧着治具52を用いて、半導体素子25、26を損傷することなく、均一に下部電極23と放熱板21とを圧着できる。粘着性の絶縁シート22は、例えば、感圧接着剤又はホットメルト形接着剤を含有する樹脂で形成される。   Further, in this embodiment, the lower electrode 23 and the heat radiating plate 21 are screwed together via the insulating sheet 22, but the lower electrode 23 and the heat radiating plate 21 are adhesively fixed using the adhesive insulating sheet 22. Also good. In any case, the lower electrode 23 and the radiator plate 21 can be uniformly crimped using the auxiliary crimping jig 51 and the crimping jig 52 without damaging the semiconductor elements 25 and 26. The adhesive insulating sheet 22 is formed of, for example, a resin containing a pressure sensitive adhesive or a hot melt adhesive.

半導体装置の基本構成の一例を示した断面図である。It is sectional drawing which showed an example of the basic composition of a semiconductor device. 半導体装置の電気回路の一例を示した図である。It is a figure showing an example of an electric circuit of a semiconductor device. 本発明の圧着方法の一実施例を示した図である。It is the figure which showed one Example of the crimping | compression-bonding method of this invention. 本発明の圧着方法の一実施例を示した図である。It is the figure which showed one Example of the crimping | compression-bonding method of this invention. 従来の半導体装置の構成の一例を示した断面図である。It is sectional drawing which showed an example of the structure of the conventional semiconductor device.

符号の説明Explanation of symbols

21 放熱板
22 絶縁シート
23 下部電極
25 第1半導体素子
26 第2半導体素子
27 上部電極
41 補助位置決め治具
42 位置決め治具
51 補助圧着治具
52 圧着治具
21 Heat Dissipation Plate 22 Insulating Sheet 23 Lower Electrode 25 First Semiconductor Element 26 Second Semiconductor Element 27 Upper Electrode 41 Auxiliary Positioning Jig 42 Positioning Jig 51 Auxiliary Crimping Jig 52 Crimping Jig

Claims (1)

複数の半導体素子を上部電極と下部電極とにより挟持し、前記上部電極および前記下部電極のうち何れか一方の電極を放熱板へ圧着する半導体素子の電極と放熱板との圧着方法において、
前記複数の半導体素子間に補助圧着治具を挿入し、前記複数の半導体素子および他方の電極と間隙を形成しつつ囲繞すると共に前記一方の電極の周縁および前記補助圧着治具に係合する圧着治具を装着し、前記圧着治具を押圧して前記一方の電極を前記放熱板へ圧着する半導体素子の電極と放熱板との圧着方法。
In a method of crimping a semiconductor element electrode and a heat sink plate, sandwiching a plurality of semiconductor elements between an upper electrode and a lower electrode, and crimping one of the upper electrode and the lower electrode to a heat sink plate,
A pressure bonding jig is inserted between the plurality of semiconductor elements, and is surrounded by forming a gap with the plurality of semiconductor elements and the other electrode, and is bonded to the peripheral edge of the one electrode and the auxiliary pressure bonding jig. A method of crimping a semiconductor element electrode and a radiator plate, wherein a jig is attached and the crimping jig is pressed to crimp the one electrode to the radiator plate.
JP2007242718A 2007-09-19 2007-09-19 Method of crimping electrode of semiconductor device and heat slinger Pending JP2009076592A (en)

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Cited By (7)

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Publication number Priority date Publication date Assignee Title
JP2013021145A (en) * 2011-07-12 2013-01-31 Fuji Electric Co Ltd Semiconductor device assembly jig and method of manufacturing semiconductor device using the same
JP2013058645A (en) * 2011-09-08 2013-03-28 Fuji Electric Co Ltd Semiconductor device and semiconductor device manufacturing method
JP2020188203A (en) * 2019-05-16 2020-11-19 三菱電機株式会社 Positioning jig for soldering
CN112701103A (en) * 2020-12-07 2021-04-23 杰群电子科技(东莞)有限公司 Combined packaging structure and combined packaging process
CN113053831A (en) * 2019-12-27 2021-06-29 株洲中车时代半导体有限公司 Crimping type IGBT module and power semiconductor device
US11063495B2 (en) 2019-07-01 2021-07-13 Nidec Motor Corporation Heatsink clamp for multiple electronic components
US11133644B2 (en) 2017-07-07 2021-09-28 Panasonic Intellectual Property Management Co., Ltd. Semiconductor laser device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013021145A (en) * 2011-07-12 2013-01-31 Fuji Electric Co Ltd Semiconductor device assembly jig and method of manufacturing semiconductor device using the same
JP2013058645A (en) * 2011-09-08 2013-03-28 Fuji Electric Co Ltd Semiconductor device and semiconductor device manufacturing method
US11133644B2 (en) 2017-07-07 2021-09-28 Panasonic Intellectual Property Management Co., Ltd. Semiconductor laser device
JP2020188203A (en) * 2019-05-16 2020-11-19 三菱電機株式会社 Positioning jig for soldering
US11063495B2 (en) 2019-07-01 2021-07-13 Nidec Motor Corporation Heatsink clamp for multiple electronic components
CN113053831A (en) * 2019-12-27 2021-06-29 株洲中车时代半导体有限公司 Crimping type IGBT module and power semiconductor device
CN113053831B (en) * 2019-12-27 2023-09-05 株洲中车时代半导体有限公司 Crimping IGBT module and power semiconductor device
CN112701103A (en) * 2020-12-07 2021-04-23 杰群电子科技(东莞)有限公司 Combined packaging structure and combined packaging process
CN112701103B (en) * 2020-12-07 2023-02-10 杰群电子科技(东莞)有限公司 Combined packaging structure and combined packaging process

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