JP2013058645A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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JP2013058645A
JP2013058645A JP2011196593A JP2011196593A JP2013058645A JP 2013058645 A JP2013058645 A JP 2013058645A JP 2011196593 A JP2011196593 A JP 2011196593A JP 2011196593 A JP2011196593 A JP 2011196593A JP 2013058645 A JP2013058645 A JP 2013058645A
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conductive plate
semiconductor device
insulating substrate
semiconductor chip
wiring pattern
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JP5919692B2 (en
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Yuji Iizuka
祐二 飯塚
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor device manufacturing method, which achieve downsizing and high reliability.SOLUTION: A semiconductor device comprises: a first conductive plate 2-1 with one surface being bonded with a rear face of a semiconductor chip 1 and another surface being bonded with a circuit pattern 3a of a first wiring board 3; protrusions 11 provided on the other surface of the first conductive plate 2-1; recesses 3a-1 provided on the circuit pattern 3a of the first wiring board 3 at locations corresponding to the protrusions 11 of the first conductive plate 2-1; a second conductive plate 2-2 with one surface being bonded with a surface of the semiconductor chip 1 and another surface being bonded with a circuit pattern 4a of a second wiring board 4; protrusions 12 provided on the other surface of the second conductive plate 2-2; and recesses 4a-4 provided on the circuit pattern 4a of the second wiring board 4 at locations corresponding to the protrusions 12 of the second conductive plate 2-2.

Description

この発明は、半導体装置および半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

従来、パワーデバイスは、電力変換用途のスイッチングデバイスとして用いられる。図６は、従来の半導体装置の構造について示す断面図である。図６に示すように、半導体装置１００は、半導体チップ１０１と、配線基板１０２と、アルミワイヤ１０３と、ヒートシンク１０４と、ケース１０５と、を備えている。   Conventionally, power devices are used as switching devices for power conversion applications. FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device. As shown in FIG. 6, the semiconductor device 100 includes a semiconductor chip 101, a wiring board 102, an aluminum wire 103, a heat sink 104, and a case 105.

配線基板１０２は、絶縁基板のおもて面に回路パターン１０２ａ，１０２ｂを形成した基板である。半導体チップ１０１の裏面は、図示省略した接合材を介して配線基板１０２の回路パターン１０２ａと接合している。半導体チップ１０１のおもて面に設けられた図示省略した電極（以下、おもて面電極とする）と回路パターン１０２ｂとはアルミワイヤ１０３によって電気的に接続されている。配線基板１０２の裏面には金属接合層１０２ｃが設けられており、この金属接合層１０２ｃが図示を省略した接合材を介してヒートシンク１０４と接合している。   The wiring substrate 102 is a substrate in which circuit patterns 102a and 102b are formed on the front surface of an insulating substrate. The back surface of the semiconductor chip 101 is bonded to the circuit pattern 102a of the wiring board 102 via a bonding material (not shown). An electrode (not shown) provided on the front surface of the semiconductor chip 101 (hereinafter referred to as a front surface electrode) and the circuit pattern 102 b are electrically connected by an aluminum wire 103. A metal bonding layer 102c is provided on the back surface of the wiring substrate 102, and the metal bonding layer 102c is bonded to the heat sink 104 via a bonding material (not shown).

ヒートシンク１０４は、良熱伝導体で作られており、ベース部１０４ａおよび放熱フィン部１０４ｂを有する。ベース部１０４ａは、半導体チップ１０１で発生し、配線基板１０２を介して伝わる熱を放熱フィン部１０４ｂへ伝導する。放熱フィン部１０４ｂは、複数の放熱フィンを有し、ベース部１０４ａから伝導された熱を放散する。ヒートシンク１０４の周縁にはケース１０５が接着されている。このように各部材を配置して接合することで、図６に示す半導体装置１００のような単体のモジュールが形成される。   The heat sink 104 is made of a good heat conductor and includes a base portion 104a and a heat radiating fin portion 104b. The base portion 104a conducts heat generated in the semiconductor chip 101 and transmitted through the wiring substrate 102 to the heat radiating fin portion 104b. The radiating fin portion 104b has a plurality of radiating fins and radiates heat conducted from the base portion 104a. A case 105 is bonded to the periphery of the heat sink 104. By arranging and joining the members in this way, a single module such as the semiconductor device 100 shown in FIG. 6 is formed.

このような単体のモジュールとして、半導体素子が面接合により実装された第１バスバーと第２バスバーを樹脂枠により一体化し、半導体素子配設領域にゲル部材を充填して硬化させることにより半導体素子を封止した半導体モジュールと、半導体モジュールが放熱シートを挟んで固定される冷却器とを備える半導体装置において、半導体素子配設領域から半導体モジュールの放熱シートに対向する部分へと貫通する孔を、樹脂枠の連結部に形成した装置が提案されている（例えば、下記特許文献１参照。）。   As such a single module, the first bus bar and the second bus bar on which the semiconductor elements are mounted by surface bonding are integrated by a resin frame, and the semiconductor element placement region is filled with a gel member and cured to cure the semiconductor element. In a semiconductor device including a sealed semiconductor module and a cooler on which the semiconductor module is fixed with a heat dissipation sheet interposed therebetween, a hole penetrating from a semiconductor element disposition region to a portion facing the heat dissipation sheet of the semiconductor module is formed of resin. An apparatus formed at a connecting portion of a frame has been proposed (for example, see Patent Document 1 below).

特開２００３−７９２８号公報JP 2003-7928 A

しかしながら、太陽光発電や風力発電など、再生可能エネルギー源による省電力を志向した発電設備の普及にともない、電力変換装置の需要が増え、電力変換装置を構成するパワーモジュールの大容量化が特に課題となっている。上述した従来の半導体装置１００の大容量化を図る場合、半導体チップ１０１のおもて面電極と配線基板１０２とを電気的に接続するアルミワイヤ１０３の本数を定格電流に応じて増やして通電能力を確保する必要がある。   However, with the widespread use of power generation facilities that aim to save power from renewable energy sources such as solar power generation and wind power generation, the demand for power conversion devices has increased, and the increase in capacity of power modules that constitute power conversion devices is particularly problematic It has become. When increasing the capacity of the above-described conventional semiconductor device 100, the number of aluminum wires 103 that electrically connect the front electrode and the wiring board 102 of the semiconductor chip 101 is increased in accordance with the rated current to increase the current carrying capacity. It is necessary to ensure.

近年、デバイスの特性改善により個々の半導体チップ１０１の通電許容電流密度が増大しており、アルミワイヤ１０３の配線密度が高まる傾向にある。このため、配線基板１０２のアルミワイヤ１０３が接合される部分、すなわち回路パターン１０２ｂの表面積をアルミワイヤ１０３の本数に応じて一定の大きさで確保する必要がある。したがって、デバイスの特性改善により個々の半導体チップ１０１が縮小化されるのに対し、半導体チップ１０１の通電許容電流密度の増大により配線基板１０２の回路パターン１０２ｂの表面積は増大する。   In recent years, the allowable current density of each semiconductor chip 101 has increased due to the improvement of device characteristics, and the wiring density of the aluminum wires 103 tends to increase. For this reason, it is necessary to secure the surface area of the portion of the wiring substrate 102 to which the aluminum wire 103 is bonded, that is, the surface area of the circuit pattern 102b, according to the number of the aluminum wires 103. Therefore, while the individual semiconductor chip 101 is reduced by improving the device characteristics, the surface area of the circuit pattern 102b of the wiring board 102 is increased by increasing the allowable current density of the semiconductor chip 101.

特に、半導体チップ１０１が複数実装されるマルチチップパッケージ型半導体装置の場合、回路パターン１０２ｂは配線基板１０２上の複数個所に配置される。さらに、各半導体チップ１０１の通電能力をそれぞれ最大限に引き出して大容量化を行うため、配線基板１０２のおもて面の表面積に占める回路パターン１０２ｂの表面積の割合が大きくなり、半導体装置１００の小型化が困難であるという問題が生じる。   In particular, in the case of a multi-chip package type semiconductor device on which a plurality of semiconductor chips 101 are mounted, the circuit pattern 102 b is disposed at a plurality of locations on the wiring substrate 102. Furthermore, since the current carrying capacity of each semiconductor chip 101 is maximized to increase the capacity, the ratio of the surface area of the circuit pattern 102b to the surface area of the front surface of the wiring board 102 increases, and the semiconductor device 100 There arises a problem that miniaturization is difficult.

さらに、上述した従来の半導体装置１００は、ヒートサイクルによる負荷によって、使用開始後の早い時期に半導体チップ１０１と配線基板１０２との接合部分に破壊が生じる虞がある。このため、半導体装置１００の信頼性を確保することが困難であるという問題が生じる。   Furthermore, in the conventional semiconductor device 100 described above, there is a possibility that the bonded portion between the semiconductor chip 101 and the wiring substrate 102 may be broken early after the start of use due to a load caused by a heat cycle. For this reason, the problem that it is difficult to ensure the reliability of the semiconductor device 100 arises.

この発明は、上述した従来技術による問題点を解消するため、小型化を実現することができる半導体装置および半導体装置の製造方法を提供することを目的とする。また、この発明は、上述した従来技術による問題点を解消するため、信頼性の高い半導体装置および半導体装置の製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can be miniaturized in order to solve the above-described problems caused by the prior art. Another object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the semiconductor device in order to solve the above-described problems caused by the prior art.

上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置は、半導体チップの主面に設けられた電極と、絶縁基板の主面に設けられた配線パターンとを電気的に接続する導電板を備え、前記導電板の一方の面は、前記半導体チップの電極が設けられた主面に接合され、前記導電板の他方の面は、前記絶縁基板の配線パターンに接合されていることを特徴とする。   In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention electrically connects an electrode provided on a main surface of a semiconductor chip and a wiring pattern provided on a main surface of an insulating substrate. A conductive plate that is electrically connected, wherein one surface of the conductive plate is bonded to a main surface provided with the electrodes of the semiconductor chip, and the other surface of the conductive plate is bonded to a wiring pattern of the insulating substrate. It is characterized by being.

また、この発明にかかる半導体装置は、上述した発明において、前記導電板の他方の面には、前記絶縁基板の主面に水平な方向における前記絶縁基板との接合位置を固定する突起部が設けられ、前記絶縁基板の配線パターンには、前記導電板の前記突起部に対応する位置に前記突起部が挿入される凹部が設けられていることを特徴とする。   In the semiconductor device according to the present invention, in the above-described invention, the other surface of the conductive plate is provided with a protrusion that fixes a bonding position with the insulating substrate in a direction horizontal to the main surface of the insulating substrate. The wiring pattern of the insulating substrate is provided with a recess into which the protrusion is inserted at a position corresponding to the protrusion of the conductive plate.

また、この発明にかかる半導体装置は、上述した発明において、前記絶縁基板の主面に水平な方向における前記絶縁基板と前記導電板との接合位置を固定する導電体をさらに備え、前記導電板の他方の面には、前記導電体の一方の端部が挿入される凹部が設けられ、前記絶縁基板の配線パターンには、前記導電板の前記凹部に対応する位置に前記導電体の他方の端部が挿入される凹部が設けられている。   The semiconductor device according to the present invention further includes a conductor that fixes a bonding position between the insulating substrate and the conductive plate in a direction horizontal to a main surface of the insulating substrate in the above-described invention, The other surface is provided with a recess into which one end of the conductor is inserted, and the other end of the conductor is positioned in the wiring pattern of the insulating substrate at a position corresponding to the recess of the conductive plate. A recess into which the part is inserted is provided.

また、この発明にかかる半導体装置は、上述した発明において、前記半導体チップの線膨張係数α１、前記導電板の線膨張係数α２、および前記絶縁基板の配線パターンの線膨張係数α３は、α１＜α２＜α３を満たすことを特徴とする。   In the semiconductor device according to the present invention, the linear expansion coefficient α1 of the semiconductor chip, the linear expansion coefficient α2 of the conductive plate, and the linear expansion coefficient α3 of the wiring pattern of the insulating substrate are α1 <α2 in the above-described invention. <Α3 is satisfied.

また、この発明にかかる半導体装置は、上述した発明において、前記導電板は、モリブデン、タングステン、銅とモリブデンとからなる合金、鉄とニッケルとからなる合金、または、鉄とニッケルとコバルトとからなる合金、もしくはこれらの金属および合金を２種類以上組み合わせて形成される複合材料で構成されていることを特徴とする。   In the semiconductor device according to the present invention, in the above-described invention, the conductive plate is made of molybdenum, tungsten, an alloy made of copper and molybdenum, an alloy made of iron and nickel, or made of iron, nickel and cobalt. It is composed of an alloy or a composite material formed by combining two or more of these metals and alloys.

また、この発明にかかる半導体装置は、上述した発明において、前記絶縁基板の配線パターンは、銅、アルミニウム、銀またはニッケルで構成されていることを特徴とする。   In the semiconductor device according to the present invention as set forth in the invention described above, the wiring pattern of the insulating substrate is made of copper, aluminum, silver or nickel.

また、この発明にかかる半導体装置は、上述した発明において、前記絶縁基板の配線パターンには複数の前記導電板が接合され、複数の前記導電板にはそれぞれ前記半導体チップが接合され、複数の前記半導体チップの主面に設けられた電極どうしは電気的に接続されている。   In the semiconductor device according to the present invention, in the above-described invention, a plurality of the conductive plates are bonded to the wiring pattern of the insulating substrate, and the semiconductor chips are bonded to the plurality of conductive plates, respectively. The electrodes provided on the main surface of the semiconductor chip are electrically connected.

また、この発明にかかる半導体装置は、上述した発明において、前記導電板は、前記半導体チップの第１の主面に接合され当該第１の主面に設けられた電極に接続する第１の導電板と、前記半導体チップの第２の主面に接合され当該第２の主面に設けられた電極に接続する第２の導電板と、を備え、前記絶縁基板は、第１の導電板の、前記半導体チップに接合された面に対して反対側の面に接合される配線パターンが設けられた第１の絶縁基板と、第２の導電板の、前記半導体チップに接合された面に対して反対側の面に接合される配線パターンが設けられた第２の絶縁基板と、を備えることを特徴とする。   Moreover, in the semiconductor device according to the present invention, in the above-described invention, the conductive plate is bonded to the first main surface of the semiconductor chip and connected to an electrode provided on the first main surface. A plate, and a second conductive plate joined to the second main surface of the semiconductor chip and connected to an electrode provided on the second main surface, wherein the insulating substrate is formed of the first conductive plate. A first insulating substrate provided with a wiring pattern bonded to a surface opposite to the surface bonded to the semiconductor chip, and a surface of the second conductive plate bonded to the semiconductor chip And a second insulating substrate provided with a wiring pattern bonded to the opposite surface.

また、上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置の製造方法は、半導体チップの主面に、前記半導体チップの主面に設けられた電極と絶縁基板の主面に設けられた配線パターンとを電気的に接続する導電板の一方の面を接合する第１の接合工程と、前記絶縁基板の配線パターンが設けられた主面に、前記導電板の他方の面を接合する第２の接合工程と、を含み、前記第１の接合工程を前記第２の接合工程とともに行うことを特徴とする。   In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention includes an electrode provided on a main surface of a semiconductor chip and an insulating substrate provided on the main surface of the semiconductor chip. A first bonding step of bonding one surface of the conductive plate to electrically connect the wiring pattern provided on the main surface of the conductive substrate; and a main surface of the conductive substrate provided with the wiring pattern of the insulating substrate. A second joining step for joining the other surfaces, wherein the first joining step is performed together with the second joining step.

また、上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置の製造方法は、半導体チップの主面に、前記半導体チップの主面に設けられた電極と絶縁基板の主面に設けられた配線パターンとを電気的に接続する導電板の一方の面を接合する第１の接合工程と、前記絶縁基板の配線パターンが設けられた主面に、前記導電板の他方の面を接合する第２の接合工程と、を含み、前記第１の接合工程の後に、前記第２の接合工程を行うことを特徴とする。   In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention includes an electrode provided on a main surface of a semiconductor chip and an insulating substrate provided on the main surface of the semiconductor chip. A first bonding step of bonding one surface of the conductive plate to electrically connect the wiring pattern provided on the main surface of the conductive substrate; and a main surface of the conductive substrate provided with the wiring pattern of the insulating substrate. A second joining step for joining the other surfaces, and the second joining step is performed after the first joining step.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記第２の接合工程では、前記絶縁基板の配線パターンに設けられた凹部に、前記導電板の他方の面に設けられた突起部を挿入し、前記絶縁基板の主面に水平な方向における前記絶縁基板と前記導電板との接合位置を固定することを特徴とする。   In the semiconductor device manufacturing method according to the present invention, in the above-described invention, in the second bonding step, the concave portion provided in the wiring pattern of the insulating substrate is provided on the other surface of the conductive plate. A protrusion is inserted to fix the bonding position of the insulating substrate and the conductive plate in a direction horizontal to the main surface of the insulating substrate.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記導電板の他方の面に設けられた凹部に導電体の一方の端部を挿入し、前記絶縁基板の配線パターンの、前記導電板の凹部に対応する位置に設けられた凹部に前記導電体の他方の端部を挿入し、前記絶縁基板の主面に水平な方向における前記絶縁基板と前記導電板との接合位置を固定することを特徴とする。   Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, one end of a conductor is inserted into a recess provided on the other surface of the conductive plate, and the wiring pattern of the insulating substrate is The other end of the conductor is inserted into a recess provided at a position corresponding to the recess of the conductive plate, and the bonding position of the insulating substrate and the conductive plate in a direction horizontal to the main surface of the insulating substrate is determined. It is fixed.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記半導体チップの線膨張係数α１、前記導電板の線膨張係数α２、および前記絶縁基板の配線パターンの線膨張係数α３は、α１＜α２＜α３を満たすことを特徴とする。   Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, the linear expansion coefficient α1 of the semiconductor chip, the linear expansion coefficient α2 of the conductive plate, and the linear expansion coefficient α3 of the wiring pattern of the insulating substrate are: It is characterized by satisfying α1 <α2 <α3.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記導電板は、モリブデン、タングステン、銅とモリブデンとからなる合金、鉄とニッケルとからなる合金、または、鉄とニッケルとコバルトとからなる合金、もしくはこれらの金属および合金を２種類以上組み合わせて形成される複合材料で構成されていることを特徴とする。   In the semiconductor device manufacturing method according to the present invention, the conductive plate may be molybdenum, tungsten, an alloy made of copper and molybdenum, an alloy made of iron and nickel, or iron, nickel and cobalt. Or a composite material formed by combining two or more of these metals and alloys.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記絶縁基板の配線パターンは、銅、アルミニウム、銀またはニッケルで構成されていることを特徴とする。   In the semiconductor device manufacturing method according to the present invention, the wiring pattern of the insulating substrate is made of copper, aluminum, silver, or nickel in the above-described invention.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記絶縁基板の配線パターンに、複数の前記導電板を接合し、前記絶縁基板の配線パターンに接合された複数の前記導電板のそれぞれに前記半導体チップを接合することを特徴とする。   According to the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, a plurality of the conductive plates are bonded to the wiring pattern of the insulating substrate, and the plurality of conductive plates are bonded to the wiring pattern of the insulating substrate. The semiconductor chip is bonded to each of the above.

上述した発明にかかる半導体装置によれば、半導体チップと絶縁基板とを導電板によって接合し、半導体チップの表面電極と絶縁基板の配線パターンとを電気的に接続する。これにより、従来のように半導体チップのおもて面電極と絶縁基板の配線パターンとを接続するためのアルミワイヤを設ける必要がなくなるので、アルミワイヤを接続するためだけの配線パターンを絶縁基板上に設ける必要がなくなる。また、上述した発明にかかる半導体装置によれば、半導体チップのおもて面に導電板を介して接合される絶縁基板の上側に設けられる外部接続端子の配置間隔を狭くすることができる。   According to the above-described semiconductor device, the semiconductor chip and the insulating substrate are joined by the conductive plate, and the surface electrode of the semiconductor chip and the wiring pattern of the insulating substrate are electrically connected. As a result, there is no need to provide an aluminum wire for connecting the front electrode of the semiconductor chip and the wiring pattern of the insulating substrate as in the prior art, so a wiring pattern only for connecting the aluminum wire is provided on the insulating substrate. There is no need to provide it. Moreover, according to the semiconductor device concerning the above-mentioned invention, the arrangement | positioning space | interval of the external connection terminal provided in the upper side of the insulating substrate joined to the front surface of a semiconductor chip via a conductive plate can be narrowed.

また、上述した発明にかかる半導体装置によれば、半導体チップと絶縁基板との間に導電板を接合することで、半導体チップ、導電板および絶縁基板の配線パターンの線膨張係数の差が最小化され、各部材の接合部分で生じる歪が各部材に均等に分担される。このため、半導体チップに対する熱応力を低減させることができる。また、半導体チップと導電板とを接合する接合材、導電板と絶縁基板の配線パターンとを接合する接合材に対する熱応力を低減させることができる。   In addition, according to the above-described semiconductor device, the difference in the linear expansion coefficient between the wiring patterns of the semiconductor chip, the conductive plate, and the insulating substrate is minimized by bonding the conductive plate between the semiconductor chip and the insulating substrate. Thus, the distortion generated at the joint portion of each member is equally distributed to each member. For this reason, the thermal stress with respect to a semiconductor chip can be reduced. Further, it is possible to reduce thermal stress on the bonding material for bonding the semiconductor chip and the conductive plate, and the bonding material for bonding the conductive plate and the wiring pattern of the insulating substrate.

また、上述した発明にかかる半導体装置の製造方法によれば、絶縁基板の配線パターンに設けられた凹部に導電板に設けられた突起部を挿入することで、半導体チップの主面に水平な方向のアライメントを正確に決定することができる。また、上述した発明にかかる半導体装置の製造方法によれば、絶縁基板の配線パターンに設けられた凹部と、この凹部に対応する位置に設けられた導電板の凹部とに同一の導電体を挿入することで、半導体装置の半導体チップの主面に水平な方向のアライメントを正確に決定することができる。これにより、半導体チップ、導電板および絶縁基板を正確な位置で接合し一体化することができる。   In addition, according to the method for manufacturing a semiconductor device according to the above-described invention, the protrusions provided on the conductive plate are inserted into the recesses provided in the wiring pattern of the insulating substrate, so that the direction parallel to the main surface of the semiconductor chip. Can be accurately determined. Further, according to the method for manufacturing a semiconductor device according to the above-described invention, the same conductor is inserted into the recess provided in the wiring pattern of the insulating substrate and the recess of the conductive plate provided at a position corresponding to the recess. By doing so, it is possible to accurately determine the alignment in the horizontal direction to the main surface of the semiconductor chip of the semiconductor device. Thereby, a semiconductor chip, a conductive plate, and an insulating substrate can be joined and integrated at an accurate position.

また、上述した発明にかかる半導体装置の製造方法によれば、半導体チップと絶縁基板とを導電板によって接合することにより、半導体チップ、導電板および絶縁基板の配線パターンの線膨張係数の差を最小化させた半導体装置を提供することができる。これにより、半導体チップに対する熱応力を低減させた半導体装置を提供することができる。   In addition, according to the method for manufacturing a semiconductor device according to the above-described invention, the difference between the linear expansion coefficients of the wiring patterns of the semiconductor chip, the conductive plate, and the insulating substrate is minimized by joining the semiconductor chip and the insulating substrate with the conductive plate. A semiconductor device can be provided. Thereby, it is possible to provide a semiconductor device with reduced thermal stress on the semiconductor chip.

本発明にかかる半導体装置および半導体装置の製造方法によれば、小型化を実現することができるという効果を奏する。また、本発明にかかる半導体装置および半導体装置の製造方法によれば、信頼性の高い半導体装置を提供することができるという効果を奏する。   According to the semiconductor device and the manufacturing method of the semiconductor device according to the present invention, there is an effect that downsizing can be realized. In addition, according to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to provide a highly reliable semiconductor device.

実施の形態１にかかる半導体装置の構造について示す断面図である。1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment; 実施の形態１にかかる半導体装置の各部材の構成について示す断面図である。FIG. 3 is a cross-sectional view illustrating a configuration of each member of the semiconductor device according to the first embodiment. 実施の形態２にかかる半導体装置の構造について示す断面図である。FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment. 実施の形態２にかかる半導体装置の各部材の構成について示す断面図である。FIG. 6 is a cross-sectional view illustrating a configuration of each member of a semiconductor device according to a second embodiment. 実施の形態３にかかる製造途中の半導体装置について示す断面図である。FIG. 6 is a cross-sectional view illustrating a semiconductor device that is being manufactured according to a third embodiment; 従来の半導体装置の構造について示す断面図である。It is sectional drawing shown about the structure of the conventional semiconductor device.

以下に添付図面を参照して、この発明にかかる半導体装置および半導体装置の製造方法の好適な実施の形態を詳細に説明する。なお、以下の実施の形態の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。   Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

（実施の形態１）
図１は、実施の形態１にかかる半導体装置の構造について示す断面図である。また、図２は、実施の形態１にかかる半導体装置の各部材の構成について示す断面図である。図２には、半導体装置１０を構成する各部材の接合前の状態を示す。図１に示すように、半導体装置１０は、半導体チップ１と、第１の導電板２−１と、第２の導電板２−２と、第１の配線基板３と、第２の配線基板４と、を備える。 (Embodiment 1)
FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view illustrating the configuration of each member of the semiconductor device according to the first embodiment. FIG. 2 shows a state before each member constituting the semiconductor device 10 is joined. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor chip 1, a first conductive plate 2-1, a second conductive plate 2-2, a first wiring substrate 3, and a second wiring substrate. 4.

半導体チップ１には、図示省略する１つ以上のデバイスが設けられている。半導体チップ１に設けられるデバイスとは、例えば、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲート型バイポーラトランジスタ）、ダイオード、ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲート型電界効果トランジスタ）などである。   The semiconductor chip 1 is provided with one or more devices not shown. The device provided in the semiconductor chip 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor), a diode, a MOSFET (Metal Oxide Semiconductor Field Transistor, or an insulated gate field effect transistor).

第１の配線基板３は、絶縁基板のおもて面に回路パターン（配線パターン）３ａを形成した基板である。第１の導電板２−１は、半導体チップ１の裏面に設けられた図示省略した１つ以上の電極（以下、裏面電極とする）と第１の配線基板３の回路パターン３ａとを電気的に接続する部材である。半導体チップ１の裏面は、図示省略した接合材を介して第１の導電板２−１と接合している。第１の導電板２−１の、半導体チップ１と接合している面に対して反対側の面は、図示省略した接合材を介して第１の配線基板３の回路パターン３ａと接合している。   The first wiring substrate 3 is a substrate in which a circuit pattern (wiring pattern) 3a is formed on the front surface of the insulating substrate. The first conductive plate 2-1 electrically connects one or more electrodes (hereinafter referred to as a back electrode) (not shown) provided on the back surface of the semiconductor chip 1 and the circuit pattern 3 a of the first wiring board 3. It is a member connected to. The back surface of the semiconductor chip 1 is bonded to the first conductive plate 2-1 through a bonding material (not shown). The surface of the first conductive plate 2-1 opposite to the surface bonded to the semiconductor chip 1 is bonded to the circuit pattern 3a of the first wiring board 3 via a bonding material not shown. Yes.

第１の導電板２−１の、第１の配線基板３と接合される側の面には、例えば円柱状の複数の突起部１１が設けられている。第１の配線基板３の回路パターン３ａには、第１の導電板２−１の各突起部１１に対応する位置にそれぞれ凹部３ａ−１が設けられている。第１の導電板２−１と第１の配線基板３の回路パターン３ａとは、図示省略する接合材を介して、第１の配線基板３の回路パターン３ａに設けられた凹部３ａ−１に第１の導電板２−１の突起部１１が挿入された状態で接合され一体化される。   For example, a plurality of columnar protrusions 11 are provided on the surface of the first conductive plate 2-1 on the side to be joined to the first wiring board 3. The circuit pattern 3a of the first wiring board 3 is provided with a recess 3a-1 at a position corresponding to each protrusion 11 of the first conductive plate 2-1. The first conductive plate 2-1 and the circuit pattern 3a of the first wiring board 3 are connected to the recess 3a-1 provided in the circuit pattern 3a of the first wiring board 3 through a bonding material (not shown). The protrusions 11 of the first conductive plate 2-1 are joined and integrated in the inserted state.

このように半導体チップ１、第１の導電板２−１および第１の配線基板３が一体化されることにより、半導体チップ１の裏面電極と第１の配線基板３の回路パターン３ａとが第１の導電板２−１を介して電気的に接続される。第１の配線基板３の裏面には金属接合層３ｂが設けられており、この金属接合層３ｂが図示を省略した接合材を介して図示省略したヒートシンクと接合している。   As described above, the semiconductor chip 1, the first conductive plate 2-1, and the first wiring board 3 are integrated, whereby the back electrode of the semiconductor chip 1 and the circuit pattern 3a of the first wiring board 3 are connected to each other. Electrically connected via one conductive plate 2-1. A metal bonding layer 3b is provided on the back surface of the first wiring board 3, and the metal bonding layer 3b is bonded to a heat sink (not shown) via a bonding material (not shown).

第２の導電板２−２は、半導体チップ１のおもて面に設けられた図示省略した１つ以上の電極（以下、おもて面電極とする）と第２の配線基板４の回路パターン４ａとを電気的に接続する部材である。半導体チップ１のおもて面は、図示省略した接合材を介して第２の導電板２−２と接合している。第２の導電板２−２の、半導体チップ１と接合している面に対して反対側の面は、図示省略した接合材を介して第２の配線基板４の回路パターン４ａと接合している。第２の導電板２−２の、第２の配線基板４の回路パターン４ａと接合される側の面には、複数の突起部１２が設けられている。   The second conductive plate 2-2 is a circuit of one or more electrodes (hereinafter referred to as front surface electrodes) (not shown) provided on the front surface of the semiconductor chip 1 and the second wiring board 4. It is a member that electrically connects the pattern 4a. The front surface of the semiconductor chip 1 is bonded to the second conductive plate 2-2 via a bonding material (not shown). The surface of the second conductive plate 2-2 opposite to the surface bonded to the semiconductor chip 1 is bonded to the circuit pattern 4a of the second wiring board 4 via a bonding material not shown. Yes. A plurality of protrusions 12 are provided on the surface of the second conductive plate 2-2 on the side to be joined to the circuit pattern 4a of the second wiring board 4.

第２の配線基板４は、絶縁基板の裏面およびおもて面にそれぞれ回路パターン４ａ，４ｂを形成した基板である。第２の配線基板４は、例えば、回路パターンを形成した絶縁基板が少なくとも２層以上積層されてなる多層基板でできている。第２の配線基板４を構成する絶縁基板間（内層）にも図示を省略する回路パターンが形成されていてもよく、各回路パターンは例えば回路パターン４ａによって電気的に接続される。   The second wiring substrate 4 is a substrate in which circuit patterns 4a and 4b are formed on the back surface and the front surface of the insulating substrate, respectively. The second wiring substrate 4 is made of, for example, a multilayer substrate in which at least two insulating substrates on which a circuit pattern is formed are stacked. A circuit pattern (not shown) may be formed between the insulating substrates (inner layers) constituting the second wiring board 4, and each circuit pattern is electrically connected by, for example, a circuit pattern 4 a.

第２の配線基板４には、第２の配線基板４を貫通する貫通孔（以下、スルーホール部とする）４ａ−１が複数設けられている。各スルーホール部４ａ−１は、第２の導電板２−２の各突起部１２に対応する位置にそれぞれ設けられている。スルーホール部４ａ−１内には、当該スルーホール部４ａ−１の側壁から第２の配線基板４の裏面にまたがって設けられた回路パターン４ａによって凹部４ａ−２が設けられている。回路パターン４ａは、スルーホール部４ａ−１を通じて、第２の配線基板４のおもて面に形成された回路パターン４ｂに接続されている。   The second wiring board 4 is provided with a plurality of through-holes (hereinafter referred to as through-hole portions) 4a-1 penetrating the second wiring board 4. Each through hole 4a-1 is provided at a position corresponding to each protrusion 12 of the second conductive plate 2-2. In the through hole portion 4a-1, a concave portion 4a-2 is provided by a circuit pattern 4a provided across the side wall of the through hole portion 4a-1 and the back surface of the second wiring board 4. The circuit pattern 4a is connected to the circuit pattern 4b formed on the front surface of the second wiring board 4 through the through hole portion 4a-1.

スルーホール部４ａ−１内に形成された凹部４ａ−２には、第２の配線基板４と第２の導電板２−２とが接合されたときに第２の導電板２−２の突起部１２と接する導電層４ａ−３が埋め込まれている。そして、スルーホール部４ａ−１内には、導電層４ａ−３を底面とし、かつ回路パターン４ａを側壁とする凹部４ａ−４が設けられている。   In the recess 4a-2 formed in the through-hole portion 4a-1, the protrusion of the second conductive plate 2-2 when the second wiring board 4 and the second conductive plate 2-2 are joined. A conductive layer 4a-3 in contact with the portion 12 is embedded. And in the through-hole part 4a-1, the recessed part 4a-4 which makes the conductive layer 4a-3 a bottom face and uses the circuit pattern 4a as a side wall is provided.

第２の導電板２−２と第２の配線基板４の回路パターン４ａとは、図示省略する接合材を介して、第２の配線基板４の回路パターン４ａに設けられた凹部４ａ−４に第２の導電板２−２の突起部１２が挿入された状態で接合され一体化される。これにより、半導体チップ１のおもて面電極と第２の配線基板４の回路パターン４ａとが第２の導電板２−２を介して電気的に接続される。   The second conductive plate 2-2 and the circuit pattern 4a of the second wiring board 4 are connected to a recess 4a-4 provided in the circuit pattern 4a of the second wiring board 4 through a bonding material (not shown). The projections 12 of the second conductive plate 2-2 are joined and integrated in the inserted state. Thereby, the front surface electrode of the semiconductor chip 1 and the circuit pattern 4a of the second wiring substrate 4 are electrically connected via the second conductive plate 2-2.

つぎに、図１に示す半導体装置１０の製造方法について説明する。まず、図２に示すように、半導体装置１０を構成する第１，２の導電板２−１，２−２、および、第１，２の配線基板３，４を形成する。具体的には、第１の導電板２−１に予め突起部１１を形成する。第２の導電板２−２に予め突起部１２を形成する。第１の配線基板３の回路パターン３ａに予め凹部３ａ−１を形成する。第２の配線基板４の回路パターン４ａに予め凹部４ａ−４を形成する。より具体的には、第１，２の導電板２−１，２−２、および、第１，２の配線基板３，４は、次のように形成される。   Next, a method for manufacturing the semiconductor device 10 shown in FIG. 1 will be described. First, as shown in FIG. 2, first and second conductive plates 2-1 and 2-2 and first and second wiring boards 3 and 4 constituting the semiconductor device 10 are formed. Specifically, the protrusion 11 is formed in advance on the first conductive plate 2-1. The protrusion 12 is formed in advance on the second conductive plate 2-2. A recess 3 a-1 is formed in advance in the circuit pattern 3 a of the first wiring board 3. A recess 4 a-4 is formed in advance in the circuit pattern 4 a of the second wiring board 4. More specifically, the first and second conductive plates 2-1 and 2-2 and the first and second wiring boards 3 and 4 are formed as follows.

第１の導電板２−１の突起部１１は、例えば、第１の導電板２−１の外形加工を行う前または後に、第１の導電板２−１の、第１の配線基板３と接合される側の面を塑性加工（プレス加工）によって変形させることで形成される。また、第１の導電板２−１の突起部１１は、例えば、第１の導電板２−１の、第１の配線基板３と接合される側の面を、エッチング処理や化学的処理によって部分的に除去することで形成されてもよい。第２の導電板２−２の突起部１２は、例えば、第１の導電板２−１の突起部１１と同様の方法で、第２の配線基板４と接合される側の面に形成される。   The protruding portion 11 of the first conductive plate 2-1 is, for example, before or after the outer shape of the first conductive plate 2-1 is formed, with the first wiring board 3 of the first conductive plate 2-1. It is formed by deforming the surfaces to be joined by plastic working (press working). In addition, the protrusion 11 of the first conductive plate 2-1 may be formed by etching or chemically treating the surface of the first conductive plate 2-1 that is bonded to the first wiring board 3. You may form by removing partially. The protruding portion 12 of the second conductive plate 2-2 is formed on the surface on the side to be joined to the second wiring board 4 by the same method as the protruding portion 11 of the first conductive plate 2-1, for example. The

第１の配線基板３には、例えばセラミック系の絶縁基板を用いてもよい。回路パターン３ａを構成する材料には、例えば、第１の配線基板３と第１の導電板２−１とを接合する接合材よりも融点の高い材料を用いてもよい。第１の配線基板３がセラミック系の絶縁基板であり、回路パターン３ａが接合材よりも融点の高い材料でできている場合、第１の配線基板３の回路パターン３ａに設けられた凹部３ａ−１は、例えば、次のように形成される。   For example, a ceramic insulating substrate may be used as the first wiring substrate 3. As a material constituting the circuit pattern 3a, for example, a material having a melting point higher than that of a bonding material for bonding the first wiring board 3 and the first conductive plate 2-1 may be used. When the first wiring substrate 3 is a ceramic insulating substrate and the circuit pattern 3a is made of a material having a melting point higher than that of the bonding material, the recess 3a- provided in the circuit pattern 3a of the first wiring substrate 3 For example, 1 is formed as follows.

まず、回路パターン３ａと第１の配線基板３とを接合する前に、回路パターン３ａの、第１の導電板２−１に接合される側の面を例えば塑性加工によって変形させ、例えばドット状の平面形状を有する複数の凹部３ａ−１を形成する。各凹部３ａ−１は、第１の配線基板３に接合される第１の導電板２−１の突起部１１に対応する位置に形成される。その後、回路パターン３ａの凹部３ａ−１を形成した面に対して反対側の平坦面と、第１の配線基板３の平坦面とを面接合する。または、第１の配線基板３の平坦面に接合した箔状の回路パターン３ａを完全に溶融し、溶融した回路パターン３ａを成型加工し凹部３ａ−１を成形してもよい。この場合、回路パターン３ａを構成する材料として例えばアルミニウムを用いてもよい。   First, before joining the circuit pattern 3a and the first wiring board 3, the surface of the circuit pattern 3a on the side to be joined to the first conductive plate 2-1 is deformed by, for example, plastic working, for example, a dot shape A plurality of recesses 3a-1 having a planar shape are formed. Each recess 3 a-1 is formed at a position corresponding to the protrusion 11 of the first conductive plate 2-1 joined to the first wiring board 3. Thereafter, the flat surface opposite to the surface on which the concave portion 3a-1 of the circuit pattern 3a is formed and the flat surface of the first wiring board 3 are surface-bonded. Alternatively, the foil-like circuit pattern 3a bonded to the flat surface of the first wiring board 3 may be completely melted, and the melted circuit pattern 3a may be molded to form the recess 3a-1. In this case, for example, aluminum may be used as a material constituting the circuit pattern 3a.

また、第１の配線基板３は、次のように形成されてもよい。まず、第１の配線基板３の平坦面に、箔状の回路パターン３ａを接合する。つぎに、フォトリソグラフィによって、回路パターン３ａの表面に、凹部３ａ−１の形成領域が開口するエッチングマスクを形成する。その後、エッチングマスクをマスクとしてエッチングを行い、エッチングマスクの開口部に露出する回路パターン３ａを、第１の配線基板３が露出しない深さで除去する。これにより、第１の配線基板３の回路パターン３ａに、複数の凹部３ａ−１が形成される。   The first wiring board 3 may be formed as follows. First, a foil-like circuit pattern 3 a is bonded to the flat surface of the first wiring board 3. Next, an etching mask is formed on the surface of the circuit pattern 3a by photolithography so that the formation region of the recess 3a-1 is opened. Thereafter, etching is performed using the etching mask as a mask, and the circuit pattern 3a exposed at the opening of the etching mask is removed at a depth at which the first wiring substrate 3 is not exposed. As a result, a plurality of recesses 3 a-1 are formed in the circuit pattern 3 a of the first wiring board 3.

第２の配線基板４の凹部４ａ−４は、例えば、次のように形成される。第２の配線基板４に、第２の配線基板４を貫通するスルーホール部４ａ−１を形成する。そして、スルーホール部４ａ−１内に、第２の配線基板４の裏面側から凹部４ａ−４が形成されるように、第２の配線基板４の裏面に回路パターン４ａおよび導電層４ａ−３を順に積層する。このとき、スルーホール部４ａ−１を通して第２の配線基板４のおもて面に形成された回路パターン４ｂに回路パターン４ａを接続し導通させる。   The recess 4a-4 of the second wiring substrate 4 is formed as follows, for example. A through hole portion 4 a-1 that penetrates the second wiring substrate 4 is formed in the second wiring substrate 4. Then, the circuit pattern 4a and the conductive layer 4a-3 are formed on the back surface of the second wiring board 4 so that the recess 4a-4 is formed from the back surface side of the second wiring board 4 in the through hole portion 4a-1. Are sequentially stacked. At this time, the circuit pattern 4a is connected to the circuit pattern 4b formed on the front surface of the second wiring board 4 through the through-hole portion 4a-1 so as to be conductive.

第１，２の配線基板３，４などの絶縁材と回路パターン３ａ，３ｂ，４ａ，４ｂなどの導体パターンは、次のように接合される。例えば、窒化アルミニウム（ＡｌＮ）および窒化珪素（Ｓｉ3Ｎ4）からなる絶縁材に、銅（Ｃｕ）からなる導体パターンを接合する場合を例に説明する。接合材として、絶縁材および導体パターンよりも融点の低い、例えば銀（Ａｇ）−銅−チタン（Ｔｉ）からなる合金（以下、ろう材とする）を用いる。ろう材の融点は、約７００℃である。 The insulating material such as the first and second wiring boards 3 and 4 and the conductor pattern such as the circuit patterns 3a, 3b, 4a, and 4b are joined as follows. For example, a case where a conductor pattern made of copper (Cu) is bonded to an insulating material made of aluminum nitride (AlN) and silicon nitride (Si 3 N 4 ) will be described as an example. As the bonding material, an alloy (hereinafter referred to as a brazing material) made of, for example, silver (Ag) -copper-titanium (Ti) having a melting point lower than that of the insulating material and the conductor pattern is used. The melting point of the brazing material is about 700 ° C.

まず、絶縁材と導体パターンとの間に板状のろう材を挿入し、絶縁材と導体パターンとを重ね合わせる。そして、ろう材の融点よりも２０〜８０℃高い加熱温度で当該重ね合わせた部材を加熱する。これにより、絶縁材および導体パターンの固相状態を保った状態で、ろう材のみが溶融される。導体パターン側では、ろう材が冷却されるときに生じる銀および銅の共晶との金属結合によって、導体パターンとろう材とが接合される。絶縁材側では、ろう材に添加物として混合されたチタンとの化合物反応が促進し、絶縁材とろう材とが物理的に接合される。   First, a plate-like brazing material is inserted between the insulating material and the conductor pattern, and the insulating material and the conductor pattern are overlapped. Then, the superposed member is heated at a heating temperature 20 to 80 ° C. higher than the melting point of the brazing material. As a result, only the brazing material is melted while maintaining the solid state of the insulating material and the conductor pattern. On the conductor pattern side, the conductor pattern and the brazing material are joined by metal bonding with silver and copper eutectic that occurs when the brazing material is cooled. On the insulating material side, the compound reaction with titanium mixed as an additive in the brazing material is promoted, and the insulating material and the brazing material are physically joined.

このため、例えば、予め凹部３ａ−１が形成された状態で回路パターン３ａを第１の配線基板３に接合する場合でも、回路パターン３ａの固相状態を保った状態で第１の配線基板３に接合される。これにより、回路パターン３ａに予め形成された凹部３ａ−１は、回路パターン３ａと第１の配線基板３との接合後においても、変形することなく回路パターン３ａに残る。第１の配線基板３に回路パターン３ｂを接合する方法、第２の配線基板４に回路パターン４ａ，４ｂを接合する方法は、第１の配線基板３に回路パターン３ａを接合する方法と同様である。   For this reason, for example, even when the circuit pattern 3a is bonded to the first wiring board 3 in a state where the recesses 3a-1 are formed in advance, the first wiring board 3 is maintained in a state where the circuit pattern 3a is kept in a solid phase. To be joined. Thereby, the recess 3a-1 formed in advance in the circuit pattern 3a remains in the circuit pattern 3a without being deformed even after the circuit pattern 3a and the first wiring board 3 are joined. The method of bonding the circuit pattern 3 b to the first wiring board 3 and the method of bonding the circuit patterns 4 a and 4 b to the second wiring board 4 are the same as the method of bonding the circuit pattern 3 a to the first wiring board 3. is there.

上述したように予め突起部１１，１２が形成された第１，２の導電板２−１，２−２、および、予め凹部３ａ−１，４ａ−４が形成された第１，２の配線基板３，４の回路パターン３ａ，４ａの表面に、各部材どうしを接合する接合材と反応しやすい金属膜（図示省略）を形成する。そして、第１の配線基板３の回路パターン３ａに設けられた凹部３ａ−１に第１の導電板２−１の突起部１１を挿入し、第１の配線基板３上に第１の導電板２−１を重ねる。また、この第１の導電板２−１上に、半導体チップ１の裏面を下にして重ね、半導体チップ１上に、突起部１２が形成された側の面に対して反対側の面を下にして第２の導電板２−２を重ねる。   As described above, the first and second conductive plates 2-1 and 2-2 in which the protrusions 11 and 12 are formed in advance, and the first and second wirings in which the recesses 3a-1 and 4a-4 are formed in advance. On the surfaces of the circuit patterns 3a and 4a of the substrates 3 and 4, a metal film (not shown) that easily reacts with a bonding material for bonding the members is formed. Then, the protrusion 11 of the first conductive plate 2-1 is inserted into the recess 3a-1 provided in the circuit pattern 3a of the first wiring board 3, and the first conductive plate is placed on the first wiring board 3. 2-1. Further, the semiconductor chip 1 is overlaid on the first conductive plate 2-1, with the back surface thereof facing down, and the surface opposite to the surface on which the protrusions 12 are formed on the semiconductor chip 1 Then, the second conductive plate 2-2 is overlapped.

さらに、第２の配線基板４の回路パターン４ａに設けられた凹部４ａ−４が第２の導電板２−２の突起部１２に挿入されるように、第２の導電板２−２上に第２の配線基板４を重ねる。これらの部材は、各部材間にそれぞれ箔状の接合材（図示省略）を挿入した状態で重ね合わされる。その後、重ね合わされた各部材を一括して加熱することで、各部材間にそれぞれ挿入された接合材を介して、第１の配線基板３、第１の導電板２−１、半導体チップ１、第２の導電板２−２、および第２の配線基板４がそれぞれ接合され一体化される。これにより、図１に示す半導体装置１０が完成する。   Further, on the second conductive plate 2-2, the concave portion 4a-4 provided in the circuit pattern 4a of the second wiring board 4 is inserted into the protrusion 12 of the second conductive plate 2-2. The second wiring board 4 is stacked. These members are overlapped in a state where a foil-like bonding material (not shown) is inserted between the members. After that, by heating the overlapped members in a lump, the first wiring board 3, the first conductive plate 2-1, the semiconductor chip 1, and the like, via the bonding materials inserted between the members, The second conductive plate 2-2 and the second wiring board 4 are joined and integrated. Thereby, the semiconductor device 10 shown in FIG. 1 is completed.

第１，２の導電板２−１，２−２、第１，２の配線基板３，４をそれぞれ構成する材料は、半導体装置１０の支持材となる第１，２の配線基板３，４と、半導体チップ１との線膨張係数の差がそれぞれの接合界面で吸収される構成となるように選択するのが好ましい。具体的には、第１，２の導電板２−１，２−２、第１，２の配線基板３，４をそれぞれ構成する材料の組み合わせは、隣接する部材どうしの線膨張係数の差が最小化される組み合わせとするのが望ましい。   The materials constituting the first and second conductive plates 2-1 and 2-2 and the first and second wiring boards 3 and 4 are the first and second wiring boards 3 and 4 that serve as support materials for the semiconductor device 10. It is preferable to select such that the difference in linear expansion coefficient with the semiconductor chip 1 is absorbed at each bonding interface. Specifically, the combination of materials constituting the first and second conductive plates 2-1 and 2-2 and the first and second wiring boards 3 and 4 has a difference in coefficient of linear expansion between adjacent members. It is desirable that the combination be minimized.

より具体的には、半導体チップ１の線膨張係数α１は、例えば半導体チップ１が通常のシリコン（Ｓｉ）からなる場合、４ｐｐｍ／Ｋ程度である。一方、例えば第１，２の配線基板３，４の回路パターン３ａ，４ａが銅からなる場合、第１，２の配線基板３，４の回路パターン３ａ，４ａの線膨張係数α３は１８ｐｐｍ／Ｋ程度である。このため、第１，２の導電板２−１，２−２の線膨張係数α２が９ｐｐｍ／Ｋ程度となるように、第１，２の導電板２−１，２−２を構成する材料を選択する。   More specifically, the linear expansion coefficient α1 of the semiconductor chip 1 is, for example, about 4 ppm / K when the semiconductor chip 1 is made of normal silicon (Si). On the other hand, for example, when the circuit patterns 3a and 4a of the first and second wiring boards 3 and 4 are made of copper, the linear expansion coefficient α3 of the circuit patterns 3a and 4a of the first and second wiring boards 3 and 4 is 18 ppm / K. Degree. Therefore, the materials constituting the first and second conductive plates 2-1 and 2-2 so that the linear expansion coefficient α2 of the first and second conductive plates 2-1 and 2-2 is about 9 ppm / K. Select.

このように、半導体チップ１、第１，２の導電板２−１，２−２、および、第１，２の配線基板３，４の回路パターン３ａ，４ａのそれぞれの線膨張係数α１，α２，α３が下記（１）式を満たすように各部材を構成する材料を選択する。これにより、各部材のそれぞれの接合部分で生じる歪は、各部材に均等に分担されるとともに、下記（１）式を満たさない材料からなる部材どうしが接合された場合よりも各部材の線膨張係数の差が最小化される。   Thus, the linear expansion coefficients α1, α2 of the semiconductor chip 1, the first and second conductive plates 2-1, 2-2, and the circuit patterns 3a, 4a of the first, second wiring boards 3, 4, respectively. , Α3 satisfies the following expression (1), and the material constituting each member is selected. As a result, the strain generated at each joint portion of each member is equally distributed to each member, and the linear expansion of each member is greater than when the members made of materials that do not satisfy the following formula (1) are joined. Coefficient differences are minimized.

α１＜α２＜α３ ・・・（１）   α1 <α2 <α3 (1)

例えば、半導体チップ１がシリコンで構成され、第１，２の配線基板３，４の回路パターン３ａ，４ａが銅で構成される場合、第１，２の導電板２−１，２−２を銅−モリブデン（Ｍｏ）からなる合金で構成してもよい。第１，２の導電板２−１，２−２を銅−モリブデンからなる合金で構成する場合、この合金の体積割合（固相率）が１５〜４５％となるように第１，２の導電材２−１，２−２を構成することで、上記（１）式を満たす半導体チップ１、第１，２の導電板２−１，２−２、および第１，２の配線基板３，４の回路パターン３ａ，４ａが得られる。   For example, when the semiconductor chip 1 is made of silicon and the circuit patterns 3a and 4a of the first and second wiring boards 3 and 4 are made of copper, the first and second conductive plates 2-1 and 2-2 are formed. You may comprise with the alloy which consists of copper-molybdenum (Mo). When the first and second conductive plates 2-1 and 2-2 are made of an alloy made of copper-molybdenum, the first and second conductive plates 2-1 and 2-2 are adjusted so that the volume ratio (solid phase ratio) of the alloy is 15 to 45%. By configuring the conductive materials 2-1 and 2-2, the semiconductor chip 1, the first and second conductive plates 2-1 and 2-2, and the first and second wiring boards 3 that satisfy the above formula (1) are satisfied. , 4 circuit patterns 3a, 4a are obtained.

また、例えば、半導体チップ１がシリコンからなり、第１，２の配線基板３，４の回路パターン３ａ，４ａが銅からなる場合、第１，２の導電板２−１，２−２を鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバルト（Ｃｏ）からなる合金で構成してもよい。第１，２の導電板２−１，２−２を鉄−ニッケル−コバルトからなる合金で構成する場合においても、第１，２の導電板２−１，２−２を銅−モリブデンからなる合金で構成した場合と同様の、第１，２の導電板２−１，２−２の線膨張係数α２が得られる。   For example, when the semiconductor chip 1 is made of silicon and the circuit patterns 3a and 4a of the first and second wiring boards 3 and 4 are made of copper, the first and second conductive plates 2-1 and 2-2 are made of iron. You may comprise with the alloy which consists of (Fe) -nickel (Ni) -cobalt (Co). Even when the first and second conductive plates 2-1 and 2-2 are made of an alloy of iron-nickel-cobalt, the first and second conductive plates 2-1 and 2-2 are made of copper-molybdenum. The linear expansion coefficient α2 of the first and second conductive plates 2-1 and 2-2, which is the same as that of the alloy, is obtained.

詳細には、第１，２の導電板２−１，２−２は、モリブデン、タングステン（Ｗ）、銅−モリブデンからなる合金、鉄−ニッケルからなる合金、または鉄−ニッケル−コバルトからなる合金で構成されてもよいし、これらの金属および合金を２種類以上組み合わせて形成される複合材料で構成されてもよい。また、第１，２の配線基板３，４の回路パターン３ａ，４ａは、銅、アルミニウム（Ａｌ）、銀またはニッケルで構成されてもよい。   Specifically, the first and second conductive plates 2-1 and 2-2 are molybdenum, tungsten (W), an alloy made of copper-molybdenum, an alloy made of iron-nickel, or an alloy made of iron-nickel-cobalt. Or a composite material formed by combining two or more of these metals and alloys. The circuit patterns 3a and 4a of the first and second wiring boards 3 and 4 may be made of copper, aluminum (Al), silver, or nickel.

半導体チップ１と第１，２の導電板２−１，２−２、および、第１，２の導電板２−１，２−２と第１，２の配線基板３，４の回路パターン３ａ，４ａとを接合する接合材として、例えば、錫（Ｓｎ）系のはんだを用いてもよい。具体的には、接合材として、例えば、錫−銀、硫黄（Ｓ）−アンチモン（Ｓｂ）、錫−銅、錫−ビスマス（Ｂｉ）、または錫−亜鉛（Ｚｎ）などを含むはんだを用いてもよい。   Circuit pattern 3a of semiconductor chip 1 and first and second conductive plates 2-1 and 2-2, and first and second conductive plates 2-1 and 2-2 and first and second wiring boards 3 and 4. , 4a, for example, tin (Sn) solder may be used. Specifically, as a bonding material, for example, a solder containing tin-silver, sulfur (S) -antimony (Sb), tin-copper, tin-bismuth (Bi), tin-zinc (Zn), or the like is used. Also good.

接合材として錫（Ｓｎ）系のはんだを用いる場合、各部材と接合材との化学反応を高めるために各部材の表面に形成される金属膜は、ニッケル、ニッケル−リン（Ｐ）からなる合金、銀、銀−パラジウムからなる合金（Ｐｄ）からなる合金、金（Ａｕ）または錫を成分とする金属膜であってもよいし、これらの金属または合金を２つ以上積層してなる多層膜であってもよい。この金属膜は、例えば、スパッタリング法や蒸着法によって各部材の表面に形成される。   When tin (Sn) -based solder is used as the bonding material, the metal film formed on the surface of each member in order to enhance the chemical reaction between each member and the bonding material is an alloy composed of nickel and nickel-phosphorus (P). , An alloy made of silver, a silver-palladium alloy (Pd), a metal film containing gold (Au) or tin as a component, or a multilayer film formed by laminating two or more of these metals or alloys It may be. This metal film is formed on the surface of each member by, for example, sputtering or vapor deposition.

以上、説明したように、実施の形態１にかかる半導体装置１０によれば、半導体チップ１と第１，２の配線基板３，４の回路パターン３ａ，４ａとをそれぞれ第１，２の導電板２−１，２−２によって接合する。これにより、従来のように半導体チップのおもて面電極と配線基板の回路パターンとを接続するためのアルミワイヤを設ける必要がなくなるので、アルミワイヤを接続するためだけの回路パターンを第１の配線基板３上に設ける必要がなくなる。これにより、配線基板を小型化することができ、半導体装置１０の小型化を実現することができる。また、半導体装置１０の小型化により、各部材の小型化が図れるので、従来よりもコストを低減することができる。   As described above, according to the semiconductor device 10 according to the first embodiment, the semiconductor chip 1 and the circuit patterns 3a and 4a of the first and second wiring boards 3 and 4 are respectively connected to the first and second conductive plates. It joins by 2-1 and 2-2. As a result, there is no need to provide an aluminum wire for connecting the front surface electrode of the semiconductor chip and the circuit pattern of the wiring board as in the prior art, so that the circuit pattern only for connecting the aluminum wire is provided in the first pattern. There is no need to provide the wiring board 3. Thereby, a wiring board can be reduced in size and the semiconductor device 10 can be reduced in size. Further, since the size of each member can be reduced by reducing the size of the semiconductor device 10, the cost can be reduced as compared with the conventional device.

また、実施の形態１にかかる半導体装置１０によれば、半導体チップ１のおもて面に第２の導電板２−２を介して接合される第２の配線基板４の上側に設けられる外部接続端子（図示省略）の配置間隔を狭くすることができる。また、実施の形態１にかかる半導体装置１０によれば、第１の配線基板３上にアルミワイヤを接続するためだけの回路パターンを設ける必要がないので、配線基板上に従来よりも多く半導体チップ１を実装することができる。これにより、従来よりも半導体装置１０の大容量化を図ることができる。   Further, according to the semiconductor device 10 according to the first embodiment, the external device provided on the upper side of the second wiring substrate 4 joined to the front surface of the semiconductor chip 1 via the second conductive plate 2-2. The arrangement interval of connection terminals (not shown) can be reduced. Further, according to the semiconductor device 10 according to the first embodiment, it is not necessary to provide a circuit pattern only for connecting an aluminum wire on the first wiring board 3, so that more semiconductor chips are provided on the wiring board than in the past. 1 can be implemented. Thereby, the capacity of the semiconductor device 10 can be increased as compared with the conventional case.

また、実施の形態１にかかる半導体装置１０によれば、半導体チップ１と第１，２の配線基板３，４との間に第１，２の導電板２−１，２−２を接合することで、半導体チップ１、第１，２の導電板２−１，２−２および第１，２の配線基板３，４の回路パターン３ａ，４ａの線膨張係数の差が最小化され、各部材の接合部分で生じる歪が各部材に均等に分担される。このため、半導体チップ１に対する熱応力を低減させることができる。また、半導体チップ１と第１，２の導電板２−１，２−２とを接合する接合材、第１，２の導電板２−１，２−２と第１，２の配線基板３，４の回路パターン３ａ，４ａとを接合する接合材に対する熱応力を低減させることができる。これにより、半導体装置１０の信頼性を高めることができる。   Further, according to the semiconductor device 10 according to the first embodiment, the first and second conductive plates 2-1 and 2-2 are joined between the semiconductor chip 1 and the first and second wiring boards 3 and 4. This minimizes the difference in linear expansion coefficient between the circuit patterns 3a and 4a of the semiconductor chip 1, the first and second conductive plates 2-1 and 2-2, and the first and second wiring boards 3 and 4. The distortion generated at the joint portion of the members is equally distributed to each member. For this reason, the thermal stress with respect to the semiconductor chip 1 can be reduced. Also, a bonding material for bonding the semiconductor chip 1 and the first and second conductive plates 2-1 and 2-2, the first and second conductive plates 2-1 and 2-2 and the first and second wiring boards 3. , 4 can be reduced in thermal stress on the bonding material for bonding the circuit patterns 3a, 4a. Thereby, the reliability of the semiconductor device 10 can be improved.

また、実施の形態１にかかる半導体装置１０の製造方法によれば、第１，２の配線基板３，４の回路パターン３ａ，４ａに設けられた凹部３ａ−１，４ａ−４に第１，２の導電板２−１，２−２に設けられた突起部１１，１２をそれぞれ挿入することで、半導体チップ１の主面に水平な方向のアライメントを正確に決定することができる。これにより、半導体チップ１、第１，２の導電板２−１，２−２および第１，２の配線基板３，４を正確な位置で接合し一体化することができる。したがって、信頼性の高い半導体装置１０を提供することができる。   Further, according to the manufacturing method of the semiconductor device 10 according to the first embodiment, the first and second recesses 3a-1 and 4a-4 provided in the circuit patterns 3a and 4a of the first and second wiring boards 3 and 4 are first and second. By inserting the protrusions 11 and 12 provided on the two conductive plates 2-1 and 2-2, the alignment in the horizontal direction on the main surface of the semiconductor chip 1 can be accurately determined. As a result, the semiconductor chip 1, the first and second conductive plates 2-1, 2-2, and the first and second wiring boards 3, 4 can be joined and integrated at accurate positions. Therefore, a highly reliable semiconductor device 10 can be provided.

また、実施の形態１にかかる半導体装置１０の製造方法によれば、半導体チップ１と第１，２の配線基板３，４の回路パターン３ａ，４ａとの間に第１，２の導電板２−１，２−２を接合することにより、半導体チップ１、第１，２の導電板２−１，２−２および第１，２の配線基板３，４の回路パターン３ａ，４ａの線膨張係数の差を最小化させた半導体装置１０を提供することができる。これにより、信頼性の高い半導体装置１０を提供することができる。また、第１の配線基板３上に従来よりも多く半導体チップ１を実装することができるので、従来よりも半導体装置１０の大容量化を図ることができる。   Further, according to the method of manufacturing the semiconductor device 10 according to the first embodiment, the first and second conductive plates 2 are disposed between the semiconductor chip 1 and the circuit patterns 3a and 4a of the first and second wiring boards 3 and 4. The linear expansion of the circuit patterns 3 a and 4 a of the semiconductor chip 1, the first and second conductive plates 2-1 and 2-2, and the first and second wiring boards 3 and 4 is performed by joining the −1 and 2-2. The semiconductor device 10 in which the difference in coefficients is minimized can be provided. Thereby, the highly reliable semiconductor device 10 can be provided. In addition, since more semiconductor chips 1 can be mounted on the first wiring substrate 3 than in the past, the capacity of the semiconductor device 10 can be increased as compared with the prior art.

（実施の形態２）
図３は、実施の形態２にかかる半導体装置の構造について示す断面図である。また、図４は、実施の形態２にかかる半導体装置の各部材の構成について示す断面図である。図４には、半導体装置２０を構成する各部材の接合前の状態を示す。実施の形態２にかかる半導体装置２０が実施の形態１にかかる半導体装置と異なるのは、第１，２の導電板の突起部に代えて、第１，２の導電板２１，２２に凹部２１−１，２２−１を設け、当該凹部２１−１，２２−１に円柱状の導電体２１−２，２２−２を挿入したことである。 (Embodiment 2)
FIG. 3 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment. FIG. 4 is a cross-sectional view illustrating the configuration of each member of the semiconductor device according to the second embodiment. FIG. 4 shows a state before each member constituting the semiconductor device 20 is joined. The semiconductor device 20 according to the second embodiment is different from the semiconductor device according to the first embodiment in that a recess 21 is formed in the first and second conductive plates 21 and 22 instead of the protrusions of the first and second conductive plates. -1 and 22-1 are provided, and cylindrical conductors 21-2 and 22-2 are inserted into the recesses 21-1 and 21-1.

図３に示すように、半導体装置２０は、半導体チップ１と、第１の導電板２１と、第２の導電板２２と、第１の配線基板３と、第２の配線基板４と、を備える。第１の導電板２１は、半導体チップ１の裏面電極と第１の配線基板３の回路パターン３ａとを電気的に接続する部材である。半導体チップ１の裏面は、図示省略した接合材を介して第１の導電板２１と接合している。   As shown in FIG. 3, the semiconductor device 20 includes the semiconductor chip 1, the first conductive plate 21, the second conductive plate 22, the first wiring substrate 3, and the second wiring substrate 4. Prepare. The first conductive plate 21 is a member that electrically connects the back electrode of the semiconductor chip 1 and the circuit pattern 3 a of the first wiring board 3. The back surface of the semiconductor chip 1 is bonded to the first conductive plate 21 via a bonding material (not shown).

第１の導電板２１の、半導体チップ１と接合している面に対して反対側の面には、例えばドット状の平面形状を有する凹部２１−１が複数設けられている。凹部２１−１には、円柱状の導電体２１−２の一方の端部が挿入される。導電体２１−２の他方の端部は、第１の配線基板３の回路パターン３ａに設けられた凹部３ａ−１に挿入される。第１の導電板２１と第１の配線基板３の回路パターン３ａとは、図示省略する接合材を介して、第１の配線基板３の回路パターン３ａに設けられた凹部３ａ−１と、この凹部３ａ−１に対応する位置に設けられた第１の導電板２１の凹部２１−１とに同一の導電体２１−２が挿入された状態で接合され一体化される。   A plurality of recesses 21-1 having, for example, a dot-like planar shape is provided on the surface of the first conductive plate 21 opposite to the surface bonded to the semiconductor chip 1. One end of a cylindrical conductor 21-2 is inserted into the recess 21-1. The other end of the conductor 21-2 is inserted into the recess 3a-1 provided in the circuit pattern 3a of the first wiring board 3. The first conductive plate 21 and the circuit pattern 3a of the first wiring board 3 are connected to the recess 3a-1 provided in the circuit pattern 3a of the first wiring board 3 through a bonding material (not shown), The same conductor 21-2 is joined and integrated with the recess 21-1 of the first conductive plate 21 provided at a position corresponding to the recess 3a-1.

第２の導電板２２は、半導体チップ１のおもて面電極と第２の配線基板４の回路パターン４ａとを電気的に接続する部材である。半導体チップ１のおもて面は、図示省略した接合材を介して第２の導電板２２と接合している。第２の導電板２２の、第２の配線基板４の回路パターン４ａと接合される側の面には、例えばドット状の平面形状を有する凹部２２−１が複数設けられている。凹部２２−１には、円柱状の導電体２２−２の一方の端部が挿入されている。導電体２２−２の他方の端部は、第２の配線基板４の回路パターン４ａに設けられた凹部４ａ−２に挿入される。   The second conductive plate 22 is a member that electrically connects the front surface electrode of the semiconductor chip 1 and the circuit pattern 4 a of the second wiring board 4. The front surface of the semiconductor chip 1 is bonded to the second conductive plate 22 via a bonding material (not shown). On the surface of the second conductive plate 22 on the side to be joined to the circuit pattern 4a of the second wiring board 4, a plurality of concave portions 22-1 having, for example, a dot-like planar shape are provided. One end of a cylindrical conductor 22-2 is inserted into the recess 22-1. The other end of the conductor 22-2 is inserted into the recess 4a-2 provided in the circuit pattern 4a of the second wiring board 4.

第２の導電板２２と第２の配線基板４の回路パターン４ａとは、図示省略する接合材を介して、第２の配線基板４の回路パターン４ａに設けられた凹部４ａ−２と、この凹部４ａ−２に対応する位置に設けられた第２の導電板２２の凹部２２−１とに同一の導電体２２−２が挿入された状態で接合され一体化される。導電体２２−２の軸方向の長さは、例えば、凹部４ａ−２の深さに合わせて適宜決定される。第２の配線基板４の回路パターン４ａに形成された凹部４ａ−２には、例えば実施の形態１のように導電層を埋め込まなくてもよい。実施の形態２にかかる半導体装置２０の第１，２の導電板２１，２２の外部形状以外の構成は、実施の形態１にかかる半導体装置と同様である。   The second conductive plate 22 and the circuit pattern 4a of the second wiring board 4 are connected to the recess 4a-2 provided in the circuit pattern 4a of the second wiring board 4 via a bonding material (not shown). The same conductor 22-2 is joined and integrated with the recess 22-1 of the second conductive plate 22 provided at a position corresponding to the recess 4a-2. The length of the conductor 22-2 in the axial direction is appropriately determined according to the depth of the recess 4a-2, for example. In the recess 4a-2 formed in the circuit pattern 4a of the second wiring board 4, for example, a conductive layer may not be embedded as in the first embodiment. The configuration of the semiconductor device 20 according to the second embodiment other than the external shape of the first and second conductive plates 21 and 22 is the same as that of the semiconductor device according to the first embodiment.

つぎに、図３に示す半導体装置２０の製造方法について説明する。まず、図４に示すように、半導体装置２０を構成する第１，２の導電板２１，２２、および、第１，２の配線基板３，４を形成する。具体的には、第１の導電板２１に予め凹部２１−１を形成する。第２の導電板２２に予め凹部２２−１を形成する。第１の配線基板３の回路パターン３ａに予め凹部３ａ−１を形成する。第２の配線基板４の回路パターン４ａに予め凹部４ａ−２を形成する。   Next, a method for manufacturing the semiconductor device 20 shown in FIG. 3 will be described. First, as shown in FIG. 4, first and second conductive plates 21 and 22 and first and second wiring boards 3 and 4 constituting the semiconductor device 20 are formed. Specifically, the concave portion 21-1 is formed in the first conductive plate 21 in advance. A recess 22-1 is formed in advance on the second conductive plate 22. A recess 3 a-1 is formed in advance in the circuit pattern 3 a of the first wiring board 3. A recess 4 a-2 is formed in advance in the circuit pattern 4 a of the second wiring board 4.

より具体的には、第１の導電板２１の凹部２１−１は、例えば、第１の導電板２１の外形加工を行う前または後に、第１の導電板２１の、第１の配線基板３と接合される側の面を塑性加工によって変形させることで形成される。第２の導電板２２の凹部２２−１の形成方法は、第１の導電板２１の凹部２１−１と同様である。第１，２の配線基板３，４の形成方法は、実施の形態１における第１，２の配線基板と同様である。   More specifically, the concave portion 21-1 of the first conductive plate 21 is, for example, before or after the outer shape of the first conductive plate 21 is processed, the first wiring board 3 of the first conductive plate 21. It is formed by deforming the surface to be joined with plastic working. The method of forming the recess 22-1 of the second conductive plate 22 is the same as that of the recess 21-1 of the first conductive plate 21. The first and second wiring boards 3 and 4 are formed in the same manner as the first and second wiring boards in the first embodiment.

上述したように予め凹部２１−１，２２−１が形成された第１，２の導電板２１，２２、および、予め凹部３ａ−１，４ａ−２が形成された第１，２の配線基板３，４の回路パターン３ａ，４ａの表面に、各部材どうしを接合する接合材と反応しやすい金属膜（図示省略）を形成する。そして、各部材間に箔状の接合材を挿入し、実施の形態１と同様の順番で各部材を重ね合わせる。   As described above, the first and second conductive plates 21 and 22 in which the concave portions 21-1 and 22-1 are formed in advance, and the first and second wiring boards in which the concave portions 3a-1 and 4a-2 are formed in advance. On the surfaces of the circuit patterns 3a and 4a of 3 and 4, a metal film (not shown) that easily reacts with a bonding material for bonding the members to each other is formed. Then, a foil-like bonding material is inserted between the members, and the members are overlapped in the same order as in the first embodiment.

各部材を重ね合わせたとき、すなわち、半導体チップ１と第１の導電板２１とを接合するときに、第１の配線基板３の回路パターン３ａに設けられた凹部３ａ−１と、この凹部３ａ−１に対応する第１の導電板２１の凹部２１−１とに同一の導電体２１−２の各端部をそれぞれ挿入する。また、半導体チップ１と第２の導電板２２とを接合するときに、第２の配線基板４の回路パターン４ａに設けられた凹部４ａ−２と、この凹部４ａ−２に対応する第２の導電板２２の凹部２２−１とに同一の導電体２２−２の各端部をそれぞれ挿入する。   When the respective members are overlapped, that is, when the semiconductor chip 1 and the first conductive plate 21 are joined, the concave portion 3a-1 provided in the circuit pattern 3a of the first wiring board 3 and the concave portion 3a Each end of the same conductor 21-2 is inserted into the recess 21-1 of the first conductive plate 21 corresponding to -1. Further, when the semiconductor chip 1 and the second conductive plate 22 are joined, the concave portion 4a-2 provided in the circuit pattern 4a of the second wiring board 4 and the second corresponding to the concave portion 4a-2. Each end of the same conductor 22-2 is inserted into the recess 22-1 of the conductive plate 22, respectively.

第１の配線基板３と第１の導電板２１、第２の配線基板４と第２の導電板２２との接合方法以外の、半導体装置２０の製造方法は、実施の形態１にかかる半導体装置と同様である。実施の形態２にかかる半導体装置２０を構成する各部材や接合材の条件は、実施の形態１にかかる半導体装置と同様である。   The manufacturing method of the semiconductor device 20 other than the bonding method of the first wiring board 3 and the first conductive plate 21 and the second wiring board 4 and the second conductive plate 22 is the semiconductor device according to the first embodiment. It is the same. Conditions of each member and bonding material constituting the semiconductor device 20 according to the second embodiment are the same as those of the semiconductor device according to the first embodiment.

以上、説明したように、実施の形態２にかかる半導体装置２０によれば、実施の形態１にかかる半導体装置と同様の効果を得ることができる。また、実施の形態２にかかる半導体装置２０の製造方法によれば、第１，２の配線基板３，４の回路パターン３ａ，４ａに設けられた凹部３ａ−１，４ａ−２と、この凹部３ａ−１，４ａ−２に対応する位置に設けられた第１，２の導電板２１，２２の凹部２１−１，２２−１とに同一の導電体２１−２，２２−２を挿入することで、半導体装置２０の半導体チップ１の主面に水平な方向のアライメントを正確に決定することができる。このため、半導体チップ１、第１，２の導電板２１，２２および第１，２の配線基板３，４を正確な位置で接合し一体化することができる。   As described above, according to the semiconductor device 20 according to the second embodiment, the same effect as that of the semiconductor device according to the first embodiment can be obtained. Further, according to the manufacturing method of the semiconductor device 20 according to the second embodiment, the recesses 3a-1 and 4a-2 provided in the circuit patterns 3a and 4a of the first and second wiring boards 3 and 4 and the recesses are provided. The same conductors 21-2 and 22-2 are inserted into the recesses 21-1 and 22-1 of the first and second conductive plates 21 and 22 provided at positions corresponding to 3a-1 and 4a-2. Thus, the alignment in the direction horizontal to the main surface of the semiconductor chip 1 of the semiconductor device 20 can be accurately determined. Therefore, the semiconductor chip 1, the first and second conductive plates 21, 22 and the first and second wiring boards 3 and 4 can be joined and integrated at accurate positions.

（実施の形態３）
図５は、実施の形態３にかかる製造途中の半導体装置について示す断面図である。実施の形態３にかかる半導体装置の製造方法が実施の形態１にかかる半導体装置と異なるのは、第１，２の導電板２−１，２−２と第１，２の配線基板３，４の回路パターン３ａ，４ａとを接合する前に、予め、半導体チップ１と第１，２の導電板２−１，２−２とを接合したことである。 (Embodiment 3)
FIG. 5 is a cross-sectional view illustrating the semiconductor device according to the third embodiment which is being manufactured. The semiconductor device manufacturing method according to the third embodiment differs from the semiconductor device according to the first embodiment in that the first and second conductive plates 2-1 and 2-2 and the first and second wiring boards 3 and 4 are different. That is, the semiconductor chip 1 and the first and second conductive plates 2-1 and 2-2 are bonded in advance before the circuit patterns 3a and 4a are bonded.

図５を参照して、実施の形態３にかかる半導体装置の製造方法について説明する。まず、半導体チップ１と、予め突起部１１，１２が形成された第１，２の導電板２−１，２−２とを接合する。具体的には、第１の導電板２−１の、突起部１１が形成された面に対して反対側の面と半導体チップ１の裏面とが接する状態で、第１の導電板２−１上に半導体チップ１を重ねる。   With reference to FIG. 5, the manufacturing method of the semiconductor device concerning Embodiment 3 is demonstrated. First, the semiconductor chip 1 is bonded to the first and second conductive plates 2-1 and 2-2 on which the protrusions 11 and 12 are formed in advance. Specifically, the first conductive plate 2-1 is in a state where the surface of the first conductive plate 2-1 opposite to the surface on which the protrusions 11 are formed and the back surface of the semiconductor chip 1 are in contact. The semiconductor chip 1 is stacked on top.

さらに、第２の導電板２−２の、突起部１２が形成された面に対して反対側の面を下にして、半導体チップ１上に第２の導電板２−２を重ねる。半導体チップ１と第１，２の導電板２−１，２−２とは、実施の形態１と同様にそれぞれ箔状の接合材（図示省略）が挿入された状態で重ね合わされる。そして、重ね合わされた各部材を一括して加熱することで、第１の導電板２−１、半導体チップ１、および第２の導電板２−２がこの順で一体化されてなる部材（第１の中間組立部材とする）３１を形成する。   Further, the second conductive plate 2-2 is overlaid on the semiconductor chip 1 with the surface of the second conductive plate 2-2 opposite to the surface on which the protrusions 12 are formed. The semiconductor chip 1 and the first and second conductive plates 2-1 and 2-2 are overlapped with a foil-like bonding material (not shown) inserted in the same manner as in the first embodiment. Then, by heating the stacked members together, the first conductive plate 2-1, the semiconductor chip 1, and the second conductive plate 2-2 are integrated in this order (first member). 1 as an intermediate assembly member 1).

半導体チップ１と第１，２の導電板２−１，２−２との接合は、例えば、接合材として高融点を有する接合材を用い、加熱しながら加圧し原子の拡散によって各部材どうしを接合する拡散接合（熱圧着）により行うのが好ましい。高融点を有する接合材とは、例えば、拡散接合による熱処理において液状化しない融点を有する接合材である。このような接合材として、例えば、銀、銅、パラジウム、金などの微細粒子で構成される接合材を用いてもよい。   The bonding between the semiconductor chip 1 and the first and second conductive plates 2-1 and 2-2 uses, for example, a bonding material having a high melting point as a bonding material, pressurizes while heating, and bonds each member by diffusion of atoms. The diffusion bonding (thermocompression bonding) is preferably performed. The bonding material having a high melting point is, for example, a bonding material having a melting point that does not liquefy during heat treatment by diffusion bonding. As such a bonding material, for example, a bonding material composed of fine particles such as silver, copper, palladium, and gold may be used.

このようにして、複数の第１の中間組立部材３１を複数形成し、複数の第１の中間組立部材３１を、第１の配線基板３２の回路パターン３ａ上の所定の位置に載置する。実施の形態１と同様に、第１配線基板３２の回路パターン３ａに設けられた凹部３ａ−１に第１の導電板２−１の突起部１１を挿入した状態で、第１の配線基板３２上に第１の中間組立部材３１を載置する。そして、第１の配線基板３２の回路パターン３ａに複数の第１の中間組立部材３１を接合して一体化し、第２の中間組立部材３３を形成する（図５の点線で囲まれた部分）。第１の配線基板３２の回路パターン３ａと第１の中間組立部材３１との接合も拡散接合により行うのが好ましい。   In this way, a plurality of first intermediate assembly members 31 are formed, and the plurality of first intermediate assembly members 31 are placed at predetermined positions on the circuit pattern 3 a of the first wiring board 32. As in the first embodiment, the first wiring board 32 is inserted in the state in which the protrusions 11 of the first conductive plate 2-1 are inserted into the recesses 3a-1 provided in the circuit pattern 3a of the first wiring board 32. The first intermediate assembly member 31 is placed thereon. Then, a plurality of first intermediate assembly members 31 are joined and integrated with the circuit pattern 3a of the first wiring board 32 to form a second intermediate assembly member 33 (portion surrounded by a dotted line in FIG. 5). . The circuit pattern 3a of the first wiring board 32 and the first intermediate assembly member 31 are also preferably joined by diffusion bonding.

つぎに、第２の中間組立部材３３の各第２の導電板２−２上にそれぞれ第２の配線基板３４を重ねる。実施の形態１と同様に、各第２の導電板２−２の突起部１２が第２配線基板３４の回路パターン４ａに設けられた凹部４ａ−４に挿入されるように、第２の中間組立部材３３と第２の配線基板３４とを重ね合わせる。そして、第２の配線基板３４の回路パターン４ａに第２の導電板２−２を接合することで、第２の配線基板３４と第２の中間組立部材３３とを一体化する。   Next, the second wiring board 34 is overlaid on each second conductive plate 2-2 of the second intermediate assembly member 33. As in the first embodiment, the second intermediate plate is inserted so that the protrusion 12 of each second conductive plate 2-2 is inserted into the recess 4a-4 provided in the circuit pattern 4a of the second wiring board 34. The assembly member 33 and the second wiring board 34 are overlapped. Then, the second wiring board 34 and the second intermediate assembly member 33 are integrated by bonding the second conductive plate 2-2 to the circuit pattern 4a of the second wiring board 34.

その後、第１の配線基板３２を所定の位置（例えば図５にて二点差線で示す部分）３５で切断し、個別の半導体装置に切り分ける。これにより、例えば、実施の形態１に示すような半導体装置が完成する。図５では、切断後の第１の配線基板３２には第１の中間組立部材３１がそれぞれ２つずつ設けられているが、これに限らず、１つの半導体装置において第１の中間組立部材３１は１つ設けられてもよいし、３つ以上設けられてもよい。   Thereafter, the first wiring substrate 32 is cut at a predetermined position (for example, a portion indicated by a two-dot chain line in FIG. 5) 35 to be cut into individual semiconductor devices. Thereby, for example, the semiconductor device as shown in the first embodiment is completed. In FIG. 5, two first intermediate assembly members 31 are provided on each of the first wiring boards 32 after being cut, but the present invention is not limited to this, and the first intermediate assembly member 31 is not limited to this. One may be provided, or three or more may be provided.

実施の形態３にかかる半導体装置の各部材の接合方法は、実施の形態１における接合方法と同様である。また、実施の形態３にかかる半導体装置を構成する各部材や接合材の条件は、実施の形態１にかかる半導体装置と同様である。また、実施の形態３においては、実施の形態１にかかる半導体装置を複数作製しているが、実施の形態２にかかる半導体装置を複数作製してもよい。   The joining method of each member of the semiconductor device according to the third embodiment is the same as the joining method in the first embodiment. Further, the conditions of each member and bonding material constituting the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment. In the third embodiment, a plurality of semiconductor devices according to the first embodiment are manufactured. However, a plurality of semiconductor devices according to the second embodiment may be manufactured.

以上、説明したように、実施の形態３によれば、実施の形態１にかかる半導体装置と同様の効果を得ることができる。また、実施の形態３によれば、複数の半導体装置を一括して作製（製造）することができる。したがって、半導体装置を構成する各部材を組み立てて複数の半導体装置を作成する際に、工程数を低減することができる。   As described above, according to the third embodiment, the same effect as that of the semiconductor device according to the first embodiment can be obtained. Further, according to the third embodiment, a plurality of semiconductor devices can be manufactured (manufactured) together. Therefore, the number of processes can be reduced when a plurality of semiconductor devices are formed by assembling the members constituting the semiconductor device.

以上において本発明では、上述した実施の形態に限らず、半導体チップを実装したさまざまな構成の半導体装置に適用することが可能である。例えば、配線基板上に１つの半導体チップが実装されたモジュールに適用してもよいし、配線基板上に複数の半導体チップが実装されたモジュールに適用してもよい。本発明は、実装される半導体チップの個数によらず同様の効果を得ることができる。   As described above, the present invention is not limited to the above-described embodiment, and can be applied to semiconductor devices having various configurations on which a semiconductor chip is mounted. For example, the present invention may be applied to a module in which one semiconductor chip is mounted on a wiring board, or may be applied to a module in which a plurality of semiconductor chips are mounted on a wiring board. The present invention can obtain the same effect regardless of the number of mounted semiconductor chips.

また、上述した実施の形態では、導電板に設けた突起部または導電板の凹部に挿入する導電体の形状を円柱状として説明しているが、これに限らず、配線基板の回路パターンに設けられた凹部に挿入されることにより、導電板と配線基板との接合時の位置ずれを防止することができる形状を有していればよい。導電板に設けた突起部または導電板の凹部に挿入する導電体の形状によって、配線基板の回路パターンに設けられた凹部の平面形状も種々変更される。また、半導体チップ１のおもて面（または裏面）に複数の表面電極が設けられ、当該複数の表面電極の電位がそれぞれ異なる場合、各表面電極にそれぞれ第１の導電板（または第２の導電板）を接合してもよい。   In the above-described embodiment, the shape of the conductor inserted into the protrusion provided on the conductive plate or the concave portion of the conductive plate is described as a cylindrical shape. However, the present invention is not limited to this, and is provided in the circuit pattern of the wiring board. It is only necessary to have a shape that can be prevented from being displaced when the conductive plate and the wiring board are joined by being inserted into the recessed portion. The planar shape of the recesses provided in the circuit pattern of the wiring board is variously changed depending on the shape of the conductors inserted into the protrusions provided on the conductive plate or the recesses of the conductive plate. In addition, when a plurality of surface electrodes are provided on the front surface (or back surface) of the semiconductor chip 1 and the potentials of the plurality of surface electrodes are different from each other, the first conductive plate (or the second conductive plate) is connected to each surface electrode. A conductive plate) may be joined.

以上のように、本発明にかかる半導体装置および半導体装置の製造方法は、電力変換用途のスイッチングデバイスとして用いられるパワー半導体装置に有用である。   As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a power semiconductor device used as a switching device for power conversion.

１ 半導体チップ
２−１ 導電板（第１）
２−２ 導電板（第２）
３ 配線基板（第１）
３ａ，３ｂ 配線基板（第１）の回路パターン
４ 配線基板（第２）
４ａ，４ｂ 配線基板（第２）の回路パターン
４ａ−１ 配線基板（第２）のスルーホール部
４ａ−２，４ａ−４ 配線基板（第２）の回路パターンに設けられた凹部
４ａ−３ 導電層
１０ 半導体装置
１１ 導電板（第１）の突起部
１２ 導電板（第２）の突起部 1 Semiconductor chip 2-1 Conductive plate (first)
2-2 Conductive plate (second)
3 Wiring board (first)
3a, 3b Circuit pattern of the wiring board (first) 4 Wiring board (second)
4a, 4b Circuit pattern of the wiring board (second) 4a-1 Through-hole portion of the wiring board (second) 4a-2, 4a-4 Recessed part provided in the circuit pattern of the wiring board (second) 4a-3 Conductivity Layer 10 Semiconductor device 11 Protruding part of conductive plate (first) 12 Protruding part of conductive plate (second)

Claims (16)

半導体チップの主面に設けられた電極と、絶縁基板の主面に設けられた配線パターンとを電気的に接続する導電板を備え、
前記導電板の一方の面は、前記半導体チップの電極が設けられた主面に接合され、
前記導電板の他方の面は、前記絶縁基板の配線パターンに接合されていることを特徴とする半導体装置。 A conductive plate for electrically connecting the electrode provided on the main surface of the semiconductor chip and the wiring pattern provided on the main surface of the insulating substrate;
One surface of the conductive plate is bonded to the main surface provided with the electrodes of the semiconductor chip,
2. The semiconductor device according to claim 1, wherein the other surface of the conductive plate is bonded to a wiring pattern of the insulating substrate. 前記導電板の他方の面には、前記絶縁基板の主面に水平な方向における前記絶縁基板との接合位置を固定する突起部が設けられ、
前記絶縁基板の配線パターンには、前記導電板の前記突起部に対応する位置に前記突起部が挿入される凹部が設けられていることを特徴とする請求項１に記載の半導体装置。 The other surface of the conductive plate is provided with a protrusion that fixes the bonding position with the insulating substrate in a direction horizontal to the main surface of the insulating substrate,
The semiconductor device according to claim 1, wherein the wiring pattern of the insulating substrate is provided with a recess into which the protrusion is inserted at a position corresponding to the protrusion of the conductive plate. 前記絶縁基板の主面に水平な方向における前記絶縁基板と前記導電板との接合位置を固定する導電体をさらに備え、
前記導電板の他方の面には、前記導電体の一方の端部が挿入される凹部が設けられ、
前記絶縁基板の配線パターンには、前記導電板の前記凹部に対応する位置に前記導電体の他方の端部が挿入される凹部が設けられていることを特徴とする請求項１に記載の半導体装置。 A conductor that fixes a bonding position between the insulating substrate and the conductive plate in a direction horizontal to the main surface of the insulating substrate;
The other surface of the conductive plate is provided with a recess into which one end of the conductor is inserted,
2. The semiconductor according to claim 1, wherein the wiring pattern of the insulating substrate is provided with a recess into which the other end of the conductor is inserted at a position corresponding to the recess of the conductive plate. apparatus. 前記半導体チップの線膨張係数α１、前記導電板の線膨張係数α２、および前記絶縁基板の配線パターンの線膨張係数α３は、次の（１）式を満たすことを特徴とする請求項１〜３のいずれか一つに記載の半導体装置。
α１＜α２＜α３ ・・・（１） The linear expansion coefficient α1 of the semiconductor chip, the linear expansion coefficient α2 of the conductive plate, and the linear expansion coefficient α3 of the wiring pattern of the insulating substrate satisfy the following expression (1): The semiconductor device according to any one of the above.
α1 <α2 <α3 (1) 前記導電板は、モリブデン、タングステン、銅とモリブデンとからなる合金、鉄とニッケルとからなる合金、または、鉄とニッケルとコバルトとからなる合金、もしくはこれらの金属および合金を２種類以上組み合わせて形成される複合材料で構成されていることを特徴とする請求項１〜４のいずれか一つに記載の半導体装置。   The conductive plate is formed of molybdenum, tungsten, an alloy composed of copper and molybdenum, an alloy composed of iron and nickel, an alloy composed of iron, nickel and cobalt, or a combination of two or more of these metals and alloys. The semiconductor device according to claim 1, wherein the semiconductor device is made of a composite material. 前記絶縁基板の配線パターンは、銅、アルミニウム、銀またはニッケルで構成されていることを特徴とする請求項１〜５のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the wiring pattern of the insulating substrate is made of copper, aluminum, silver, or nickel. 前記絶縁基板の配線パターンには複数の前記導電板が接合され、複数の前記導電板にはそれぞれ前記半導体チップが接合され、複数の前記半導体チップの主面に設けられた電極どうしは電気的に接続されていることを特徴とする請求項１〜６のいずれか一つに記載の半導体装置。   A plurality of the conductive plates are bonded to the wiring pattern of the insulating substrate, the semiconductor chips are bonded to the plurality of conductive plates, respectively, and the electrodes provided on the main surfaces of the plurality of semiconductor chips are electrically connected to each other. The semiconductor device according to claim 1, wherein the semiconductor device is connected. 前記導電板は、前記半導体チップの第１の主面に接合され当該第１の主面に設けられた電極に接続する第１の導電板と、前記半導体チップの第２の主面に接合され当該第２の主面に設けられた電極に接続する第２の導電板と、を備え、
前記絶縁基板は、第１の導電板の、前記半導体チップに接合された面に対して反対側の面に接合される配線パターンが設けられた第１の絶縁基板と、第２の導電板の、前記半導体チップに接合された面に対して反対側の面に接合される配線パターンが設けられた第２の絶縁基板と、を備えることを特徴とする請求項１〜７のいずれか一つに記載の半導体装置。 The conductive plate is bonded to a first main surface of the semiconductor chip and connected to an electrode provided on the first main surface, and is bonded to a second main surface of the semiconductor chip. A second conductive plate connected to the electrode provided on the second main surface,
The insulating substrate includes: a first insulating substrate provided with a wiring pattern bonded to a surface of the first conductive plate opposite to a surface bonded to the semiconductor chip; and a second conductive plate And a second insulating substrate provided with a wiring pattern bonded to a surface opposite to the surface bonded to the semiconductor chip. A semiconductor device according to 1. 半導体チップの主面に、前記半導体チップの主面に設けられた電極と絶縁基板の主面に設けられた配線パターンとを電気的に接続する導電板の一方の面を接合する第１の接合工程と、
前記絶縁基板の配線パターンが設けられた主面に、前記導電板の他方の面を接合する第２の接合工程と、
を含み、
前記第１の接合工程を前記第２の接合工程とともに行うことを特徴とする半導体装置の製造方法。 A first joint that joins one surface of a conductive plate that electrically connects an electrode provided on the main surface of the semiconductor chip and a wiring pattern provided on the main surface of the insulating substrate to the main surface of the semiconductor chip. Process,
A second bonding step of bonding the other surface of the conductive plate to the main surface provided with the wiring pattern of the insulating substrate;
Including
A method of manufacturing a semiconductor device, wherein the first bonding step is performed together with the second bonding step. 半導体チップの主面に、前記半導体チップの主面に設けられた電極と絶縁基板の主面に設けられた配線パターンとを電気的に接続する導電板の一方の面を接合する第１の接合工程と、
前記絶縁基板の配線パターンが設けられた主面に、前記導電板の他方の面を接合する第２の接合工程と、
を含み、
前記第１の接合工程の後に、前記第２の接合工程を行うことを特徴とする半導体装置の製造方法。 A first joint that joins one surface of a conductive plate that electrically connects an electrode provided on the main surface of the semiconductor chip and a wiring pattern provided on the main surface of the insulating substrate to the main surface of the semiconductor chip. Process,
A second bonding step of bonding the other surface of the conductive plate to the main surface provided with the wiring pattern of the insulating substrate;
Including
A method of manufacturing a semiconductor device, wherein the second bonding step is performed after the first bonding step. 前記第２の接合工程では、前記絶縁基板の配線パターンに設けられた凹部に、前記導電板の他方の面に設けられた突起部を挿入し、前記絶縁基板の主面に水平な方向における前記絶縁基板と前記導電板との接合位置を固定することを特徴とする請求項９または１０に記載の半導体装置の製造方法。   In the second bonding step, a protrusion provided on the other surface of the conductive plate is inserted into a recess provided in the wiring pattern of the insulating substrate, and the horizontal surface of the insulating substrate in the horizontal direction is inserted. 11. The method of manufacturing a semiconductor device according to claim 9, wherein a bonding position between the insulating substrate and the conductive plate is fixed. 前記第２の接合工程では、前記導電板の他方の面に設けられた凹部に導電体の一方の端部を挿入し、前記絶縁基板の配線パターンの、前記導電板の凹部に対応する位置に設けられた凹部に前記導電体の他方の端部を挿入し、前記絶縁基板の主面に水平な方向における前記絶縁基板と前記導電板との接合位置を固定することを特徴とする請求項９または１０に記載の半導体装置の製造方法。   In the second bonding step, one end of the conductor is inserted into a recess provided on the other surface of the conductive plate, and the wiring pattern of the insulating substrate is positioned at a position corresponding to the recess of the conductive plate. 10. The other end portion of the conductor is inserted into a provided recess, and a bonding position between the insulating substrate and the conductive plate in a direction horizontal to the main surface of the insulating substrate is fixed. Or a method of manufacturing a semiconductor device according to 10; 前記半導体チップの線膨張係数α１、前記導電板の線膨張係数α２、および前記絶縁基板の配線パターンの線膨張係数α３は、次の（２）式を満たすことを特徴とする請求項９〜１２のいずれか一つに記載の半導体装置の製造方法。
α１＜α２＜α３ ・・・（２） The linear expansion coefficient α1 of the semiconductor chip, the linear expansion coefficient α2 of the conductive plate, and the linear expansion coefficient α3 of the wiring pattern of the insulating substrate satisfy the following expression (2). A method for manufacturing a semiconductor device according to any one of the above.
α1 <α2 <α3 (2) 前記導電板は、モリブデン、タングステン、銅とモリブデンとからなる合金、鉄とニッケルとからなる合金、または、鉄とニッケルとコバルトとからなる合金、もしくはこれらの金属および合金を２種類以上組み合わせて形成される複合材料で構成されていることを特徴とする請求項９〜１３のいずれか一つに記載の半導体装置の製造方法。   The conductive plate is formed of molybdenum, tungsten, an alloy composed of copper and molybdenum, an alloy composed of iron and nickel, an alloy composed of iron, nickel and cobalt, or a combination of two or more of these metals and alloys. The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor device is made of a composite material. 前記絶縁基板の配線パターンは、銅、アルミニウム、銀またはニッケルで構成されていることを特徴とする請求項９〜１４のいずれか一つに記載の半導体装置の製造方法。   15. The method for manufacturing a semiconductor device according to claim 9, wherein the wiring pattern of the insulating substrate is made of copper, aluminum, silver, or nickel. 前記絶縁基板の配線パターンに、複数の前記導電板を接合し、
前記絶縁基板の配線パターンに接合された複数の前記導電板のそれぞれに前記半導体チップを接合することを特徴とする請求項９〜１５のいずれか一つに記載の半導体装置の製造方法。 Bonding a plurality of the conductive plates to the wiring pattern of the insulating substrate,
The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor chip is bonded to each of the plurality of conductive plates bonded to the wiring pattern of the insulating substrate.
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