CN114050144A - Semiconductor package device and method of manufacturing the same - Google Patents

Semiconductor package device and method of manufacturing the same Download PDF

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Publication number
CN114050144A
CN114050144A CN202111232807.4A CN202111232807A CN114050144A CN 114050144 A CN114050144 A CN 114050144A CN 202111232807 A CN202111232807 A CN 202111232807A CN 114050144 A CN114050144 A CN 114050144A
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Prior art keywords
redistribution layer
semiconductor package
substrate
package device
accommodating space
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CN202111232807.4A
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Chinese (zh)
Inventor
呂文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202111232807.4A priority Critical patent/CN114050144A/en
Publication of CN114050144A publication Critical patent/CN114050144A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a substrate having an accommodating space; the rewiring layer is arranged on the substrate and covers the accommodating space; a first electronic element and a second electronic element which are provided on the rewiring layer and electrically connected to the rewiring layer; the bridging element is arranged in the accommodating space, and the rewiring layer is electrically connected with the bridging element so as to realize the electrical connection between the first electronic element and the second electronic element. The semiconductor packaging device can resist the stress caused by different thermal expansion coefficients of all materials by the larger strength of the bridging element, and the thickness of the packaging device is not required to be increased, so that the yield of products is improved on the premise of keeping the size of the packaging device unchanged.

Description

Semiconductor package device and method of manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.
Background
The FOCoS (Fan Out Chip on Substrate) packaging technology is implemented by using Fan-Out composite chips on a typical ball grid array Substrate. It can provide a lower cost solution with practically better electrical and thermal performance than silicon interposer structures.
In the FOCoS package device, the Coefficient of Thermal Expansion (CTE) may not be uniform between the materials (mismatch). In the thermal cycle process, different expansion amounts are generated due to different thermal expansion coefficients of the materials, and further stress is generated in the structure. The stress tends to crack (crack) the internal structure of the FOCoS package, especially the Redistribution Layer (RDL). If a Reinforcement Structure (Reinforcement Structure) is added to the redistribution layer, the thickness of the entire package increases. If the Bridge Die is provided below the redistribution layer, the thickness of the package device is increased, and the manufacturing yield of the entire package device is reduced due to the manufacturing yield of the Bridge Die.
Therefore, a new technical solution is needed to solve at least one of the above technical problems.
Disclosure of Invention
The present disclosure provides a semiconductor package device and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package device, comprising:
a substrate having an accommodating space;
the rewiring layer is arranged on the substrate and covers the accommodating space;
a first electronic element and a second electronic element which are provided on the rewiring layer and electrically connected to the rewiring layer;
and a bridging element is arranged in the accommodating space, and the redistribution layer is electrically connected with the bridging element so as to realize the electrical connection between the first electronic element and the second electronic element.
In some optional embodiments, the redistribution layer includes a dielectric material, and the dielectric material extends into the accommodating space and partially covers the bridging element.
In some optional embodiments, the first side wall of the accommodating space is located in a vertical projection area of the first electronic element, and the second side wall of the accommodating space is located in a vertical projection area of the second electronic element.
In some alternative embodiments, a first edge of the bridging element is located within a vertical projection area of the first electronic element and a second edge of the bridging element is located within a vertical projection area of the second electronic element.
In some optional embodiments, the bridge element includes a silicon material and a bridge line disposed on the silicon material.
In some optional embodiments, a capillary underfill material is disposed between the first electronic component and the redistribution layer, between the second electronic component and the redistribution layer, and/or a molding material is disposed over the redistribution layer; or
And molding underfill materials are arranged between the first electronic element and the redistribution layer, between the second electronic element and the redistribution layer and above the redistribution layer.
In some optional embodiments, the first electronic element and the redistribution layer are electrically connected by a conductive pad and/or a conductive pillar.
In some alternative embodiments, the first electronic element and the redistribution layer are electrically connected by a direct metal bonding or by a solder bonding.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:
providing a substrate, wherein the substrate is provided with an accommodating space;
grabbing and placing the bridging element in the accommodating space;
forming a rewiring layer on the substrate;
electrically connecting a first electronic element and a second electronic element to the rewiring layer, and electrically connecting the rewiring layer and the bridge element.
In some optional embodiments, the forming a redistribution layer on the substrate includes:
forming a dielectric material on the substrate in a pressing manner, wherein the dielectric material extends into the accommodating space and partially covers the bridging element;
the rewiring layer is formed based on a dielectric material.
In some optional embodiments, the providing a substrate comprises:
forming a through groove on the substrate;
and a dielectric film is arranged on one side of the through groove to form the accommodating space.
In some optional embodiments, after the electrically connecting the first and second electronic elements to the redistribution layer and the electrically connecting the redistribution layer and the bridge element, the method further comprises:
disposing a capillary underfill material between the first electronic component and the redistribution layer, between the second electronic component and the redistribution layer, and/or disposing a molding material over the redistribution layer; or
A mold underfill material is disposed between the first electronic component and the redistribution layer, between the second electronic component and the redistribution layer, and over the redistribution layer.
In the semiconductor package device and the manufacturing method thereof provided by the present disclosure, the accommodating space is provided on the substrate, and the bridging element is disposed in the accommodating space, so that on one hand, stress caused by inconsistent thermal expansion coefficients of materials can be resisted by the higher strength of the bridging element, and on the other hand, the thickness of the package device does not need to be increased, which is beneficial to improving the yield of products on the premise of keeping the size of the package device unchanged.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a prior art semiconductor package device;
fig. 2-8 are first through seventh schematic views of a semiconductor package device according to an embodiment of the present disclosure;
fig. 9-16 are schematic diagrams of methods of manufacturing semiconductor package devices according to embodiments of the present disclosure.
Description of the symbols:
11. a lower substrate; 12. a fan-out layer; 13. a left side chip; 14. a right chip; 15. connecting a line; 100. a substrate; 110. an accommodating space; 200. a rewiring layer; 210. a first electrical connection; 220. a dielectric material; 300. a first electronic component; 310. a second electrical connection; 320. welding flux; 400. a second electronic component; 410. a third electrical connection; 500. a bridging element; 510. a silicon material; 520. bridging a line; 610. a capillary underfill material; 620. molding an underfill material; 700. molding the material; 800. a direct engagement portion; 810. a first element; 820. a second element; 830. a third element; 840. a fourth element; 910. a through groove; 920. a dielectric film; 930. a bonding device; 940. a laminating device; 950. and an electrical connection structure.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.
It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.
It should be readily understood that the meaning of "in.. on," "over,", and "above" in this disclosure should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.
Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used in this disclosure to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly as such.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a schematic diagram of a semiconductor package device in the prior art. As shown in fig. 1, the semiconductor package device includes a lower substrate 11, a fan-out layer 12, a left chip 13, and a right chip 14. The fan-out layer 12 is disposed on the lower substrate 11. The left side chip 13 and the right side chip 14 are both disposed on the fan-out layer 12. The bridge circuit 520 is contained in the fan-out layer 12. The Gap (Gap) between the left chip 13 and the right chip 14 is located at the same vertical position as the connection line 15. In the semiconductor package device, there is a difference in thermal expansion coefficient of materials of respective portions, and stress is generated when heat is applied, causing the connection wiring 15 to break, as shown by the dotted line in fig. 1.
The disclosed embodiments provide a semiconductor package device. Fig. 2-8 are first through seventh schematic views of semiconductor packaging devices according to embodiments of the present disclosure.
Fig. 2 shows a longitudinal section of the semiconductor package device. As shown in fig. 2, the semiconductor package device includes a substrate 100, a redistribution layer 200, a first electronic component 300, and a second electronic component 400. The substrate 100 has a receiving space 110. The receiving space 110 may be a counterbore, a groove, or a cavity. The redistribution layer 200 is disposed on the substrate 100 and covers the accommodating space 110. The first electronic component 300 and the second electronic component 400 are disposed on the rewiring layer 200 and electrically connected to the rewiring layer 200. The bridging element 500 is disposed in the accommodating space 110. The redistribution layer 200 is electrically connected to the bridge member 500 to achieve electrical connection between the first electronic component 300 and the second electronic component 400.
As shown in fig. 2, a first electrical connector 210 is disposed on the redistribution layer 200, and a second electrical connector 310 and a third electrical connector 410 are disposed on the first electronic element 300 and the second electronic element 400, respectively. The second electrical connector 310 and the third electrical connector 410 are electrically connected to the first electrical connector 210, respectively, to achieve electrical connection of the first electronic element 300 and the second electronic element 400 to the redistribution layer 200. The first electrical connector 210 may be a conductive pad, and the second electrical connector 310 and the third electrical connector 410 may be conductive posts. The material of the lines in the rewiring layer 200 is, for example, copper (Cu), silver (Ag), gold (Au), aluminum (Al), nickel (Ni), titanium (Ti), lead (Pb), or the like.
As shown in fig. 2, capillary underfill 610 is disposed between the first electronic component 300 and the redistribution layer 200 and between the second electronic component 400 and the redistribution layer 200 to fill the gap at the relevant portion and improve the structural strength.
As shown in fig. 2, the redistribution layer 200 includes a dielectric material 220, and the dielectric material 220 extends into the accommodating space 110 and partially covers the bridging element 500, so as to fix and protect the bridging element 500.
As shown in fig. 2, a first sidewall (i.e., a left sidewall in fig. 2) of the accommodating space 110 is located in a vertical projection area of the first electronic component 300, and a second sidewall (i.e., a right sidewall in fig. 2) of the accommodating space 110 is located in a vertical projection area of the second electronic component 400. That is, the accommodating space 110 spans the first electronic component 300 and the second electronic component 400.
As shown in fig. 2, a first edge (i.e., the left edge in fig. 2) of the bridging element 500 is located within the vertical projection area of the first electronic component 300, and a second edge (i.e., the right edge in fig. 2) of the bridging element 500 is located within the vertical projection area of the second electronic component 400. That is, the bridge member 500 spans the first electronic component 300 and the second electronic component 400.
In one example, the thickness of the bridging element 500 is greater than or equal to 20 microns and less than or equal to 100 microns, and the thickness of the substrate 100 is greater than or equal to 50 microns and less than or equal to 200 microns. The width of the longitudinal cross section of the bridging element 500 is greater than 0.1 mm. The size ratio (including the thickness ratio and/or the width ratio) of the bridge member 500 with respect to the accommodating space 110 is greater than or equal to 0.5 and less than or equal to 0.8. The bridge line 520 has a line width and a line pitch of less than 2 μm. The thickness of the metallic titanium (Ti) in the bridge wire 520 is greater than or equal to 0.1 micrometers and less than or equal to 0.3 micrometers. The thickness of metallic copper (Cu) in the bridge wire 520 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers. The thickness of the dielectric material over the bridge wire 520 is greater than or equal to 1 micron and less than or equal to 10 microns. The distance between the first electronic component 300 and the second electronic component 400 is greater than 70 microns.
Fig. 3 is an enlarged view of the bridging element 500 in the semiconductor package device. As shown in fig. 3, the bridge component 500 may be a bridge chip, and includes a silicon material 510 and a bridge circuit 520. The bridge element 500 may be formed by fabricating a bridge circuit 520 on a silicon material 510.
Fig. 4 is a variation of the semiconductor package of fig. 2. As shown in fig. 4, a molding material 700 is further disposed above the redistribution layer 200 to protect the first electronic element 300 and the second electronic element 400.
Fig. 5 is a variation of the semiconductor package of fig. 2. In fig. 2, a Capillary Underfill (CUF) 610 is provided between the first electronic component 300 and the redistribution layer 200 and between the second electronic component 400 and the redistribution layer 200. In fig. 5, a Molding Underfill (MUF) 620 is disposed between the first electronic component 300 and the redistribution layer 200 and between the second electronic component 400 and the redistribution layer 200. In addition, a mold underfill 620 is also provided over the redistribution layer 200 in fig. 5. For the semiconductor package device in fig. 5, the molding underfill 620 may be formed between the first electronic component 300 and the redistribution layer 200, between the second electronic component 400 and the redistribution layer 200, and above the redistribution layer 200 at one time, which is beneficial to reducing the process steps and improving the production efficiency.
Fig. 6 is a variation of the semiconductor package of fig. 2. In fig. 2, the second electrical connection 310 is a conductive pillar. In fig. 6, the second electrical connection 310 is a conductive pad. The conductive posts may be made of copper (Cu), silver (Ag), gold (Au), aluminum (Al), protactinium (Pa), platinum (Pt), or alloys thereof.
Fig. 7 shows different bonding manners of the electronic components (including the first electronic component 300 and the second electronic component 400) to the rewiring layer 200. As shown in fig. 7, the first electronic component 300 and the redistribution layer 200 are connected by soldering with solder 320 interposed therebetween, and the second electronic component 400 and the redistribution layer 200 are connected by Direct Bonding with a Direct Bonding portion 800 formed therebetween. The metal to be directly bonded may be copper (Cu), silver (Ag), gold (Au), or the like.
Fig. 8 is a variation of the semiconductor package of fig. 2. As shown in fig. 8, four electronic components including a first component 810, a second component 820, a third component 830, and a fourth component 840 are disposed on the redistribution layer 200. For two adjacent electronic components, a corresponding bridging element 500 is provided within the redistribution layer 200 to enable electrical connection of the two adjacent electronic components. By providing a plurality of electronic components, more abundant functions can be realized.
In the present embodiment, the dielectric materials in the bridge circuit 520, the redistribution layer 200 and the substrate 100 may be formed by using an organic photosensitive material, a non-photosensitive liquid or a dry film material, and the adhesion may be achieved by deposition, lamination, printing, potting or dipping.
In the semiconductor package device according to the embodiment of the disclosure, the accommodating space 110 is disposed on the substrate 100, and the bridging element 500 is disposed in the accommodating space 110, so that on one hand, the stress of the materials due to the inconsistent thermal expansion coefficients can be resisted by the high strength of the bridging element 500, and on the other hand, the thickness of the package device does not need to be increased, which is beneficial to improving the yield of the product on the premise of keeping the size of the package device unchanged.
The embodiment of the disclosure also provides a manufacturing method of the semiconductor packaging device. Fig. 9-16 are schematic diagrams of methods of manufacturing semiconductor package devices according to embodiments of the present disclosure.
Fig. 9 and 10 show a manufacturing process of the substrate 100. First, as shown in fig. 9, through-grooves 910 are formed on the substrate 100. Next, as shown in fig. 10, a dielectric film 920 is disposed on one side of the through-groove 910 to form the substrate 100 having the accommodating space 110.
Fig. 11 and 12 show the setting process of the bridging element 500. First, as shown in fig. 11, an electrical connection structure 950 is formed on the surface of dielectric film 920 to make external connection. Next, as shown in fig. 12, the substrate 100 is turned over, and the bridge component 500 is captured and placed (Pick and Place) in the accommodating space 110 by the bonding device 930.
Fig. 13-15 show a process of forming the rewiring layer 200. First, as shown in fig. 13 and 14, the dielectric material 220 is formed on the substrate 100 by a laminating device 940 in a pressing manner, so that the dielectric material 220 extends into the accommodating space 110 and partially covers the bridging element 500. Next, as shown in fig. 15, a redistribution layer 200 is formed on the basis of a dielectric material 220.
Fig. 16 shows a setting process of the electronic component. As shown in fig. 16, the first electronic element 300 and the second electronic element 400 are electrically placed on the rewiring layer 200, and the first electronic element 300 and the rewiring layer 200, the second electronic element 400 and the rewiring layer 200, and the bridge element 500 and the rewiring layer 200 are electrically connected by Flip Chip.
Further, a capillary underfill 610 may be provided between the first electronic element 300 and the redistribution layer 200, between the second electronic element 400 and the redistribution layer 200, and a molding material 700 may be provided above the redistribution layer 200 to obtain the semiconductor package device as shown in fig. 4. Alternatively, a mold underfill 620 may be provided between the first electronic element 300 and the redistribution layer 200, between the second electronic element 400 and the redistribution layer 200, and above the redistribution layer 200 to obtain the semiconductor package device shown in fig. 5.
The method for manufacturing a semiconductor package device according to the embodiments of the present disclosure can achieve similar technical effects to those of the semiconductor package device described above, and will not be described herein again.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed in this disclosure have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated in the present disclosure, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package device, comprising:
a substrate having an accommodating space;
the rewiring layer is arranged on the substrate and covers the accommodating space;
a first electronic element and a second electronic element which are provided on the rewiring layer and electrically connected to the rewiring layer;
and a bridging element is arranged in the accommodating space, and the redistribution layer is electrically connected with the bridging element so as to realize the electrical connection between the first electronic element and the second electronic element.
2. The semiconductor package device of claim 1, wherein the redistribution layer comprises a dielectric material that extends into the receiving space and partially encapsulates the bridging element.
3. The semiconductor package device of claim 1, wherein a first sidewall of the receiving space is located within a vertical projection area of the first electronic component and a second sidewall of the receiving space is located within a vertical projection area of the second electronic component.
4. The semiconductor package device of claim 1, wherein the bridge element comprises a silicon material and a bridge wire disposed on the silicon material.
5. The semiconductor package device of claim 1, wherein a capillary underfill material is disposed between the first electronic component and the redistribution layer, between the second electronic component and the redistribution layer, and/or a molding material is disposed over the redistribution layer; or
And molding underfill materials are arranged between the first electronic element and the redistribution layer, between the second electronic element and the redistribution layer and above the redistribution layer.
6. The semiconductor package device according to claim 1, wherein the first electronic element and the redistribution layer are electrically connected by a conductive pad and/or a conductive pillar.
7. The semiconductor package device according to claim 1, wherein the first electronic element and the redistribution layer are electrically connected by a direct metal bonding method or by a solder bonding method.
8. A method of manufacturing a semiconductor package device, comprising:
providing a substrate, wherein the substrate is provided with an accommodating space;
grabbing and placing the bridging element in the accommodating space;
forming a rewiring layer on the substrate;
electrically connecting a first electronic element and a second electronic element to the rewiring layer, and electrically connecting the rewiring layer and the bridge element.
9. The method of claim 8, wherein the forming a redistribution layer on the substrate comprises:
forming a dielectric material on the substrate in a pressing manner, wherein the dielectric material extends into the accommodating space and partially covers the bridging element;
the rewiring layer is formed based on a dielectric material.
10. The method of claim 8, wherein the providing a substrate comprises:
forming a through groove on the substrate;
and a dielectric film is arranged on one side of the through groove to form the accommodating space.
CN202111232807.4A 2021-10-22 2021-10-22 Semiconductor package device and method of manufacturing the same Pending CN114050144A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115360170A (en) * 2022-10-19 2022-11-18 睿力集成电路有限公司 Semiconductor structure and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115360170A (en) * 2022-10-19 2022-11-18 睿力集成电路有限公司 Semiconductor structure and forming method thereof
CN115360170B (en) * 2022-10-19 2023-01-31 睿力集成电路有限公司 Semiconductor structure and forming method thereof

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