JP2015090965A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2015090965A
JP2015090965A JP2013231312A JP2013231312A JP2015090965A JP 2015090965 A JP2015090965 A JP 2015090965A JP 2013231312 A JP2013231312 A JP 2013231312A JP 2013231312 A JP2013231312 A JP 2013231312A JP 2015090965 A JP2015090965 A JP 2015090965A
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solder
wiring board
recess
semiconductor device
hole
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Inventor
幸紘 森下
Yukihiro Morishita
幸紘 森下
宏貴 園田
Hirotaka Sonoda
宏貴 園田
広志 岩永
Hiroshi Iwanaga
広志 岩永
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2013231312A priority Critical patent/JP2015090965A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Cooling Or The Like Of Electrical Apparatus (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve a soldering strength without a significant increase in solder amount.SOLUTION: A semiconductor device comprises: a wiring board arranged on a heat sink; a semiconductor chip mounted on the wiring board; a hollow case bonded to the heat sink so as to surround the wiring board and the semiconductor chip; an electrode terminal having a fixing part fixed to the case and a flat surface part 8b bonded to the wiring board by a solder 9 in the case; a recess 11 provided on a top face of the flat surface part 8b; and a through hole 12 provided from a lower surface of the flat surface part 8b to reach a bottom face of the recess 11. The lower surface of the flat surface part 8 and the wiring board are bonded by the solder 9. The solder extends in the through hole 12 and on the bottom face of the recess 11.

Description

本発明は、大幅なはんだ量の増加なくはんだ付け強度を向上させることができる半導体装置に関する。   The present invention relates to a semiconductor device that can improve soldering strength without a significant increase in the amount of solder.

電力用の半導体装置（パワーモジュール）において、中空のケースが配線基板及び半導体チップを取り囲むように放熱板に接合され、ケースに固定された電極端子の平面部が配線基板にはんだにより接合されている。   In a power semiconductor device (power module), a hollow case is joined to a heat sink so as to surround the wiring board and the semiconductor chip, and a flat portion of the electrode terminal fixed to the case is joined to the wiring board by solder. .

しかし、半導体装置の動作中に温度が上昇し、配線基板と電極端子のはんだ接合面に線膨張係数の違いに起因して熱応力が発生する。これにより、電極端子が配線基板から剥離して故障が発生するという問題があった。これに対して、電極端子の平面部に貫通孔を設けることが提案されている（例えば、特許文献１参照）。貫通孔を通って平面部の上面に存在するはんだがリベットになるため、はんだバルクによるアンカー効果が得られ、はんだ付け強度を向上させることができる。   However, the temperature rises during the operation of the semiconductor device, and thermal stress is generated on the solder joint surface between the wiring board and the electrode terminal due to the difference in coefficient of linear expansion. As a result, there has been a problem that the electrode terminal is peeled off from the wiring board and a failure occurs. On the other hand, providing a through-hole in the flat part of an electrode terminal is proposed (for example, refer to patent documents 1). Since the solder existing on the upper surface of the flat portion through the through hole becomes a rivet, an anchor effect by the solder bulk can be obtained and the soldering strength can be improved.

特開昭６２−２０２５４８号公報JP-A-62-2202548

しかし、単純な貫通孔のみではリベットを構成するために、はんだ量を大幅に増加する必要がある。   However, in order to form a rivet with only a simple through hole, it is necessary to greatly increase the amount of solder.

本発明は、上述のような課題を解決するためになされたもので、その目的は大幅なはんだ量の増加なくはんだ付け強度を向上させることができる半導体装置を得るものである。   The present invention has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device capable of improving the soldering strength without a significant increase in the amount of solder.

本発明に係る半導体装置は、放熱板と、前記放熱板上に配置された配線基板と、前記配線基板上に実装された半導体チップと、前記配線基板及び前記半導体チップを取り囲むように前記放熱板に接合された中空のケースと、前記ケースに固定される固定部と、前記ケース内において前記配線基板にはんだにより接合された平面部とを有する電極端子とを備え、前記平面部の上面に凹部が設けられ、前記平面部の下面から前記凹部の底面に達する貫通孔が設けられ、前記平面部の前記下面と前記配線基板が前記はんだにより接合され、前記はんだは前記貫通孔内と前記凹部の前記底面上にも延在することを特徴とする。   The semiconductor device according to the present invention includes a heat sink, a wiring board disposed on the heat sink, a semiconductor chip mounted on the wiring board, and the heat sink so as to surround the wiring board and the semiconductor chip. A hollow case joined to the case, a fixed part fixed to the case, and an electrode terminal having a planar part joined to the wiring board by solder in the case, and a recess formed on the upper surface of the planar part A through hole reaching the bottom surface of the concave portion from the lower surface of the flat portion is provided, the lower surface of the flat portion and the wiring board are joined by the solder, and the solder is formed in the through hole and the concave portion. It also extends on the bottom surface.

本発明では貫通孔内と凹部の底面上に存在するはんだがリベットになるため、はんだバルクによるアンカー効果が得られ、はんだ付け強度を向上させ、信頼性において優れた半導体装置を得ることができる。また、単純な貫通孔のみではリベットを構成するために、はんだ量を大幅に増加する必要がある。そこで、平面部の上面に凹部を設け、平面部の下面から凹部の底面に達する貫通孔を設ける。これにより、大幅なはんだ量の増加なくはんだ付け強度を向上させることができる。   In the present invention, since the solder present in the through hole and on the bottom surface of the recess becomes a rivet, an anchor effect by the solder bulk can be obtained, the soldering strength can be improved, and a semiconductor device excellent in reliability can be obtained. Moreover, in order to constitute a rivet with only a simple through hole, it is necessary to greatly increase the amount of solder. Therefore, a concave portion is provided on the upper surface of the flat portion, and a through hole reaching from the lower surface of the flat portion to the bottom surface of the concave portion is provided. Thereby, the soldering strength can be improved without significantly increasing the amount of solder.

本発明の実施の形態１に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る電極端子と配線基板との接合部を示す斜視図である。It is a perspective view which shows the junction part of the electrode terminal and wiring board which concern on Embodiment 1 of this invention. 図２のＩ−ＩＩに沿った断面図である。It is sectional drawing along I-II of FIG. 本発明の実施の形態２に係る電極端子の平面部を示す断面図である。It is sectional drawing which shows the plane part of the electrode terminal which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る電極端子と配線基板との接合部を示す斜視図である。It is a perspective view which shows the junction part of the electrode terminal and wiring board which concern on Embodiment 3 of this invention. 本発明の実施の形態４に係る電極端子の平面部を示す断面図である。It is sectional drawing which shows the plane part of the electrode terminal which concerns on Embodiment 4 of this invention. 本発明の実施の形態５に係る電極端子と配線基板との接合部を示す斜視図である。It is a perspective view which shows the junction part of the electrode terminal and wiring board which concern on Embodiment 5 of this invention. 図７のＩ−ＩＩに沿った断面図である。It is sectional drawing along I-II of FIG. 図７のＩ−ＩＩに沿った断面図である。It is sectional drawing along I-II of FIG. 本発明の実施の形態６に係る電極端子の平面部を示す断面図である。It is sectional drawing which shows the plane part of the electrode terminal which concerns on Embodiment 6 of this invention.

本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す断面図である。放熱板１上に配線基板２が配置されている。両者ははんだ３により接合されている。配線基板２は絶縁基板上に回路が形成されたものである。絶縁基板は、放熱性に優れるＡｌＮ（窒化アルミニウム）等である。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. A wiring board 2 is disposed on the heat sink 1. Both are joined by solder 3. The wiring board 2 is a circuit board formed on an insulating substrate. The insulating substrate is AlN (aluminum nitride) or the like having excellent heat dissipation.

配線基板２上にＩＧＢＴ（Insulated-Gate Bipolar Transistor）等の半導体チップ４がはんだ５により実装されている。半導体チップ４はワイヤ６により配線基板２に接続されている。中空のケース７が配線基板２及び半導体チップ４を取り囲むように放熱板１に接合されている。ケース７はエンプラ（ＰＰＳ）等である。   A semiconductor chip 4 such as an IGBT (Insulated-Gate Bipolar Transistor) is mounted on the wiring board 2 by solder 5. The semiconductor chip 4 is connected to the wiring board 2 by wires 6. A hollow case 7 is joined to the heat sink 1 so as to surround the wiring substrate 2 and the semiconductor chip 4. Case 7 is engineering plastic (PPS) or the like.

電極端子８は、ケース７に固定される固定部８ａと、ケース７内において配線基板２にはんだ９により接合された平面部８ｂとを有し、直線状の固定部８ａに対して平面部８ｂが横に折れ曲がったＬ字型となっている。電極端子８は、はんだ付け性を向上させるためＮｉめっきを施したＣｕ等である。ケース７の内部にはシリコーンゲル１０が充填されている。   The electrode terminal 8 has a fixing portion 8a fixed to the case 7, and a flat portion 8b joined to the wiring board 2 by the solder 9 in the case 7, and the flat portion 8b with respect to the linear fixing portion 8a. Is L-shaped bent sideways. The electrode terminal 8 is made of Cu or the like plated with Ni in order to improve solderability. The inside of the case 7 is filled with a silicone gel 10.

図２は、本発明の実施の形態１に係る電極端子と配線基板との接合部を示す斜視図である。図３は、図２のＩ−ＩＩに沿った断面図である。平面部８ｂの上面に凹部１１が設けられている。平面部８ｂの下面から凹部１１の底面に達する貫通孔１２が設けられている。平面部８ｂの下面と配線基板２がはんだ９により接合されている。はんだ９は貫通孔１２内と凹部１１の底面上にも延在する。凹部１１の側面及び底面の一部にはんだ９が接合されているが、側面及び底面の全面にはんだ９が接合されていてもよい。   FIG. 2 is a perspective view showing a joint portion between the electrode terminal and the wiring board according to Embodiment 1 of the present invention. FIG. 3 is a cross-sectional view taken along the line I-II in FIG. A concave portion 11 is provided on the upper surface of the flat portion 8b. A through hole 12 that reaches the bottom surface of the recess 11 from the lower surface of the flat surface portion 8b is provided. The lower surface of the flat portion 8 b and the wiring board 2 are joined by solder 9. The solder 9 also extends in the through hole 12 and on the bottom surface of the recess 11. The solder 9 is joined to a part of the side surface and the bottom surface of the recess 11, but the solder 9 may be joined to the entire surface of the side surface and the bottom surface.

続いて、本実施の形態の効果を説明する。半導体装置の動作中に発生した熱で、ケース７、放熱板１、配線基板２が変形する。この変形により、ケース７に固定された電極端子８と配線基板２との接合部に応力が発生する。電極端子８を覆うシリコーンゲル１０はモールド樹脂のように電極を固定するほどの強度がない。このため、電極端子８と配線基板２との接合部に大きな負荷が加わる。しかし、貫通孔１２と凹部１１が無い従来構造では、はんだ付け強度は平面部８ｂの下面と配線基板２の接合界面での強度だけで決まってしまう。   Then, the effect of this Embodiment is demonstrated. The case 7, the heat sink 1, and the wiring substrate 2 are deformed by heat generated during the operation of the semiconductor device. Due to this deformation, a stress is generated at the joint between the electrode terminal 8 fixed to the case 7 and the wiring board 2. The silicone gel 10 covering the electrode terminal 8 does not have enough strength to fix the electrode like a mold resin. For this reason, a large load is applied to the joint between the electrode terminal 8 and the wiring board 2. However, in the conventional structure without the through hole 12 and the recess 11, the soldering strength is determined only by the strength at the bonding interface between the lower surface of the flat portion 8 b and the wiring board 2.

一方、本実施の形態では、貫通孔１２内と凹部１１の底面上に存在するはんだ９がリベットになるため、はんだバルクによるアンカー効果が得られる。例えば変形により図３に示す上下の引張応力が印加された際に、はんだ９のリベットが凹部１１の底面に下向きの抗力を発生させる。従って、はんだ付け強度を向上させ、信頼性において優れた半導体装置を得ることができる。また、単純な貫通孔１２のみではリベットを構成するために、はんだ量を大幅に増加する必要がある。そこで、平面部８ｂの上面に凹部１１を設け、平面部８ｂの下面から凹部１１の底面に達する貫通孔１２を設ける。これにより、大幅なはんだ量の増加なくはんだ付け強度を向上させることができる。   On the other hand, in the present embodiment, since the solder 9 existing in the through hole 12 and on the bottom surface of the recess 11 becomes a rivet, an anchor effect by the solder bulk can be obtained. For example, when the upper and lower tensile stresses shown in FIG. 3 are applied due to deformation, the rivet of the solder 9 generates a downward drag on the bottom surface of the recess 11. Therefore, the soldering strength can be improved and a semiconductor device excellent in reliability can be obtained. Moreover, in order to form a rivet only with the simple through-hole 12, it is necessary to greatly increase the amount of solder. Therefore, the concave portion 11 is provided on the upper surface of the flat portion 8b, and the through hole 12 reaching the bottom surface of the concave portion 11 from the lower surface of the flat portion 8b is provided. Thereby, the soldering strength can be improved without significantly increasing the amount of solder.

実施の形態２．
図４は、本発明の実施の形態２に係る電極端子の平面部を示す断面図である。凹部１１の断面形状は円弧型である。凹部１１の円弧の部分の一部にはんだ９が接合されているが、円弧の部分の全面にはんだ９が接合されていてもよい。 Embodiment 2. FIG.
FIG. 4 is a cross-sectional view showing a planar portion of the electrode terminal according to Embodiment 2 of the present invention. The cross-sectional shape of the recess 11 is an arc shape. Although the solder 9 is joined to a part of the arc portion of the recess 11, the solder 9 may be joined to the entire surface of the arc portion.

パワーモジュールの動作により斜め上下方向に引張応力が印加された際に、凹部１１の円弧の部分でその応力に対抗する抗力を発生させることができる。よって、上下方向だけでなく、斜め方向への応力に対してはんだバルクの強度を付加することができる。   When a tensile stress is applied obliquely in the vertical direction by the operation of the power module, it is possible to generate a drag force against the stress at the arc portion of the recess 11. Therefore, the strength of the solder bulk can be added to the stress in the oblique direction as well as the vertical direction.

実施の形態３．
図５は、本発明の実施の形態３に係る電極端子と配線基板との接合部を示す斜視図である。はんだ付けされる平面部８ｂに発生する応力は特に先端角部で大きくなり、この部分を起点にしてはんだにクラックができ、内部に進行していき、最終的には剥離に至る。そこで、本実施の形態では凹部１１を平面部８ｂの先端角部に設けている。これにより、クラックの起点となる部分の耐剥離強度が大きくなるため、クラックの発生を抑え、はんだ付け強度を向上させることができる。 Embodiment 3 FIG.
FIG. 5 is a perspective view showing a joint portion between the electrode terminal and the wiring board according to Embodiment 3 of the present invention. The stress generated in the flat part 8b to be soldered is particularly large at the corner of the tip, and the solder is cracked starting from this part, progresses to the inside, and finally peels off. Therefore, in the present embodiment, the concave portion 11 is provided at the tip corner of the flat portion 8b. Thereby, since the peeling-proof strength of the part used as the starting point of a crack becomes large, generation | occurrence | production of a crack can be suppressed and soldering intensity | strength can be improved.

実施の形態４．
図６は、本発明の実施の形態４に係る電極端子の平面部を示す断面図である。貫通孔１２の下端部に直線状又は曲面状の面取り１３が施されている。これにより、はんだ９の濡れ上がり性が向上するために、はんだ９が貫通孔１２を通って凹部１１の底面上に達しやすくなり、はんだ９によるリベット形状が安定して形成される。 Embodiment 4 FIG.
FIG. 6 is a cross-sectional view showing a planar portion of an electrode terminal according to Embodiment 4 of the present invention. A linear or curved chamfer 13 is provided at the lower end of the through hole 12. Thereby, since the wet-up property of the solder 9 is improved, the solder 9 easily reaches the bottom surface of the concave portion 11 through the through hole 12, and the rivet shape by the solder 9 is stably formed.

実施の形態５．
図７は、本発明の実施の形態５に係る電極端子と配線基板との接合部を示す斜視図である。図８及び図９は、図７のＩ−ＩＩに沿った断面図である。平面部８ｂの上面三辺にそれぞれ凹部１４が少なくとも１つ設けられている。平面部８ｂの下面と配線基板２がはんだ９により接合されている。はんだ９は平面部８ｂの下面から側面を這い上がって凹部１４の底面上にも延在する。この凹部１４の側面と底面の一部にはんだ９が接合されているが、側面と底面の全面にはんだ９が接合されていてもよい。 Embodiment 5 FIG.
FIG. 7 is a perspective view showing a joint portion between an electrode terminal and a wiring board according to Embodiment 5 of the present invention. 8 and 9 are cross-sectional views taken along the line II of FIG. At least one recess 14 is provided on each of the three upper sides of the flat portion 8b. The lower surface of the flat portion 8 b and the wiring board 2 are joined by solder 9. The solder 9 scoops up the side surface from the lower surface of the flat portion 8 b and extends also on the bottom surface of the recess 14. Although the solder 9 is joined to a part of the side surface and the bottom surface of the recess 14, the solder 9 may be joined to the entire surface of the side surface and the bottom surface.

剥離が発生しやすい平面部８ｂの周辺部において、はんだバルクによるアンカー効果が得られ、はんだ付け強度を向上させることができる。そして、図８に示すように、平面部８ｂを上に向かって引き剥がそうとする応力に対し、凹部１４の底面上のはんだ９が平面部８ｂを上方から押さえることができる。また、平面部８ｂの上面三辺にそれぞれ凹部１４を設けることにより、図９に示すように左右方向の応力に対しても抗力を持たせることができる。   An anchor effect due to the solder bulk can be obtained at the peripheral portion of the flat portion 8b where peeling easily occurs, and the soldering strength can be improved. Then, as shown in FIG. 8, the solder 9 on the bottom surface of the recess 14 can press the flat portion 8b from above against the stress to peel off the flat portion 8b upward. Further, by providing the concave portions 14 on the three sides of the upper surface of the flat portion 8b, it is possible to have a resistance against the stress in the left-right direction as shown in FIG.

実施の形態６．
図１０は、本発明の実施の形態６に係る電極端子の平面部を示す断面図である。本実施の形態において電極端子８と配線基板２との接合部は図７と同様であり、図１０は図７のＩ−ＩＩに沿った断面図に対応する。平面部８ｂの下面から凹部１４の底面に達する円柱状の貫通孔１５が設けられている。はんだ９は貫通孔１５内にも延在する。これにより、はんだ９の濡れ上がり性が向上するために、はんだ９が貫通孔１５を通って凹部１４の底面上に達しやすくなり、はんだ９によるリベット形状が安定して形成される。 Embodiment 6 FIG.
FIG. 10 is a cross-sectional view showing a planar portion of an electrode terminal according to Embodiment 6 of the present invention. In the present embodiment, the joint between the electrode terminal 8 and the wiring board 2 is the same as in FIG. 7, and FIG. 10 corresponds to a cross-sectional view taken along the line II in FIG. A cylindrical through-hole 15 is provided that reaches the bottom surface of the recess 14 from the lower surface of the flat portion 8b. The solder 9 also extends into the through hole 15. Thereby, since the wet-up property of the solder 9 is improved, the solder 9 easily reaches the bottom surface of the recess 14 through the through hole 15, and the rivet shape by the solder 9 is stably formed.

なお、半導体チップ４は、珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成された半導体チップ４は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された半導体チップ４を用いることで、この素子を組み込んだ半導体装置も小型化できる。また、半導体チップ４の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体装置を更に小型化できる。また、半導体チップ４の電力損失が低く高効率であるため、半導体装置を高効率化できる。   The semiconductor chip 4 is not limited to being formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. Since the semiconductor chip 4 formed of such a wide band gap semiconductor has high voltage resistance and allowable current density, it can be miniaturized. By using the miniaturized semiconductor chip 4, a semiconductor device incorporating this element can be miniaturized. Moreover, since the heat resistance of the semiconductor chip 4 is high, the heat dissipating fins of the heat sink can be reduced in size, and the water cooling part can be cooled in the air, so that the semiconductor device can be further reduced in size. In addition, since the semiconductor chip 4 has low power loss and high efficiency, the semiconductor device can be highly efficient.

１ 放熱板、２ 配線基板、４ 半導体チップ、７ ケース、８ 電極端子、８ａ 固定部、８ｂ 平面部、９ はんだ、１１，１４ 凹部、１２，１５ 貫通孔、１３ 面取り DESCRIPTION OF SYMBOLS 1 Heat sink, 2 Wiring board, 4 Semiconductor chip, 7 Case, 8 Electrode terminal, 8a Fixed part, 8b Plane part, 9 Solder, 11, 14 Recessed part, 12, 15 Through hole, 13 Chamfer

Claims (6)

放熱板と、
前記放熱板上に配置された配線基板と、
前記配線基板上に実装された半導体チップと、
前記配線基板及び前記半導体チップを取り囲むように前記放熱板に接合された中空のケースと、
前記ケースに固定される固定部と、前記ケース内において前記配線基板にはんだにより接合された平面部とを有する電極端子とを備え、
前記平面部の上面に凹部が設けられ、
前記平面部の下面から前記凹部の底面に達する貫通孔が設けられ、
前記平面部の前記下面と前記配線基板が前記はんだにより接合され、
前記はんだは前記貫通孔内と前記凹部の前記底面上にも延在することを特徴とする半導体装置。 A heat sink,
A wiring board disposed on the heat sink;
A semiconductor chip mounted on the wiring board;
A hollow case joined to the heat sink so as to surround the wiring board and the semiconductor chip;
An electrode terminal having a fixed portion fixed to the case and a plane portion joined to the wiring board by solder in the case;
A concave portion is provided on the upper surface of the planar portion,
A through hole reaching the bottom surface of the recess from the lower surface of the planar portion is provided,
The lower surface of the planar portion and the wiring board are joined by the solder,
The solder extends in the through hole and also on the bottom surface of the recess. 前記凹部の断面形状は円弧型であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a cross-sectional shape of the recess is an arc shape. 前記凹部は前記平面部の先端角部に設けられていることを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the concave portion is provided at a corner portion of the flat portion. 前記貫通孔の下端部に面取りが施されていることを特徴とする請求項１〜３の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a chamfer is applied to a lower end portion of the through hole. 放熱板と、
前記放熱板上に配置された配線基板と、
前記配線基板上に実装された半導体チップと、
前記配線基板及び前記半導体チップを取り囲むように前記放熱板に接合された中空のケースと、
前記ケースに固定される固定部と、前記ケース内において前記配線基板にはんだにより接合された平面部とを有する電極端子とを備え、
前記平面部の上面三辺にそれぞれ凹部が設けられ、
前記平面部の前記下面と前記配線基板が前記はんだにより接合され、
前記はんだは前記凹部の底面上にも延在することを特徴とする半導体装置。 A heat sink,
A wiring board disposed on the heat sink;
A semiconductor chip mounted on the wiring board;
A hollow case joined to the heat sink so as to surround the wiring board and the semiconductor chip;
An electrode terminal having a fixed portion fixed to the case and a plane portion joined to the wiring board by solder in the case;
Recesses are provided on each of the three upper surfaces of the flat part,
The lower surface of the planar portion and the wiring board are joined by the solder,
The semiconductor device, wherein the solder also extends on a bottom surface of the recess. 前記平面部の下面から前記凹部の底面に達する貫通孔が設けられ、
前記はんだは前記貫通孔内にも延在することを特徴とする請求項５に記載の半導体装置。 A through hole reaching the bottom surface of the recess from the lower surface of the planar portion is provided,
The semiconductor device according to claim 5, wherein the solder also extends into the through hole.
JP2013231312A 2013-11-07 2013-11-07 Semiconductor device Pending JP2015090965A (en)

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