KR101897304B1 - Power module - Google Patents

Power module Download PDF

Info

Publication number
KR101897304B1
KR101897304B1 KR1020130125170A KR20130125170A KR101897304B1 KR 101897304 B1 KR101897304 B1 KR 101897304B1 KR 1020130125170 A KR1020130125170 A KR 1020130125170A KR 20130125170 A KR20130125170 A KR 20130125170A KR 101897304 B1 KR101897304 B1 KR 101897304B1
Authority
KR
South Korea
Prior art keywords
substrate
buffer
heat dissipation
semiconductor element
lower heat
Prior art date
Application number
KR1020130125170A
Other languages
Korean (ko)
Other versions
KR20150045652A (en
Inventor
조희진
이승원
오헌철
김광중
Original Assignee
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지전자 주식회사 filed Critical 엘지전자 주식회사
Priority to KR1020130125170A priority Critical patent/KR101897304B1/en
Publication of KR20150045652A publication Critical patent/KR20150045652A/en
Application granted granted Critical
Publication of KR101897304B1 publication Critical patent/KR101897304B1/en

Links

Images

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Ceramic Engineering (AREA)

Abstract

A power module according to an embodiment of the present invention includes one or more semiconductor elements; A lower heat dissipation substrate directly contacting the lower surface of the semiconductor element; An upper side heat dissipation substrate disposed on the upper side of the semiconductor element; A first buffer interposed between the lower heat dissipation substrate and the upper heat dissipation substrate to allow at least the lower heat dissipation substrate and the upper heat dissipation substrate to be in thermal communication; An upper heat sink placed on the upper surface of the upper heat radiation substrate; And a lower heat sink placed on a lower surface of the lower heat sink.

Description

Power module {Power module}

The present invention relates to a power module.

2. Description of the Related Art In recent years, there has been a growing demand for increasing the output of power converters such as inverters or converters mounted on hybrid vehicles or electric vehicles, and high power output of the power modules constituting the inverters is required. Furthermore, since there is an increasing demand for miniaturization compared to high power, increasing the cooling performance is an important factor in order to satisfy this demand.

In the conventional power module, since the number of wires that can be bonded to electrodes of a semiconductor element is limited when mounting a semiconductor element that generates heat, it can not flexibly cope with high currents, Current loss is proportional to the junction resistance of the device and the length of the wire.

Further, such a wire bonding structure has a disadvantage in that it is unfavorable for applications in which the heat resistance is large because it is a unidirectional heat dissipating structure capable of bonding the heat sink to only the surface to which the wires are not bonded, resulting in high output.

The present invention has been proposed in order to overcome such disadvantages.

According to an aspect of the present invention, there is provided a power module including: at least one semiconductor element; A lower heat dissipation substrate directly contacting the lower surface of the semiconductor element; An upper side heat dissipation substrate disposed on the upper side of the semiconductor element; A first buffer interposed between the lower heat dissipation substrate and the upper heat dissipation substrate to allow at least the lower heat dissipation substrate and the upper heat dissipation substrate to be in thermal communication; An upper heat sink placed on the upper surface of the upper heat radiation substrate; And a lower heat sink placed on the lower surface of the lower heat sink.

The power module may further include a second buffer interposed between an upper surface of the semiconductor element and a lower surface of the upper heat radiation substrate.

The power module may further include an adhesive member interposed between the first buffer, the second buffer, and the contact area between the heat dissipation boards and the semiconductor elements, and the adhesive member may be thermally conductive And may include a thermal interface material (TIM).

The upper and lower heat radiation substrates may include a DBC substrate (Direct Bonded Copper Substrate) in which a copper circuit substrate is bonded to both surfaces of an alumina ceramic substrate.

The contact surfaces of the semiconductor element and either or both of the first buffer and the second buffer are surface-treated with a bondable metal.

The metal used for the surface treatment may include at least one of gold, silver, nickel and tin, and the surface treatment is a vapor deposition treatment.

In addition, the semiconductor device may include an element in which electrodes are formed on one or both surfaces of the upper surface and the lower surface.

The power module may further include an input terminal connected to the lower substrate and electrically connected to the input electrode of the semiconductor element, and an output terminal connected to the lower substrate corresponding to the opposite side of the input terminal, And an output terminal electrically connected to the electrode.

The first buffer connects an input electrode of the semiconductor element to the input terminal to transmit an input signal to the semiconductor element and connects an output electrode of the semiconductor element to the output terminal or the ground terminal. do.

The upper heat radiation substrate and the lower heat radiation substrate are directly brought into close contact with the upper heat sink and the lower heat sink by thermal expansion of the first and second buffers.
In another aspect, a power module according to an embodiment of the present invention includes one or more semiconductor devices; A lower heat dissipation substrate directly contacting the lower surface of the semiconductor element; An upper side heat dissipation substrate disposed on the upper side of the semiconductor element; A buffer interposed between an upper surface of the semiconductor element and a lower surface of the upper heat radiation substrate; An upper heat sink placed on the upper surface of the upper heat radiation substrate; And a lower heat sink placed on the lower surface of the lower heat sink.
The power module may further include an adhesive member interposed between a contact portion between the buffer and the upper heat dissipating substrate and a contact portion between the buffer and the semiconductor device, And may include a thermal interface material (TIM).
The upper and lower heat dissipation boards may include a DBC substrate (Direct Bonded Copper Substrate) in which a copper circuit board is bonded to both surfaces of an alumina ceramic substrate. In addition, any one or both of the semiconductor device and the buffer Is characterized by being surface-treated with a bondable metal.
Further, the metal used for the surface treatment may include at least one of gold, silver, nickel, and tin, and the surface treatment is a vapor deposition treatment.
In addition, the semiconductor device may include an element in which electrodes are formed on one or both surfaces of the upper surface and the lower surface.

The power module according to the embodiment of the present invention having the above-described configuration has the following effects.

First, according to the present invention, since a semiconductor device can be flip chip mounted without wire bonding, heat can be radiated to both sides of the chip, and heat radiation effect is remarkably increased.

Secondly, the surface of a bare chip-shaped semiconductor element is surface-treated with a metal that can be bonded and then directly mounted on a heat-dissipating insulating substrate. This has the advantage of reducing the contact resistance and further simplifying the manufacturing process of the power module There are advantages.

Third, since the buffer is provided on the semiconductor element, the flatness of the substrate can be maintained even if a semiconductor element having a different thickness is mounted.

Fourth, since the buffer is interposed between the substrate and the substrate, there is an advantage that thermal and electrical currents and physical stress are dispersed between the upper substrate and the lower substrate.

Fifth, when the substrate module is bonded to the heat sink, the facing heat sinks are connected to each other using the fastening member, and the heat sinks are directly bonded only by increasing the pressure due to the thermal expansion of the buffers. There is an advantage that the stability is excellent and the assembling process is simplified as compared with the case of using by using.

1 is a perspective view of a power module according to an embodiment of the present invention;
2 is an exploded perspective view of the power module.
3 is a longitudinal sectional view of the power module.

FIG. 1 is a perspective view of a power module according to an embodiment of the present invention, FIG. 2 is an exploded perspective view of the power module, and FIG. 3 is a longitudinal sectional view of the power module.

1 to 3, a power module 10 according to an embodiment of the present invention includes one or more semiconductor elements 11 and a lower heat radiation substrate A first buffer 12 interposed between the lower heat dissipation substrate 14 and the upper heat dissipation substrate 15 and a second buffer 12 interposed between the lower heat dissipation substrate 14 and the upper heat dissipation substrate 15; An upper side heat sink 17 and a lower side heat sink 16 which are respectively attached to the upper surface of the upper heat radiation substrate 15 and the lower surface of the lower heat radiation substrate 14, And an input terminal 18 and an output terminal 19 connected to one end and the other end of the lower heat sink 14, respectively.

The space between the upper side heat sink 17 and the lower side heat sink 16 may be filled with an insulating material 21 including a resin for electrical insulation. The insulating material 21 may include a flexible resin such as a polyimide-based or polyamide-based resin or an epoxy-based resin. The upper heat sink (17) and the lower heat sink (16) are connected by a fastening member (20).

The contact surface between the lower heat dissipation substrate 14 and the semiconductor element 11 and the contact surface between the lower heat dissipation substrate 14 and the first buffer 12 and between the semiconductor element 11 and the second buffer 13, The adhesive member 22 can be applied to the contact surface of the adhesive layer. As the adhesive member 22, a thermally conductive thermal interface material (TIM) having a bonding property such as nano silver and a high thermal conductivity can be applied. The thermally conductive thermal interface material (TIM) significantly reduces the contact resistance between the metal surface of the power semiconductor and the heat spreader, thereby improving the lifetime and reliability of the power module.

The first and second buffers 12 and 13 may include a metal buffer having a high thermal conductivity and a high electrical conductivity, and the upper surface and / or the lower surface may be bonded to the semiconductor element 11 or the heat dissipation Is attached to the substrate (14, 15). Particularly, the first buffer 12 electrically and thermally connects the upper heat dissipation substrate 15 and the lower heat dissipation substrate 14 to form a gap between the signal input terminal 18 and the output terminal 19 Enabling current flow. In other words, the first buffer 12 connects an input electrode of the semiconductor element 11 to the input terminal 18 to transmit an input signal to the semiconductor element 11, and the semiconductor element 11 Is connected to the output terminal 18 or the ground terminal to transmit the output signal of the semiconductor device 11 to the outside of the power module 10 and the output signal from the input terminal 18 So that the current flows smoothly to the terminal (19).

Furthermore, the first buffer 12 may be bonded so that physical stress is dispersed in the upper and lower heat dissipation substrates 15 and 14, and soldering or sintering may be selected and bonded. Of course, the second buffer 13 can also be selected by soldering or sintering using a material having high thermal conductivity and high electrical conductivity. The flatness of the upper and lower heat dissipation boards 14 and 15 is determined by applying a predetermined temperature and pressure to the bonding material (TIM) used as the bonding material 22 by using a material or general solder which is sintered at a predetermined temperature and pressure. Can be ensured.

The second buffer 13 appropriately selects the length depending on the type and thickness of the semiconductor element 11 to be mounted on the lower heat dissipation substrate 14 to secure the flatness of the upper heat dissipation substrate 15 . The upper and lower surfaces of the first and second buffers 12 and 13 are formed by depositing a metal material such as gold, silver, nickel, or tin on the upper and lower surfaces of the semiconductor device 11, And can be joined by a method of soldering or sintering. The plurality of first buffers 12 may be disposed at regular intervals for effective heat transfer and stress dispersion between the upper heat dissipation substrate 15 and the lower heat dissipation substrate 14.

The heat dissipation boards 14 and 15 are formed by directly applying an insulating material to a metal plate and patterning the buffer plates 12 and 13 and the semiconductor elements 11, Can be formed by forming a circuit with a metal material.

In detail, the heat dissipation boards 14 and 15 are heat dissipation boards, and may be a DBC board (Direct Bonded Copper Substrate) in which a copper circuit board is bonded to both surfaces of an alumina ceramic board.

The semiconductor device 11 may include an IGBT, a diode, or the like, and may be mounted in the form of a bare chip. The surface of the bare chip-shaped semiconductor element 11 is surface-treated with a bondable metal. In addition, the contact resistance can be minimized by directly mounting on the heat dissipation boards (14, 15) using the adhesive member (22). The second buffer 13 is bonded to the upper surface of the semiconductor element 11 using the adhesive member 20 so that instantaneous heat can be absorbed and the flatness of the upper heat radiation substrate 15 .

 Further, as described above, the heat radiation substrates 14 and 15 are attached to the upper and lower surfaces of the semiconductor element 11, respectively. For example, when the semiconductor device 11 is an IGBT, the emitter electrode and the gate electrode formed on the lower surface are directly bonded to the lower heat dissipation substrate 14, and the collector electrode formed on the upper surface is connected to the second buffer 13 . When the semiconductor element 11 is a diode, the positive electrode is in direct contact with the lower heat sink 14, and the negative electrode is in direct contact with the second buffer 13. Here, it is noted that the semiconductor element 11 is not only a device having electrodes on upper and lower surfaces as described above, but also a semiconductor device having electrodes on only one surface.

After the semiconductor element 11 and the buffers 12 and 13 are mounted on the upper substrate 15 and the lower substrate 14 as described above, the upper surface of the upper substrate 15 and the lower substrate 14 The heat sinks 16 and 17 are attached to the lower surfaces of the heat sinks 16 and 17, respectively. That is, an upper heat sink 17 is attached to the upper surface of the upper substrate 15, and a lower heat sink 16 is attached to the lower surface of the lower substrate 14. The upper heat sink 17 and the lower heat sink 16 are connected to each other by the fastening member 20 passing therethrough to form one module.

Here, the bonding of the heat sinks 16 and 17 and the heat dissipation boards 14 and 15 must be performed in a vacuum state, and instead of using soldering that can cause shape deformation due to thermal expansion, The pressure increase due to the thermal expansion of the first and second buffers 12 and 13 interposed between the substrate 15 and the lower heat sink 14 can be utilized.

In other words, when the buffers 12 and 13 are thermally expanded, the coupling member 20 catches the upper heat sink 17 and the lower heat sink 16, The upper heat sink 17 and the lower heat sink 16 can be effectively adhered to each other.

3, the heat generated in the semiconductor elements 11 is absorbed by the lower heat radiation substrate (not shown) 14 and the lower heat sink 16 and is discharged through the first buffer 12 and the second buffer 13 to the lower side of the upper heat radiation substrate 15 And flows to the upper side of the power module 10 through the upper side heat sink 17 to be radiated. Accordingly, there is an advantage that the heat dissipation efficiency is increased as compared with the conventional wire-bonding type power module having unidirectional heat radiation flow structure.

Claims (16)

One or more semiconductor elements;
A lower heat dissipation substrate directly contacting the lower surface of the semiconductor element;
An upper side heat dissipation substrate disposed on the upper side of the semiconductor element;
A first buffer interposed between the lower heat dissipation substrate and the upper heat dissipation substrate to allow at least the lower heat dissipation substrate and the upper heat dissipation substrate to be in thermal communication;
A second buffer interposed between an upper surface of the semiconductor element and a lower surface of the upper heat radiation substrate;
An upper heat sink placed on the upper surface of the upper heat radiation substrate; And
And a lower heat sink placed on the lower surface of the lower heat sink,
Wherein the height of the first buffer is higher than the height of the second buffer.
delete The method according to claim 1,
Further comprising an adhesive member interposed between the first buffer, the second buffer, and the contact portions between the heat radiation substrates and the semiconductor elements,
Wherein the adhesive member comprises a thermally conductive thermal interface material (TIM).
The method according to claim 1,
Wherein the upper and lower heat radiation substrates include a DBC substrate (Direct Bonded Copper Substrate) in which a copper circuit substrate is bonded to both surfaces of an alumina ceramic substrate.
The method according to claim 1,
Wherein a contact surface of the semiconductor element and either or both of the first and second buffers is surface-treated with a bondable metal.
6. The method of claim 5,
The metal used for the surface treatment includes at least one of gold, silver, nickel, and tin,
Wherein the surface treatment is a vapor deposition treatment.
The method according to claim 1,
Wherein the semiconductor element includes an element in which electrodes are formed on one or both surfaces of an upper surface and a lower surface.
The method according to claim 1,
An input terminal connected to the lower heat radiation substrate and electrically connected to an input electrode of the semiconductor element,
Further comprising an output terminal connected to the lower heat dissipating substrate opposite to the input terminal and electrically connected to an output electrode of the semiconductor device.
9. The method of claim 8,
Wherein the first buffer comprises:
Wherein an input electrode of the semiconductor device is connected to the input terminal to transmit an input signal to the semiconductor device and an output electrode of the semiconductor device is connected to the output terminal or the ground terminal.
The method according to claim 1,
Wherein the upper heat radiation substrate and the lower heat radiation substrate are in direct contact with the upper heat sink and the lower heat sink due to thermal expansion of the first and second buffers.
delete delete delete delete delete delete
KR1020130125170A 2013-10-21 2013-10-21 Power module KR101897304B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020130125170A KR101897304B1 (en) 2013-10-21 2013-10-21 Power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130125170A KR101897304B1 (en) 2013-10-21 2013-10-21 Power module

Publications (2)

Publication Number Publication Date
KR20150045652A KR20150045652A (en) 2015-04-29
KR101897304B1 true KR101897304B1 (en) 2018-09-10

Family

ID=53037523

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130125170A KR101897304B1 (en) 2013-10-21 2013-10-21 Power module

Country Status (1)

Country Link
KR (1) KR101897304B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021112590A2 (en) * 2019-12-05 2021-06-10 주식회사 아모센스 Power semiconductor module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130270687A1 (en) * 2012-04-13 2013-10-17 Samsung Electro-Mechanics Co., Ltd. Double side cooling power semiconductor module and multi-stacked power semiconductor module package using the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101232034B1 (en) * 2011-04-01 2013-02-22 한국세라믹기술원 Solar cell module integrated with heat radiating package
KR101428146B1 (en) * 2011-12-09 2014-08-08 엘지이노텍 주식회사 Solar cell module and method of fabricating the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130270687A1 (en) * 2012-04-13 2013-10-17 Samsung Electro-Mechanics Co., Ltd. Double side cooling power semiconductor module and multi-stacked power semiconductor module package using the same

Also Published As

Publication number Publication date
KR20150045652A (en) 2015-04-29

Similar Documents

Publication Publication Date Title
US11139278B2 (en) Low parasitic inductance power module and double-faced heat-dissipation low parasitic inductance power module
JP6217756B2 (en) Semiconductor module
KR101388737B1 (en) Semiconductor package, semiconductor module, and mounting structure thereof
JP5965687B2 (en) Power semiconductor module
JP6218898B2 (en) Power semiconductor device
JP2014199829A (en) Semiconductor module and inverter mounting the same
JP6862896B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
JP2019071412A (en) Chip package
CN102593081A (en) Semiconductor device including a heat spreader
JP5895220B2 (en) Manufacturing method of semiconductor device
JP2016018866A (en) Power module
JP2015076562A (en) Power module
CN111261598A (en) Packaging structure and power module applicable to same
JP6003624B2 (en) Semiconductor module
JP2008258547A (en) Semiconductor device, and manufacturing method thereof
JP6504962B2 (en) Power semiconductor device
JP4146888B2 (en) Semiconductor module and method for manufacturing semiconductor module
KR102586458B1 (en) semiconductor sub-assembly and semiconductor power module
CN110676232B (en) Semiconductor device packaging structure, manufacturing method thereof and electronic equipment
JP2021082714A (en) Semiconductor device
KR101897304B1 (en) Power module
JP2013120866A (en) Semiconductor device
JP5619232B2 (en) Semiconductor device and method for manufacturing electrode member
JP6540587B2 (en) Power module
CN210379025U (en) Power device packaging structure

Legal Events

Date Code Title Description
A201 Request for examination
AMND Amendment
E902 Notification of reason for refusal
AMND Amendment
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
AMND Amendment
X701 Decision to grant (after re-examination)
GRNT Written decision to grant