JPS59121841U - Package for IC chip - Google Patents

Package for IC chip

Info

Publication number
JPS59121841U
JPS59121841U JP1487083U JP1487083U JPS59121841U JP S59121841 U JPS59121841 U JP S59121841U JP 1487083 U JP1487083 U JP 1487083U JP 1487083 U JP1487083 U JP 1487083U JP S59121841 U JPS59121841 U JP S59121841U
Authority
JP
Japan
Prior art keywords
package
signal conductor
dielectric substrate
conductor pattern
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1487083U
Other languages
Japanese (ja)
Other versions
JPS6348129Y2 (en
Inventor
高野　勇
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1487083U priority Critical patent/JPS59121841U/en
Publication of JPS59121841U publication Critical patent/JPS59121841U/en
Application granted granted Critical
Publication of JPS6348129Y2 publication Critical patent/JPS6348129Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のＩＣチップ用パッケージの平面を示した
図、第２図は第１図に示した従来のＩＣチップ用パッケ
ージの断面を示した従来のＩＣチップ用パッケージの断
面を示した図である。第３図は、本考案のＩＣチップ用
パッケージの構成を説明するために示した図。第４図は
第３図のＸ−Ｘ′間の断面を示したものである。第５図
は本考案のＩＣチップ用パッケージに外部回路との接続
用リードを備えた態様の平面図を示したものである。 なお、図中の記号はそれぞれ次のものを示している。１
１０１．２１０１川リード、１１０２゜２１０２．３ｉ
０２．４１０２・・・パッケージ本体、１１０３．２１
０６．３１０３．４１０３・・・信号導体用パターン、
１１０４．２１０４・・・ＩＣチップ搭載用金ラうド部
、２１０５．３１０５゜４１０５・・・放熱用スタッド
、２１０６．４１０６・・・ＩＣチップ、２１０７．４
１０７・・・ボンディングワイヤ、２１０８．４１０８
・・・パッケージキャップ、４１０１・・・接地導体パ
ターン。Fig. 1 is a plan view of a conventional IC chip package, and Fig. 2 is a cross-sectional view of the conventional IC chip package shown in Fig. 1. It is. FIG. 3 is a diagram shown to explain the structure of the IC chip package of the present invention. FIG. 4 shows a cross section taken along line XX' in FIG. 3. FIG. 5 shows a plan view of an embodiment in which the IC chip package of the present invention is provided with leads for connection to an external circuit. Note that the symbols in the figure indicate the following, respectively. 1
101.2101 river lead, 1102°2102.3i
02.4102...Package body, 1103.21
06.3103.4103...Signal conductor pattern,
1104.2104...Gold roof part for mounting IC chip, 2105.3105゜4105...Stud for heat dissipation, 2106.4106...IC chip, 2107.4
107...Bonding wire, 2108.4108
...Package cap, 4101...Ground conductor pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フラットパックタイプのＩＣチップ用パッケージにおい
て、パッケージ本体である誘電体基板の表面上に複数本
の信号導体パターンを設け、さらに前記誘電体基板の裏
面全体に接地導体パターンを設け、前記信号導体パター
ンの線路幅をパッケージ本体の中心部に向って連続的に
細（すると共に、前記誘電体基板の厚さを前記信号導体
パターンの幅の変化に比例して連続的に薄くすることに
より前記各信号導体パターンを一定特性インピーダンス
ｚＯのマイクロストリップラインとし、さらにこのＩＣ
チップ用パッケージを回路基板に搭載する時の接続部と
して、前記各信号導体パターンと、パッケージの裏面に
設けられ前記接地導体パターンと電気的に導通している
放熱用スタッドとを用いることを特徴とするＩＣチップ
用パッケージ。In a flat pack type IC chip package, a plurality of signal conductor patterns are provided on the surface of a dielectric substrate that is the package body, and a ground conductor pattern is provided on the entire back surface of the dielectric substrate, and the signal conductor patterns are Each of the signal conductors is made thinner by continuously thinning the line width toward the center of the package body, and by thinning the thickness of the dielectric substrate in proportion to the change in the width of the signal conductor pattern. The pattern is a microstrip line with a constant characteristic impedance zO, and this IC
Each of the signal conductor patterns and a heat dissipation stud provided on the back surface of the package and electrically connected to the ground conductor pattern are used as connection parts when the chip package is mounted on a circuit board. A package for IC chips.
JP1487083U 1983-02-03 1983-02-03 Package for IC chip Granted JPS59121841U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1487083U JPS59121841U (en) 1983-02-03 1983-02-03 Package for IC chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1487083U JPS59121841U (en) 1983-02-03 1983-02-03 Package for IC chip

Publications (2)

Publication Number Publication Date
JPS59121841U true JPS59121841U (en) 1984-08-16
JPS6348129Y2 JPS6348129Y2 (en) 1988-12-12

Family

ID=30146211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1487083U Granted JPS59121841U (en) 1983-02-03 1983-02-03 Package for IC chip

Country Status (1)

Country Link
JP (1) JPS59121841U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636861A (en) * 1986-06-26 1988-01-12 Nec Corp Container for semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155847U (en) * 1982-04-14 1983-10-18 株式会社東芝 microwave integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155847U (en) * 1982-04-14 1983-10-18 株式会社東芝 microwave integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS636861A (en) * 1986-06-26 1988-01-12 Nec Corp Container for semiconductor device

Also Published As

Publication number Publication date
JPS6348129Y2 (en) 1988-12-12

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